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https://github.com/intel/llvm.git
synced 2026-01-13 19:08:21 +08:00
48ae32a33b
Summary: Refactor architecture-specific code out of llvm into llvm-bolt. Introduce MCPlusBuilder, a class that is taking over MCInstrAnalysis responsibilities, i.e. creating, analyzing, and modifying instructions. To access the builder use BC->MIB, i.e. substitute MIA with MIB. MIB is an acronym for MCInstBuilder, that's what MCPlusBuilder used to be. The name stuck, and I find it better than MPB. Instructions are still MCInst, and a bunch of BOLT-specific code still lives in LLVM, but the staff under Target/* is significantly reduced. (cherry picked from FBD7300101)
385 lines
11 KiB
C++
385 lines
11 KiB
C++
//===- MCPlusBuilder.cpp - main interface for MCPlus-level instructions ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Create/analyze/modify instructions at MC+ level.
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//
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//===----------------------------------------------------------------------===//
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#include "MCPlusBuilder.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <cstdint>
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#include <queue>
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#define DEBUG_TYPE "mcplus"
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using namespace llvm;
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using namespace bolt;
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bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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return Analysis->evaluateBranch(Inst, Addr, Size, Target);
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}
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namespace {
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const MCLandingPad *findLandingPad(const MCInst &Inst) {
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for (unsigned I = Inst.getNumOperands(); I > 0; --I) {
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const auto &Op = Inst.getOperand(I - 1);
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if (Op.isLandingPad()) {
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return Op.getLandingPad();
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}
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}
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return nullptr;
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}
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}
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bool MCPlusBuilder::hasEHInfo(const MCInst &Inst) const {
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return findLandingPad(Inst) != nullptr;
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}
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MCLandingPad MCPlusBuilder::getEHInfo(const MCInst &Inst) const {
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const MCSymbol *LPSym = nullptr;
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uint64_t Action = 0;
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if (isCall(Inst)) {
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if (auto LP = findLandingPad(Inst)) {
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std::tie(LPSym, Action) = *LP;
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}
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}
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return std::make_pair(LPSym, Action);
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}
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// Add handler and action info for call instruction.
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void MCPlusBuilder::addEHInfo(MCInst &Inst,
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const MCLandingPad &LP,
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MCContext *Ctx) const {
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if (isCall(Inst)) {
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assert(!hasEHInfo(Inst));
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Inst.addOperand(
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MCOperand::createLandingPad(new (*Ctx) MCLandingPad(LP)));
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}
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}
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int64_t MCPlusBuilder::getGnuArgsSize(const MCInst &Inst) const {
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for (unsigned I = Inst.getNumOperands(); I > 0; --I) {
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const auto &Op = Inst.getOperand(I - 1);
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if (Op.isGnuArgsSize()) {
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return Op.getGnuArgsSize();
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}
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}
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return -1LL;
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}
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void MCPlusBuilder::addGnuArgsSize(MCInst &Inst, int64_t GnuArgsSize) const {
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assert(GnuArgsSize >= 0 && "cannot set GNU_args_size to negative value");
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assert(getGnuArgsSize(Inst) == -1LL && "GNU_args_size already set");
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assert(isInvoke(Inst) && "GNU_args_size can only be set for invoke");
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Inst.addOperand(MCOperand::createGnuArgsSize(GnuArgsSize));
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}
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uint64_t MCPlusBuilder::getJumpTable(const MCInst &Inst) const {
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for (unsigned I = Inst.getNumOperands(); I > 0; --I) {
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const auto &Op = Inst.getOperand(I - 1);
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if (Op.isJumpTable()) {
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return Op.getJumpTable();
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}
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}
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return 0;
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}
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bool MCPlusBuilder::setJumpTable(MCContext *Ctx, MCInst &Inst, uint64_t Value,
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uint16_t IndexReg) const {
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if (!isIndirectBranch(Inst))
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return false;
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assert(getJumpTable(Inst) == 0 && "jump table already set");
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Inst.addOperand(MCOperand::createJumpTable(Value));
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addAnnotation<>(Ctx, Inst, "JTIndexReg", IndexReg);
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return true;
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}
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Optional<uint64_t>
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MCPlusBuilder::getConditionalTailCall(const MCInst &Inst) const {
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for (unsigned I = Inst.getNumOperands(); I > 0; --I) {
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const auto &Op = Inst.getOperand(I - 1);
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if (Op.isConditionalTailCall()) {
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return Op.getConditionalTailCall();
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}
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}
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return NoneType();
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}
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bool
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MCPlusBuilder::setConditionalTailCall(MCInst &Inst, uint64_t Dest) const {
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if (!isConditionalBranch(Inst))
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return false;
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for (unsigned I = Inst.getNumOperands(); I > 0; --I) {
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auto &Op = Inst.getOperand(I - 1);
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if (Op.isConditionalTailCall()) {
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Op.setConditionalTailCall(Dest);
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return true;
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}
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}
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Inst.addOperand(MCOperand::createConditionalTailCall(Dest));
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return true;
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}
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bool MCPlusBuilder::unsetConditionalTailCall(MCInst &Inst) const {
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for (auto OpI = Inst.begin(), OpE = Inst.end(); OpI != OpE; ++OpI) {
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if (OpI->isConditionalTailCall()) {
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Inst.erase(OpI);
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return true;
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}
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}
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return false;
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}
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namespace {
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unsigned findAnnotationIndex(const MCInst &Inst, StringRef Name) {
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for (unsigned I = Inst.getNumOperands(); I > 0; --I) {
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const auto& Op = Inst.getOperand(I - 1);
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if (Op.isAnnotation() && Op.getAnnotation()->getName() == Name) {
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return I - 1;
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}
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}
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return Inst.getNumOperands();
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}
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}
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bool MCPlusBuilder::hasAnnotation(const MCInst &Inst, StringRef Name) const {
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return findAnnotationIndex(Inst, Name) < Inst.getNumOperands();
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}
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bool MCPlusBuilder::removeAnnotation(MCInst &Inst, StringRef Name) const {
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const auto Idx = findAnnotationIndex(Inst, Name);
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if (Idx < Inst.getNumOperands()) {
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auto *Annotation = Inst.getOperand(Idx).getAnnotation();
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auto Itr = AnnotationPool.find(Annotation);
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if (Itr != AnnotationPool.end()) {
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AnnotationPool.erase(Itr);
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Annotation->~MCAnnotation();
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}
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Inst.erase(Inst.begin() + Idx);
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return true;
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}
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return false;
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}
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void MCPlusBuilder::removeAllAnnotations(MCInst &Inst) const {
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for (auto Idx = Inst.getNumOperands(); Idx > 0; --Idx) {
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auto &Op = Inst.getOperand(Idx - 1);
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if (Op.isAnnotation()) {
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auto *Annotation = Op.getAnnotation();
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auto Itr = AnnotationPool.find(Annotation);
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if (Itr != AnnotationPool.end()) {
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AnnotationPool.erase(Itr);
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Annotation->~MCAnnotation();
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}
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Inst.erase(Inst.begin() + Idx - 1);
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}
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}
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}
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bool MCPlusBuilder::renameAnnotation(MCInst &Inst,
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StringRef Before,
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StringRef After) const {
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const auto Idx = findAnnotationIndex(Inst, Before);
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if (Idx >= Inst.getNumOperands()) {
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return false;
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}
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auto *Annotation = Inst.getOperand(Idx).getAnnotation();
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auto PooledName = AnnotationNames.intern(After);
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AnnotationNameRefs.insert(PooledName);
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Annotation->setName(*PooledName);
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return true;
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}
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const MCAnnotation *
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MCPlusBuilder::getAnnotation(const MCInst &Inst, StringRef Name) const {
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const auto Idx = findAnnotationIndex(Inst, Name);
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assert(Idx < Inst.getNumOperands());
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return Inst.getOperand(Idx).getAnnotation();
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}
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void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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}
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const auto &Operand = Inst.getOperand(I);
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assert(Operand.isReg());
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Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/false);
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}
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}
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void MCPlusBuilder::getTouchedRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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}
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const auto *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
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}
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/false);
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}
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}
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void MCPlusBuilder::getWrittenRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
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}
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const auto &Operand = Inst.getOperand(I);
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assert(Operand.isReg());
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Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
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}
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}
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void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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}
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
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}
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}
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const BitVector &
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MCPlusBuilder::getAliases(MCPhysReg Reg,
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bool OnlySmaller) const {
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// AliasMap caches a mapping of registers to the set of registers that
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// alias (are sub or superregs of itself, including itself).
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static std::vector<BitVector> AliasMap;
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static std::vector<MCPhysReg> SuperReg;
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if (AliasMap.size() > 0) {
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if (OnlySmaller)
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return AliasMap[Reg];
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return AliasMap[SuperReg[Reg]];
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}
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// Build alias map
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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BitVector BV(RegInfo->getNumRegs(), false);
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BV.set(I);
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AliasMap.emplace_back(std::move(BV));
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SuperReg.emplace_back(I);
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}
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std::queue<MCPhysReg> Worklist;
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// Propagate alias info upwards
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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Worklist.push(I);
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}
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while (!Worklist.empty()) {
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MCPhysReg I = Worklist.front();
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Worklist.pop();
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for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
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AliasMap[I] |= AliasMap[*SI];
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}
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for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
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Worklist.push(*SI);
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}
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}
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// Propagate parent reg downwards
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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Worklist.push(I);
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}
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while (!Worklist.empty()) {
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MCPhysReg I = Worklist.front();
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Worklist.pop();
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for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
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SuperReg[*SI] = SuperReg[I];
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Worklist.push(*SI);
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}
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}
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DEBUG({
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dbgs() << "Dumping reg alias table:\n";
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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dbgs() << "Reg " << I << ": ";
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const BitVector &BV = AliasMap[SuperReg[I]];
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int Idx = BV.find_first();
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while (Idx != -1) {
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dbgs() << Idx << " ";
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Idx = BV.find_next(Idx);
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}
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dbgs() << "\n";
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}
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});
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if (OnlySmaller)
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return AliasMap[Reg];
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return AliasMap[SuperReg[Reg]];
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}
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uint8_t
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MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
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// SizeMap caches a mapping of registers to their sizes
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static std::vector<uint8_t> SizeMap;
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if (SizeMap.size() > 0) {
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return SizeMap[Reg];
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}
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SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
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// Build size map
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for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
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++I) {
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for (MCPhysReg Reg : *I) {
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SizeMap[Reg] = I->getSize();
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}
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}
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return SizeMap[Reg];
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}
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