mirror of
https://github.com/intel/llvm.git
synced 2026-01-13 19:08:21 +08:00
48ae32a33b
Summary: Refactor architecture-specific code out of llvm into llvm-bolt. Introduce MCPlusBuilder, a class that is taking over MCInstrAnalysis responsibilities, i.e. creating, analyzing, and modifying instructions. To access the builder use BC->MIB, i.e. substitute MIA with MIB. MIB is an acronym for MCInstBuilder, that's what MCPlusBuilder used to be. The name stuck, and I find it better than MPB. Instructions are still MCInst, and a bunch of BOLT-specific code still lives in LLVM, but the staff under Target/* is significantly reduced. (cherry picked from FBD7300101)
431 lines
14 KiB
C++
431 lines
14 KiB
C++
//===--- Passes/RegReAssign.cpp -------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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#include "DataflowAnalysis.h"
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#include "DataflowInfoManager.h"
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#include "RegReAssign.h"
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#include <numeric>
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#define DEBUG_TYPE "regreassign"
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using namespace llvm;
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namespace opts {
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extern cl::OptionCategory BoltOptCategory;
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extern cl::opt<bool> UpdateDebugSections;
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extern bool shouldProcess(const bolt::BinaryFunction &Function);
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static cl::opt<bool>
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AggressiveReAssign("use-aggr-reg-reassign",
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cl::desc("use register liveness analysis to try to find more opportunities "
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"for -reg-reassign optimization"),
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cl::init(false),
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cl::ZeroOrMore,
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cl::cat(BoltOptCategory));
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}
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namespace llvm {
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namespace bolt {
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void RegReAssign::swap(BinaryContext &BC, BinaryFunction &Function, MCPhysReg A,
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MCPhysReg B) {
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const BitVector &AliasA = BC.MIB->getAliases(A, false);
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const BitVector &AliasB = BC.MIB->getAliases(B, false);
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// Regular instructions
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for (auto &BB : Function) {
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for (auto &Inst : BB) {
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for (int I = 0, E = Inst.getNumPrimeOperands(); I != E; ++I) {
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auto &Operand = Inst.getOperand(I);
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if (!Operand.isReg())
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continue;
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auto Reg = Operand.getReg();
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if (AliasA.test(Reg)) {
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Operand.setReg(BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg)));
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--StaticBytesSaved;
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DynBytesSaved -= BB.getKnownExecutionCount();
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continue;
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}
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if (!AliasB.test(Reg))
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continue;
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Operand.setReg(BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg)));
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++StaticBytesSaved;
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DynBytesSaved += BB.getKnownExecutionCount();
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}
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}
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}
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// CFI
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DenseSet<const MCCFIInstruction *> Changed;
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for (auto &BB : Function) {
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for (auto &Inst : BB) {
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if (!BC.MIB->isCFI(Inst))
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continue;
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auto *CFI = Function.getCFIFor(Inst);
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if (Changed.count(CFI))
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continue;
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Changed.insert(CFI);
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switch (CFI->getOperation()) {
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case MCCFIInstruction::OpRegister: {
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const auto CFIReg2 = CFI->getRegister2();
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const MCPhysReg Reg2 = BC.MRI->getLLVMRegNum(CFIReg2, /*isEH=*/false);
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if (AliasA.test(Reg2)) {
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CFI->setRegister2(BC.MRI->getDwarfRegNum(
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BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg2)), false));
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} else if (AliasB.test(Reg2)) {
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CFI->setRegister2(BC.MRI->getDwarfRegNum(
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BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg2)), false));
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}
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}
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// Fall-through
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case MCCFIInstruction::OpUndefined:
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case MCCFIInstruction::OpDefCfa:
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case MCCFIInstruction::OpOffset:
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case MCCFIInstruction::OpRestore:
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case MCCFIInstruction::OpSameValue:
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case MCCFIInstruction::OpDefCfaRegister:
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case MCCFIInstruction::OpRelOffset:
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case MCCFIInstruction::OpExpression:
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case MCCFIInstruction::OpValExpression: {
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const auto CFIReg = CFI->getRegister();
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const MCPhysReg Reg = BC.MRI->getLLVMRegNum(CFIReg, /*isEH=*/false);
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if (AliasA.test(Reg)) {
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CFI->setRegister(BC.MRI->getDwarfRegNum(
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BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg)), false));
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} else if (AliasB.test(Reg)) {
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CFI->setRegister(BC.MRI->getDwarfRegNum(
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BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg)), false));
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}
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break;
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}
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default:
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break;
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}
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}
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}
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}
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void RegReAssign::rankRegisters(BinaryContext &BC, BinaryFunction &Function) {
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std::fill(RegScore.begin(), RegScore.end(), 0);
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std::fill(RankedRegs.begin(), RankedRegs.end(), 0);
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for (auto &BB : Function) {
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for (auto &Inst : BB) {
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const bool CannotUseREX = BC.MIB->cannotUseREX(Inst);
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const auto &Desc = BC.MII->get(Inst.getOpcode());
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// Disallow substituitions involving regs in implicit uses lists
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const auto *ImplicitUses = Desc.getImplicitUses();
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while (ImplicitUses && *ImplicitUses) {
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const size_t RegEC =
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BC.MIB->getAliases(*ImplicitUses, false).find_first();
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RegScore[RegEC] =
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std::numeric_limits<decltype(RegScore)::value_type>::min();
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++ImplicitUses;
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}
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// Disallow substituitions involving regs in implicit defs lists
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const auto *ImplicitDefs = Desc.getImplicitDefs();
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while (ImplicitDefs && *ImplicitDefs) {
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const size_t RegEC =
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BC.MIB->getAliases(*ImplicitDefs, false).find_first();
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RegScore[RegEC] =
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std::numeric_limits<decltype(RegScore)::value_type>::min();
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++ImplicitDefs;
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}
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for (int I = 0, E = Inst.getNumPrimeOperands(); I != E; ++I) {
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const auto &Operand = Inst.getOperand(I);
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if (!Operand.isReg())
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continue;
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if (Desc.getOperandConstraint(I, MCOI::TIED_TO) != -1)
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continue;
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auto Reg = Operand.getReg();
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size_t RegEC = BC.MIB->getAliases(Reg, false).find_first();
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if (RegEC == 0)
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continue;
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// Disallow substituitions involving regs in instrs that cannot use REX
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if (CannotUseREX) {
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RegScore[RegEC] =
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std::numeric_limits<decltype(RegScore)::value_type>::min();
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continue;
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}
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// Unsupported substitution, cannot swap BH with R* regs, bail
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if (BC.MIB->isUpper8BitReg(Reg) && ClassicCSR.test(Reg)) {
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RegScore[RegEC] =
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std::numeric_limits<decltype(RegScore)::value_type>::min();
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continue;
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}
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RegScore[RegEC] += BB.getKnownExecutionCount();
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}
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}
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}
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std::iota(RankedRegs.begin(), RankedRegs.end(), 0); // 0, 1, 2, 3...
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std::sort(RankedRegs.begin(), RankedRegs.end(),
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[&](size_t A, size_t B) { return RegScore[A] > RegScore[B]; });
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DEBUG({
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for (auto Reg : RankedRegs) {
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if (RegScore[Reg] == 0)
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continue;
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dbgs() << Reg << " ";
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if (RegScore[Reg] > 0)
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dbgs() << BC.MRI->getName(Reg) << ": " << RegScore[Reg] << "\n";
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else
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dbgs() << BC.MRI->getName(Reg) << ": (blacklisted)\n";
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}
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});
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}
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void RegReAssign::aggressivePassOverFunction(BinaryContext &BC,
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BinaryFunction &Function) {
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rankRegisters(BC, Function);
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// Bail early if our registers are all black listed, before running expensive
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// analysis passes
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bool Bail = true;
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int64_t LowScoreClassic = std::numeric_limits<int64_t>::max();
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for (int J = ClassicRegs.find_first(); J != -1;
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J = ClassicRegs.find_next(J)) {
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if (RegScore[J] <= 0)
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continue;
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Bail = false;
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if (RegScore[J] < LowScoreClassic)
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LowScoreClassic = RegScore[J];
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}
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if (Bail)
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return;
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BitVector Extended = ClassicRegs;
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Extended.flip();
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Extended &= GPRegs;
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Bail = true;
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int64_t HighScoreExtended = 0;
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for (int J = Extended.find_first(); J != -1; J = Extended.find_next(J)) {
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if (RegScore[J] <= 0)
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continue;
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Bail = false;
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if (RegScore[J] > HighScoreExtended)
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HighScoreExtended = RegScore[J];
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}
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// Also bail early if there is no profitable substitution even if we assume
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// all registers can be exchanged
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if (Bail || (LowScoreClassic << 1) >= HighScoreExtended)
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return;
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// -- expensive pass -- determine all regs alive during func start
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DataflowInfoManager Info(BC, Function, RA.get(), nullptr);
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auto AliveAtStart = *Info.getLivenessAnalysis().getStateAt(
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ProgramPoint::getFirstPointAt(*Function.begin()));
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for (auto &BB : Function) {
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if (BB.pred_size() == 0)
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AliveAtStart |= *Info.getLivenessAnalysis().getStateAt(
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ProgramPoint::getFirstPointAt(BB));
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}
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// Mark frame pointer alive because of CFI
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AliveAtStart |= BC.MIB->getAliases(BC.MIB->getFramePointer(), false);
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// Never touch return registers
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BC.MIB->getDefaultLiveOut(AliveAtStart);
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// Try swapping more profitable options first
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auto Begin = RankedRegs.begin();
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auto End = std::prev(RankedRegs.end());
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while (Begin != End) {
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MCPhysReg ClassicReg = *End;
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if (!ClassicRegs[ClassicReg] || RegScore[ClassicReg] <= 0) {
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--End;
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continue;
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}
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MCPhysReg ExtReg = *Begin;
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if (!Extended[ExtReg] || RegScore[ExtReg] <= 0) {
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++Begin;
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continue;
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}
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if (RegScore[ClassicReg] << 1 >= RegScore[ExtReg]) {
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DEBUG(dbgs() << " Ending at " << BC.MRI->getName(ClassicReg) << " with "
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<< BC.MRI->getName(ExtReg)
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<< " because exchange is not profitable\n");
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break;
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}
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BitVector AnyAliasAlive = AliveAtStart;
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AnyAliasAlive &= BC.MIB->getAliases(ClassicReg);
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if (AnyAliasAlive.any()) {
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DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg) << " with "
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<< BC.MRI->getName(ExtReg)
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<< " because classic reg is alive\n");
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--End;
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continue;
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}
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AnyAliasAlive = AliveAtStart;
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AnyAliasAlive &= BC.MIB->getAliases(ExtReg);
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if (AnyAliasAlive.any()) {
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DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg) << " with "
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<< BC.MRI->getName(ExtReg)
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<< " because extended reg is alive\n");
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++Begin;
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continue;
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}
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// Opportunity detected. Swap.
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DEBUG(dbgs() << "\n ** Swapping " << BC.MRI->getName(ClassicReg) << " with "
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<< BC.MRI->getName(ExtReg) << "\n\n");
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swap(BC, Function, ClassicReg, ExtReg);
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FuncsChanged.insert(&Function);
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++Begin;
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if (Begin == End)
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break;
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--End;
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}
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}
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bool RegReAssign::conservativePassOverFunction(BinaryContext &BC,
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BinaryFunction &Function) {
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rankRegisters(BC, Function);
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// Try swapping R12, R13, R14 or R15 with RBX (we work with all callee-saved
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// regs except RBP)
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MCPhysReg Candidate = 0;
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for (int J = ExtendedCSR.find_first(); J != -1;
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J = ExtendedCSR.find_next(J)) {
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if (RegScore[J] > RegScore[Candidate])
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Candidate = J;
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}
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if (!Candidate || RegScore[Candidate] < 0)
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return false;
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// Check if our classic callee-saved reg (RBX is the only one) has lower
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// score / utilization rate
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MCPhysReg RBX = 0;
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for (int I = ClassicCSR.find_first(); I != -1; I = ClassicCSR.find_next(I)) {
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auto ScoreRBX = RegScore[I];
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if (ScoreRBX <= 0)
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continue;
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if (RegScore[Candidate] > (ScoreRBX + 10)) {
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RBX = I;
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}
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}
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if (!RBX)
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return false;
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DEBUG(dbgs() << "\n ** Swapping " << BC.MRI->getName(RBX) << " with "
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<< BC.MRI->getName(Candidate) << "\n\n");
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swap(BC, Function, RBX, Candidate);
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FuncsChanged.insert(&Function);
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return true;
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}
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void RegReAssign::setupAggressivePass(BinaryContext &BC,
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std::map<uint64_t, BinaryFunction> &BFs) {
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setupConservativePass(BC, BFs);
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CG.reset(new BinaryFunctionCallGraph(buildCallGraph(BC, BFs)));
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RA.reset(new RegAnalysis(BC, BFs, *CG));
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GPRegs = BitVector(BC.MRI->getNumRegs(), false);
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BC.MIB->getGPRegs(GPRegs);
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}
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void RegReAssign::setupConservativePass(
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BinaryContext &BC, std::map<uint64_t, BinaryFunction> &BFs) {
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// Set up constant bitvectors used throughout this analysis
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ClassicRegs = BitVector(BC.MRI->getNumRegs(), false);
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CalleeSaved = BitVector(BC.MRI->getNumRegs(), false);
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ClassicCSR = BitVector(BC.MRI->getNumRegs(), false);
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ExtendedCSR = BitVector(BC.MRI->getNumRegs(), false);
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// Never consider the frame pointer
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BC.MIB->getClassicGPRegs(ClassicRegs);
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ClassicRegs.flip();
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ClassicRegs |= BC.MIB->getAliases(BC.MIB->getFramePointer(), false);
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ClassicRegs.flip();
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BC.MIB->getCalleeSavedRegs(CalleeSaved);
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ClassicCSR |= ClassicRegs;
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ClassicCSR &= CalleeSaved;
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BC.MIB->getClassicGPRegs(ClassicRegs);
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ExtendedCSR |= ClassicRegs;
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ExtendedCSR.flip();
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ExtendedCSR &= CalleeSaved;
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DEBUG({
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RegStatePrinter P(BC);
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dbgs() << "Starting register reassignment\nClassicRegs: ";
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P.print(dbgs(), ClassicRegs);
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dbgs() << "\nCalleeSaved: ";
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P.print(dbgs(), CalleeSaved);
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dbgs() << "\nClassicCSR: ";
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P.print(dbgs(), ClassicCSR);
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dbgs() << "\nExtendedCSR: ";
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P.print(dbgs(), ExtendedCSR);
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dbgs() << "\n";
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});
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}
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void RegReAssign::runOnFunctions(BinaryContext &BC,
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std::map<uint64_t, BinaryFunction> &BFs,
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std::set<uint64_t> &LargeFunctions) {
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RegScore = std::vector<int64_t>(BC.MRI->getNumRegs(), 0);
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RankedRegs = std::vector<size_t>(BC.MRI->getNumRegs(), 0);
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if (opts::AggressiveReAssign)
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setupAggressivePass(BC, BFs);
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else
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setupConservativePass(BC, BFs);
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for (auto &I : BFs) {
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auto &Function = I.second;
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if (!Function.isSimple() || !opts::shouldProcess(Function))
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continue;
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DEBUG(dbgs() << "====================================\n");
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DEBUG(dbgs() << " - " << Function.getPrintName() << "\n");
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if (!conservativePassOverFunction(BC, Function) &&
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opts::AggressiveReAssign) {
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aggressivePassOverFunction(BC, Function);
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DEBUG({
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if (FuncsChanged.count(&Function)) {
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dbgs() << "Aggressive pass successful on " << Function.getPrintName()
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<< "\n";
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}
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});
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}
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}
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if (FuncsChanged.empty()) {
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outs() << "BOLT-INFO: Reg Reassignment Pass: no changes were made.\n";
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return;
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}
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if (opts::UpdateDebugSections) {
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outs() << "BOLT-WARNING: You used -reg-reassign and -update-debug-sections."
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<< " Some registers were changed but associated AT_LOCATION for "
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<< "impacted variables were NOT updated! This operation is "
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<< "currently unsupported by BOLT.\n";
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}
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outs() << "BOLT-INFO: Reg Reassignment Pass Stats:\n";
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outs() << "\t " << FuncsChanged.size() << " functions affected.\n";
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outs() << "\t " << StaticBytesSaved << " static bytes saved.\n";
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outs() << "\t " << DynBytesSaved << " dynamic bytes saved.\n";
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}
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}
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}
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