Ian Bearman 0816b96a10 Allow same memory space for SRC and DST of dma_start operations ...

This change allows the SRC and DST of dma_start operations to be located in the
    same memory space. This applies to both the Affine dialect and Memref dialect
    versions of these Ops. The documention has been updated to reflect this by
    explicitly stating overlapping memory locations are not supported (undefined
    behavior).

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D102274

2021-05-14 10:40:15 -07:00

..

mlir

Allow same memory space for SRC and DST of dma_start operations

2021-05-14 10:40:15 -07:00

mlir-c

[mlir][sparse][capi][python] add sparse tensor passes

2021-05-12 16:40:50 -07:00