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bab3568105
This patch includes tests where we actually need to adjust the CHECK lines for SCEV based code generation. Besides these adjustments we add explicit calls to -polly-codegen-scev=[true|false] and make sure we test both cases. llvm-svn: 222112
66 lines
2.7 KiB
LLVM
66 lines
2.7 KiB
LLVM
; RUN: opt %loadPolly -polly-codegen-isl -polly-ast-detect-parallel -polly-codegen-scev=false -S < %s | FileCheck %s
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; RUN: opt %loadPolly -polly-codegen-isl -polly-ast-detect-parallel -polly-codegen-scev=true -S < %s | FileCheck %s
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;
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; Check that we mark multiple parallel loops correctly including the memory instructions.
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;
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; CHECK-DAG: %polly.loop_cond[[COuter:[0-9]*]] = icmp sle i64 %polly.indvar{{[0-9]*}}, 1022
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; CHECK-DAG: br i1 %polly.loop_cond[[COuter]], label %polly.loop_header{{[0-9]*}}, label %polly.loop_exit{{[0-9]*}}, !llvm.loop ![[IDOuter:[0-9]*]]
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;
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; CHECK-DAG: %polly.loop_cond[[CInner:[0-9]*]] = icmp sle i64 %polly.indvar{{[0-9]*}}, 510
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; CHECK-DAG: br i1 %polly.loop_cond[[CInner]], label %polly.loop_header{{[0-9]*}}, label %polly.loop_exit{{[0-9]*}}, !llvm.loop ![[IDInner:[0-9]*]]
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;
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; CHECK-DAG: store i32 %{{[a-z_0-9]*}}, i32* %{{[a-z_0-9]*}}, {{[ ._!,a-zA-Z0-9]*}}, !llvm.mem.parallel_loop_access !4
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;
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; CHECK-DAG: ![[IDOuter]] = metadata !{metadata ![[IDOuter]]}
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; CHECK-DAG: ![[IDInner]] = metadata !{metadata ![[IDInner]]}
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; CHECK-DAG: !4 = metadata !{metadata ![[IDOuter]], metadata ![[IDInner]]}
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;
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; void jd(int *A) {
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; for (int i = 0; i < 1024; i++)
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; for (int j = 0; j < 512; j++)
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; A[i * 512 + j] = i + j;
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; }
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @jd(i32* %A) {
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entry:
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br label %for.cond
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for.cond: ; preds = %for.inc5, %entry
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%indvars.iv3 = phi i64 [ %indvars.iv.next4, %for.inc5 ], [ 0, %entry ]
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%exitcond6 = icmp ne i64 %indvars.iv3, 1024
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br i1 %exitcond6, label %for.body, label %for.end7
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for.body: ; preds = %for.cond
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br label %for.cond1
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for.cond1: ; preds = %for.inc, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %for.body ]
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%exitcond = icmp ne i64 %indvars.iv, 512
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br i1 %exitcond, label %for.body3, label %for.end
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for.body3: ; preds = %for.cond1
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%tmp = add nsw i64 %indvars.iv3, %indvars.iv
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%tmp7 = shl nsw i64 %indvars.iv3, 9
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%tmp8 = add nsw i64 %tmp7, %indvars.iv
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%arrayidx = getelementptr inbounds i32* %A, i64 %tmp8
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%tmp9 = trunc i64 %tmp to i32
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store i32 %tmp9, i32* %arrayidx, align 4
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br label %for.inc
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for.inc: ; preds = %for.body3
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %for.cond1
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for.end: ; preds = %for.cond1
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br label %for.inc5
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for.inc5: ; preds = %for.end
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%indvars.iv.next4 = add nuw nsw i64 %indvars.iv3, 1
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br label %for.cond
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for.end7: ; preds = %for.cond
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ret void
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}
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