intel/llvm

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History

Chao Chen 75524dee18 [mlir][xegpu] Relax rank restriction of TensorDescType (#145916 )

2025-07-09 19:40:24 -05:00

..

benchmark/python

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[MLIR][IRDL][CMake] CMake fixes for cross-compilation (#145672 )

2025-07-04 13:04:33 +02:00

[MLIR][Linalg] Remove elemwise_unary and elemwise_binary (#147082 )

2025-07-07 12:33:55 +01:00

[mlir][examples] Use {} instead of std::nullopt (NFC) (#146949 )

2025-07-03 15:49:43 -07:00

[mlir][xegpu] Relax rank restriction of TensorDescType (#145916 )

2025-07-09 19:40:24 -05:00

[mlir][xegpu] Relax rank restriction of TensorDescType (#145916 )

2025-07-09 19:40:24 -05:00

[MLIR][Transform] Introduce transform.tune.knob op (#146732 )

2025-07-08 11:00:34 +01:00

[mlir][xegpu] Relax rank restriction of TensorDescType (#145916 )

2025-07-09 19:40:24 -05:00

[mlir-tblgen] Emit named operand indices (#146839 )

2025-07-04 17:15:11 +02:00

[mlir][AffineExpr] Order arguments in the commutative affine exprs (#146895 )

2025-07-04 23:34:07 +03:00

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.clang-format

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.clang-tidy

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CMakeLists.txt

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LICENSE.TXT

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README.md

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README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.