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When using vec_load/store_len_r with an immediate length operand of 16 or larger, LLVM will currently emit an VLRL/VSTRL instruction with that immediate. This creates a valid encoding (which should be supported by the assembler), but always traps at runtime. This patch fixes this by not creating VLRL/VSTRL in those cases. This would result in loading the length into a register and calling VLRLR/VSTRLR instead. However, these operations with a length of 15 or larger are in fact simply equivalent to a full vector load or store. And in fact the same holds true for vec_load/store_len as well. Therefore, add a DAGCombine rule to replace those operations with plain vector loads or stores if the length is known at compile time and equal or larger to 15.
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