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67d0d7ac0a
The patch introduces the required changes to update the pass declarations and definitions to use the new autogenerated files and allow dropping the old infrastructure. Reviewed By: mehdi_amini, rriddle Differential Review: https://reviews.llvm.org/D132838
334 lines
14 KiB
C++
334 lines
14 KiB
C++
//===-- RewriteLoop.cpp ---------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "flang/Optimizer/Dialect/FIRDialect.h"
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#include "flang/Optimizer/Dialect/FIROps.h"
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#include "flang/Optimizer/Transforms/Passes.h"
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#include "mlir/Dialect/Affine/IR/AffineOps.h"
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#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "llvm/Support/CommandLine.h"
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namespace fir {
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#define GEN_PASS_DEF_CFGCONVERSION
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#include "flang/Optimizer/Transforms/Passes.h.inc"
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} // namespace fir
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using namespace fir;
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using namespace mlir;
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namespace {
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// Conversion of fir control ops to more primitive control-flow.
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//
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// FIR loops that cannot be converted to the affine dialect will remain as
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// `fir.do_loop` operations. These can be converted to control-flow operations.
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/// Convert `fir.do_loop` to CFG
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class CfgLoopConv : public mlir::OpRewritePattern<fir::DoLoopOp> {
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public:
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using OpRewritePattern::OpRewritePattern;
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CfgLoopConv(mlir::MLIRContext *ctx, bool forceLoopToExecuteOnce)
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: mlir::OpRewritePattern<fir::DoLoopOp>(ctx),
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forceLoopToExecuteOnce(forceLoopToExecuteOnce) {}
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mlir::LogicalResult
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matchAndRewrite(DoLoopOp loop,
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mlir::PatternRewriter &rewriter) const override {
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auto loc = loop.getLoc();
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// Create the start and end blocks that will wrap the DoLoopOp with an
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// initalizer and an end point
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auto *initBlock = rewriter.getInsertionBlock();
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auto initPos = rewriter.getInsertionPoint();
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auto *endBlock = rewriter.splitBlock(initBlock, initPos);
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// Split the first DoLoopOp block in two parts. The part before will be the
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// conditional block since it already has the induction variable and
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// loop-carried values as arguments.
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auto *conditionalBlock = &loop.getRegion().front();
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conditionalBlock->addArgument(rewriter.getIndexType(), loc);
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auto *firstBlock =
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rewriter.splitBlock(conditionalBlock, conditionalBlock->begin());
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auto *lastBlock = &loop.getRegion().back();
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// Move the blocks from the DoLoopOp between initBlock and endBlock
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rewriter.inlineRegionBefore(loop.getRegion(), endBlock);
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// Get loop values from the DoLoopOp
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auto low = loop.getLowerBound();
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auto high = loop.getUpperBound();
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assert(low && high && "must be a Value");
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auto step = loop.getStep();
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// Initalization block
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rewriter.setInsertionPointToEnd(initBlock);
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auto diff = rewriter.create<mlir::arith::SubIOp>(loc, high, low);
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auto distance = rewriter.create<mlir::arith::AddIOp>(loc, diff, step);
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mlir::Value iters =
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rewriter.create<mlir::arith::DivSIOp>(loc, distance, step);
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if (forceLoopToExecuteOnce) {
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auto zero = rewriter.create<mlir::arith::ConstantIndexOp>(loc, 0);
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auto cond = rewriter.create<mlir::arith::CmpIOp>(
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loc, arith::CmpIPredicate::sle, iters, zero);
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auto one = rewriter.create<mlir::arith::ConstantIndexOp>(loc, 1);
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iters = rewriter.create<mlir::arith::SelectOp>(loc, cond, one, iters);
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}
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llvm::SmallVector<mlir::Value> loopOperands;
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loopOperands.push_back(low);
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auto operands = loop.getIterOperands();
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loopOperands.append(operands.begin(), operands.end());
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loopOperands.push_back(iters);
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rewriter.create<mlir::cf::BranchOp>(loc, conditionalBlock, loopOperands);
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// Last loop block
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auto *terminator = lastBlock->getTerminator();
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rewriter.setInsertionPointToEnd(lastBlock);
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auto iv = conditionalBlock->getArgument(0);
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mlir::Value steppedIndex =
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rewriter.create<mlir::arith::AddIOp>(loc, iv, step);
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assert(steppedIndex && "must be a Value");
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auto lastArg = conditionalBlock->getNumArguments() - 1;
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auto itersLeft = conditionalBlock->getArgument(lastArg);
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auto one = rewriter.create<mlir::arith::ConstantIndexOp>(loc, 1);
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mlir::Value itersMinusOne =
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rewriter.create<mlir::arith::SubIOp>(loc, itersLeft, one);
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llvm::SmallVector<mlir::Value> loopCarried;
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loopCarried.push_back(steppedIndex);
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auto begin = loop.getFinalValue() ? std::next(terminator->operand_begin())
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: terminator->operand_begin();
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loopCarried.append(begin, terminator->operand_end());
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loopCarried.push_back(itersMinusOne);
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rewriter.create<mlir::cf::BranchOp>(loc, conditionalBlock, loopCarried);
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rewriter.eraseOp(terminator);
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// Conditional block
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rewriter.setInsertionPointToEnd(conditionalBlock);
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auto zero = rewriter.create<mlir::arith::ConstantIndexOp>(loc, 0);
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auto comparison = rewriter.create<mlir::arith::CmpIOp>(
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loc, arith::CmpIPredicate::sgt, itersLeft, zero);
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rewriter.create<mlir::cf::CondBranchOp>(
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loc, comparison, firstBlock, llvm::ArrayRef<mlir::Value>(), endBlock,
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llvm::ArrayRef<mlir::Value>());
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// The result of the loop operation is the values of the condition block
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// arguments except the induction variable on the last iteration.
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auto args = loop.getFinalValue()
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? conditionalBlock->getArguments()
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: conditionalBlock->getArguments().drop_front();
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rewriter.replaceOp(loop, args.drop_back());
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return success();
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}
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private:
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bool forceLoopToExecuteOnce;
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};
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/// Convert `fir.if` to control-flow
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class CfgIfConv : public mlir::OpRewritePattern<fir::IfOp> {
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public:
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using OpRewritePattern::OpRewritePattern;
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CfgIfConv(mlir::MLIRContext *ctx, bool forceLoopToExecuteOnce)
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: mlir::OpRewritePattern<fir::IfOp>(ctx) {}
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mlir::LogicalResult
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matchAndRewrite(IfOp ifOp, mlir::PatternRewriter &rewriter) const override {
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auto loc = ifOp.getLoc();
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// Split the block containing the 'fir.if' into two parts. The part before
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// will contain the condition, the part after will be the continuation
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// point.
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auto *condBlock = rewriter.getInsertionBlock();
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auto opPosition = rewriter.getInsertionPoint();
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auto *remainingOpsBlock = rewriter.splitBlock(condBlock, opPosition);
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mlir::Block *continueBlock;
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if (ifOp.getNumResults() == 0) {
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continueBlock = remainingOpsBlock;
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} else {
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continueBlock = rewriter.createBlock(
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remainingOpsBlock, ifOp.getResultTypes(),
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llvm::SmallVector<mlir::Location>(ifOp.getNumResults(), loc));
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rewriter.create<mlir::cf::BranchOp>(loc, remainingOpsBlock);
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}
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// Move blocks from the "then" region to the region containing 'fir.if',
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// place it before the continuation block, and branch to it.
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auto &ifOpRegion = ifOp.getThenRegion();
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auto *ifOpBlock = &ifOpRegion.front();
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auto *ifOpTerminator = ifOpRegion.back().getTerminator();
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auto ifOpTerminatorOperands = ifOpTerminator->getOperands();
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rewriter.setInsertionPointToEnd(&ifOpRegion.back());
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rewriter.create<mlir::cf::BranchOp>(loc, continueBlock,
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ifOpTerminatorOperands);
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rewriter.eraseOp(ifOpTerminator);
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rewriter.inlineRegionBefore(ifOpRegion, continueBlock);
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// Move blocks from the "else" region (if present) to the region containing
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// 'fir.if', place it before the continuation block and branch to it. It
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// will be placed after the "then" regions.
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auto *otherwiseBlock = continueBlock;
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auto &otherwiseRegion = ifOp.getElseRegion();
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if (!otherwiseRegion.empty()) {
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otherwiseBlock = &otherwiseRegion.front();
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auto *otherwiseTerm = otherwiseRegion.back().getTerminator();
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auto otherwiseTermOperands = otherwiseTerm->getOperands();
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rewriter.setInsertionPointToEnd(&otherwiseRegion.back());
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rewriter.create<mlir::cf::BranchOp>(loc, continueBlock,
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otherwiseTermOperands);
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rewriter.eraseOp(otherwiseTerm);
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rewriter.inlineRegionBefore(otherwiseRegion, continueBlock);
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}
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rewriter.setInsertionPointToEnd(condBlock);
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rewriter.create<mlir::cf::CondBranchOp>(
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loc, ifOp.getCondition(), ifOpBlock, llvm::ArrayRef<mlir::Value>(),
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otherwiseBlock, llvm::ArrayRef<mlir::Value>());
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rewriter.replaceOp(ifOp, continueBlock->getArguments());
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return success();
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}
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};
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/// Convert `fir.iter_while` to control-flow.
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class CfgIterWhileConv : public mlir::OpRewritePattern<fir::IterWhileOp> {
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public:
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using OpRewritePattern::OpRewritePattern;
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CfgIterWhileConv(mlir::MLIRContext *ctx, bool forceLoopToExecuteOnce)
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: mlir::OpRewritePattern<fir::IterWhileOp>(ctx) {}
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mlir::LogicalResult
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matchAndRewrite(fir::IterWhileOp whileOp,
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mlir::PatternRewriter &rewriter) const override {
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auto loc = whileOp.getLoc();
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// Start by splitting the block containing the 'fir.do_loop' into two parts.
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// The part before will get the init code, the part after will be the end
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// point.
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auto *initBlock = rewriter.getInsertionBlock();
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auto initPosition = rewriter.getInsertionPoint();
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auto *endBlock = rewriter.splitBlock(initBlock, initPosition);
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// Use the first block of the loop body as the condition block since it is
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// the block that has the induction variable and loop-carried values as
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// arguments. Split out all operations from the first block into a new
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// block. Move all body blocks from the loop body region to the region
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// containing the loop.
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auto *conditionBlock = &whileOp.getRegion().front();
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auto *firstBodyBlock =
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rewriter.splitBlock(conditionBlock, conditionBlock->begin());
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auto *lastBodyBlock = &whileOp.getRegion().back();
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rewriter.inlineRegionBefore(whileOp.getRegion(), endBlock);
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auto iv = conditionBlock->getArgument(0);
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auto iterateVar = conditionBlock->getArgument(1);
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// Append the induction variable stepping logic to the last body block and
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// branch back to the condition block. Loop-carried values are taken from
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// operands of the loop terminator.
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auto *terminator = lastBodyBlock->getTerminator();
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rewriter.setInsertionPointToEnd(lastBodyBlock);
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auto step = whileOp.getStep();
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mlir::Value stepped = rewriter.create<mlir::arith::AddIOp>(loc, iv, step);
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assert(stepped && "must be a Value");
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llvm::SmallVector<mlir::Value> loopCarried;
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loopCarried.push_back(stepped);
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auto begin = whileOp.getFinalValue()
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? std::next(terminator->operand_begin())
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: terminator->operand_begin();
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loopCarried.append(begin, terminator->operand_end());
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rewriter.create<mlir::cf::BranchOp>(loc, conditionBlock, loopCarried);
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rewriter.eraseOp(terminator);
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// Compute loop bounds before branching to the condition.
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rewriter.setInsertionPointToEnd(initBlock);
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auto lowerBound = whileOp.getLowerBound();
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auto upperBound = whileOp.getUpperBound();
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assert(lowerBound && upperBound && "must be a Value");
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// The initial values of loop-carried values is obtained from the operands
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// of the loop operation.
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llvm::SmallVector<mlir::Value> destOperands;
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destOperands.push_back(lowerBound);
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auto iterOperands = whileOp.getIterOperands();
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destOperands.append(iterOperands.begin(), iterOperands.end());
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rewriter.create<mlir::cf::BranchOp>(loc, conditionBlock, destOperands);
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// With the body block done, we can fill in the condition block.
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rewriter.setInsertionPointToEnd(conditionBlock);
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// The comparison depends on the sign of the step value. We fully expect
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// this expression to be folded by the optimizer or LLVM. This expression
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// is written this way so that `step == 0` always returns `false`.
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auto zero = rewriter.create<mlir::arith::ConstantIndexOp>(loc, 0);
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auto compl0 = rewriter.create<mlir::arith::CmpIOp>(
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loc, arith::CmpIPredicate::slt, zero, step);
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auto compl1 = rewriter.create<mlir::arith::CmpIOp>(
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loc, arith::CmpIPredicate::sle, iv, upperBound);
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auto compl2 = rewriter.create<mlir::arith::CmpIOp>(
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loc, arith::CmpIPredicate::slt, step, zero);
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auto compl3 = rewriter.create<mlir::arith::CmpIOp>(
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loc, arith::CmpIPredicate::sle, upperBound, iv);
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auto cmp0 = rewriter.create<mlir::arith::AndIOp>(loc, compl0, compl1);
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auto cmp1 = rewriter.create<mlir::arith::AndIOp>(loc, compl2, compl3);
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auto cmp2 = rewriter.create<mlir::arith::OrIOp>(loc, cmp0, cmp1);
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// Remember to AND in the early-exit bool.
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auto comparison =
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rewriter.create<mlir::arith::AndIOp>(loc, iterateVar, cmp2);
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rewriter.create<mlir::cf::CondBranchOp>(
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loc, comparison, firstBodyBlock, llvm::ArrayRef<mlir::Value>(),
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endBlock, llvm::ArrayRef<mlir::Value>());
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// The result of the loop operation is the values of the condition block
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// arguments except the induction variable on the last iteration.
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auto args = whileOp.getFinalValue()
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? conditionBlock->getArguments()
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: conditionBlock->getArguments().drop_front();
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rewriter.replaceOp(whileOp, args);
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return success();
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}
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};
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/// Convert FIR structured control flow ops to CFG ops.
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class CfgConversion : public fir::impl::CFGConversionBase<CfgConversion> {
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public:
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void runOnOperation() override {
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auto *context = &getContext();
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mlir::RewritePatternSet patterns(context);
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patterns.insert<CfgLoopConv, CfgIfConv, CfgIterWhileConv>(
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context, forceLoopToExecuteOnce);
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mlir::ConversionTarget target(*context);
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target.addLegalDialect<mlir::AffineDialect, mlir::cf::ControlFlowDialect,
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FIROpsDialect, mlir::func::FuncDialect>();
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// apply the patterns
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target.addIllegalOp<ResultOp, DoLoopOp, IfOp, IterWhileOp>();
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target.markUnknownOpDynamicallyLegal([](Operation *) { return true; });
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if (mlir::failed(mlir::applyPartialConversion(getOperation(), target,
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std::move(patterns)))) {
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mlir::emitError(mlir::UnknownLoc::get(context),
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"error in converting to CFG\n");
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signalPassFailure();
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}
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}
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};
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} // namespace
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/// Convert FIR's structured control flow ops to CFG ops. This
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/// conversion enables the `createLowerToCFGPass` to transform these to CFG
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/// form.
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std::unique_ptr<mlir::Pass> fir::createFirToCfgPass() {
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return std::make_unique<CfgConversion>();
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}
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