mirror of
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ec44c74fe7
This PR adds support for the `FlattenCFG` transformation on `switch` statements. It also introduces the `SwitchFlatOp`, which is necessary for subsequent lowering to LLVM.
570 lines
22 KiB
C++
570 lines
22 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements pass that inlines CIR operations regions into the parent
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// function region.
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//
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//===----------------------------------------------------------------------===//
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#include "PassDetail.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/IR/Block.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Support/LogicalResult.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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#include "clang/CIR/Dialect/IR/CIRDialect.h"
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#include "clang/CIR/Dialect/Passes.h"
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#include "clang/CIR/MissingFeatures.h"
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using namespace mlir;
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using namespace cir;
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namespace {
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/// Lowers operations with the terminator trait that have a single successor.
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void lowerTerminator(mlir::Operation *op, mlir::Block *dest,
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mlir::PatternRewriter &rewriter) {
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assert(op->hasTrait<mlir::OpTrait::IsTerminator>() && "not a terminator");
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mlir::OpBuilder::InsertionGuard guard(rewriter);
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rewriter.setInsertionPoint(op);
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rewriter.replaceOpWithNewOp<cir::BrOp>(op, dest);
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}
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/// Walks a region while skipping operations of type `Ops`. This ensures the
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/// callback is not applied to said operations and its children.
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template <typename... Ops>
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void walkRegionSkipping(
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mlir::Region ®ion,
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mlir::function_ref<mlir::WalkResult(mlir::Operation *)> callback) {
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region.walk<mlir::WalkOrder::PreOrder>([&](mlir::Operation *op) {
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if (isa<Ops...>(op))
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return mlir::WalkResult::skip();
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return callback(op);
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});
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}
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struct CIRFlattenCFGPass : public CIRFlattenCFGBase<CIRFlattenCFGPass> {
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CIRFlattenCFGPass() = default;
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void runOnOperation() override;
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};
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struct CIRIfFlattening : public mlir::OpRewritePattern<cir::IfOp> {
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using OpRewritePattern<IfOp>::OpRewritePattern;
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mlir::LogicalResult
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matchAndRewrite(cir::IfOp ifOp,
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mlir::PatternRewriter &rewriter) const override {
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mlir::OpBuilder::InsertionGuard guard(rewriter);
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mlir::Location loc = ifOp.getLoc();
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bool emptyElse = ifOp.getElseRegion().empty();
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mlir::Block *currentBlock = rewriter.getInsertionBlock();
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mlir::Block *remainingOpsBlock =
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rewriter.splitBlock(currentBlock, rewriter.getInsertionPoint());
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mlir::Block *continueBlock;
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if (ifOp->getResults().empty())
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continueBlock = remainingOpsBlock;
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else
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llvm_unreachable("NYI");
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// Inline the region
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mlir::Block *thenBeforeBody = &ifOp.getThenRegion().front();
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mlir::Block *thenAfterBody = &ifOp.getThenRegion().back();
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rewriter.inlineRegionBefore(ifOp.getThenRegion(), continueBlock);
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rewriter.setInsertionPointToEnd(thenAfterBody);
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if (auto thenYieldOp =
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dyn_cast<cir::YieldOp>(thenAfterBody->getTerminator())) {
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rewriter.replaceOpWithNewOp<cir::BrOp>(thenYieldOp, thenYieldOp.getArgs(),
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continueBlock);
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}
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rewriter.setInsertionPointToEnd(continueBlock);
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// Has else region: inline it.
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mlir::Block *elseBeforeBody = nullptr;
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mlir::Block *elseAfterBody = nullptr;
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if (!emptyElse) {
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elseBeforeBody = &ifOp.getElseRegion().front();
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elseAfterBody = &ifOp.getElseRegion().back();
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rewriter.inlineRegionBefore(ifOp.getElseRegion(), continueBlock);
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} else {
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elseBeforeBody = elseAfterBody = continueBlock;
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}
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rewriter.setInsertionPointToEnd(currentBlock);
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rewriter.create<cir::BrCondOp>(loc, ifOp.getCondition(), thenBeforeBody,
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elseBeforeBody);
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if (!emptyElse) {
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rewriter.setInsertionPointToEnd(elseAfterBody);
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if (auto elseYieldOP =
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dyn_cast<cir::YieldOp>(elseAfterBody->getTerminator())) {
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rewriter.replaceOpWithNewOp<cir::BrOp>(
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elseYieldOP, elseYieldOP.getArgs(), continueBlock);
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}
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}
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rewriter.replaceOp(ifOp, continueBlock->getArguments());
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return mlir::success();
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}
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};
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class CIRScopeOpFlattening : public mlir::OpRewritePattern<cir::ScopeOp> {
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public:
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using OpRewritePattern<cir::ScopeOp>::OpRewritePattern;
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mlir::LogicalResult
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matchAndRewrite(cir::ScopeOp scopeOp,
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mlir::PatternRewriter &rewriter) const override {
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mlir::OpBuilder::InsertionGuard guard(rewriter);
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mlir::Location loc = scopeOp.getLoc();
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// Empty scope: just remove it.
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// TODO: Remove this logic once CIR uses MLIR infrastructure to remove
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// trivially dead operations. MLIR canonicalizer is too aggressive and we
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// need to either (a) make sure all our ops model all side-effects and/or
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// (b) have more options in the canonicalizer in MLIR to temper
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// aggressiveness level.
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if (scopeOp.isEmpty()) {
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rewriter.eraseOp(scopeOp);
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return mlir::success();
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}
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// Split the current block before the ScopeOp to create the inlining
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// point.
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mlir::Block *currentBlock = rewriter.getInsertionBlock();
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mlir::Block *continueBlock =
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rewriter.splitBlock(currentBlock, rewriter.getInsertionPoint());
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if (scopeOp.getNumResults() > 0)
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continueBlock->addArguments(scopeOp.getResultTypes(), loc);
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// Inline body region.
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mlir::Block *beforeBody = &scopeOp.getScopeRegion().front();
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mlir::Block *afterBody = &scopeOp.getScopeRegion().back();
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rewriter.inlineRegionBefore(scopeOp.getScopeRegion(), continueBlock);
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// Save stack and then branch into the body of the region.
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rewriter.setInsertionPointToEnd(currentBlock);
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assert(!cir::MissingFeatures::stackSaveOp());
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rewriter.create<cir::BrOp>(loc, mlir::ValueRange(), beforeBody);
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// Replace the scopeop return with a branch that jumps out of the body.
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// Stack restore before leaving the body region.
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rewriter.setInsertionPointToEnd(afterBody);
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if (auto yieldOp = dyn_cast<cir::YieldOp>(afterBody->getTerminator())) {
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rewriter.replaceOpWithNewOp<cir::BrOp>(yieldOp, yieldOp.getArgs(),
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continueBlock);
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}
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// Replace the op with values return from the body region.
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rewriter.replaceOp(scopeOp, continueBlock->getArguments());
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return mlir::success();
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}
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};
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class CIRSwitchOpFlattening : public mlir::OpRewritePattern<cir::SwitchOp> {
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public:
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using OpRewritePattern<cir::SwitchOp>::OpRewritePattern;
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inline void rewriteYieldOp(mlir::PatternRewriter &rewriter,
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cir::YieldOp yieldOp,
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mlir::Block *destination) const {
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rewriter.setInsertionPoint(yieldOp);
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rewriter.replaceOpWithNewOp<cir::BrOp>(yieldOp, yieldOp.getOperands(),
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destination);
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}
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// Return the new defaultDestination block.
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Block *condBrToRangeDestination(cir::SwitchOp op,
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mlir::PatternRewriter &rewriter,
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mlir::Block *rangeDestination,
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mlir::Block *defaultDestination,
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const APInt &lowerBound,
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const APInt &upperBound) const {
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assert(lowerBound.sle(upperBound) && "Invalid range");
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mlir::Block *resBlock = rewriter.createBlock(defaultDestination);
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cir::IntType sIntType = cir::IntType::get(op.getContext(), 32, true);
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cir::IntType uIntType = cir::IntType::get(op.getContext(), 32, false);
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cir::ConstantOp rangeLength = rewriter.create<cir::ConstantOp>(
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op.getLoc(), cir::IntAttr::get(sIntType, upperBound - lowerBound));
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cir::ConstantOp lowerBoundValue = rewriter.create<cir::ConstantOp>(
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op.getLoc(), cir::IntAttr::get(sIntType, lowerBound));
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cir::BinOp diffValue =
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rewriter.create<cir::BinOp>(op.getLoc(), sIntType, cir::BinOpKind::Sub,
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op.getCondition(), lowerBoundValue);
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// Use unsigned comparison to check if the condition is in the range.
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cir::CastOp uDiffValue = rewriter.create<cir::CastOp>(
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op.getLoc(), uIntType, CastKind::integral, diffValue);
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cir::CastOp uRangeLength = rewriter.create<cir::CastOp>(
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op.getLoc(), uIntType, CastKind::integral, rangeLength);
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cir::CmpOp cmpResult = rewriter.create<cir::CmpOp>(
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op.getLoc(), cir::BoolType::get(op.getContext()), cir::CmpOpKind::le,
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uDiffValue, uRangeLength);
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rewriter.create<cir::BrCondOp>(op.getLoc(), cmpResult, rangeDestination,
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defaultDestination);
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return resBlock;
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}
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mlir::LogicalResult
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matchAndRewrite(cir::SwitchOp op,
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mlir::PatternRewriter &rewriter) const override {
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llvm::SmallVector<CaseOp> cases;
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op.collectCases(cases);
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// Empty switch statement: just erase it.
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if (cases.empty()) {
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rewriter.eraseOp(op);
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return mlir::success();
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}
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// Create exit block from the next node of cir.switch op.
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mlir::Block *exitBlock = rewriter.splitBlock(
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rewriter.getBlock(), op->getNextNode()->getIterator());
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// We lower cir.switch op in the following process:
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// 1. Inline the region from the switch op after switch op.
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// 2. Traverse each cir.case op:
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// a. Record the entry block, block arguments and condition for every
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// case. b. Inline the case region after the case op.
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// 3. Replace the empty cir.switch.op with the new cir.switchflat op by the
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// recorded block and conditions.
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// inline everything from switch body between the switch op and the exit
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// block.
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{
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cir::YieldOp switchYield = nullptr;
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// Clear switch operation.
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for (mlir::Block &block :
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llvm::make_early_inc_range(op.getBody().getBlocks()))
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if (auto yieldOp = dyn_cast<cir::YieldOp>(block.getTerminator()))
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switchYield = yieldOp;
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assert(!op.getBody().empty());
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mlir::Block *originalBlock = op->getBlock();
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mlir::Block *swopBlock =
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rewriter.splitBlock(originalBlock, op->getIterator());
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rewriter.inlineRegionBefore(op.getBody(), exitBlock);
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if (switchYield)
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rewriteYieldOp(rewriter, switchYield, exitBlock);
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rewriter.setInsertionPointToEnd(originalBlock);
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rewriter.create<cir::BrOp>(op.getLoc(), swopBlock);
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}
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// Allocate required data structures (disconsider default case in
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// vectors).
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llvm::SmallVector<mlir::APInt, 8> caseValues;
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llvm::SmallVector<mlir::Block *, 8> caseDestinations;
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llvm::SmallVector<mlir::ValueRange, 8> caseOperands;
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llvm::SmallVector<std::pair<APInt, APInt>> rangeValues;
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llvm::SmallVector<mlir::Block *> rangeDestinations;
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llvm::SmallVector<mlir::ValueRange> rangeOperands;
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// Initialize default case as optional.
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mlir::Block *defaultDestination = exitBlock;
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mlir::ValueRange defaultOperands = exitBlock->getArguments();
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// Digest the case statements values and bodies.
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for (cir::CaseOp caseOp : cases) {
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mlir::Region ®ion = caseOp.getCaseRegion();
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// Found default case: save destination and operands.
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switch (caseOp.getKind()) {
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case cir::CaseOpKind::Default:
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defaultDestination = ®ion.front();
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defaultOperands = defaultDestination->getArguments();
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break;
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case cir::CaseOpKind::Range:
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assert(caseOp.getValue().size() == 2 &&
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"Case range should have 2 case value");
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rangeValues.push_back(
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{cast<cir::IntAttr>(caseOp.getValue()[0]).getValue(),
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cast<cir::IntAttr>(caseOp.getValue()[1]).getValue()});
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rangeDestinations.push_back(®ion.front());
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rangeOperands.push_back(rangeDestinations.back()->getArguments());
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break;
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case cir::CaseOpKind::Anyof:
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case cir::CaseOpKind::Equal:
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// AnyOf cases kind can have multiple values, hence the loop below.
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for (const mlir::Attribute &value : caseOp.getValue()) {
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caseValues.push_back(cast<cir::IntAttr>(value).getValue());
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caseDestinations.push_back(®ion.front());
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caseOperands.push_back(caseDestinations.back()->getArguments());
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}
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break;
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}
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// Handle break statements.
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walkRegionSkipping<cir::LoopOpInterface, cir::SwitchOp>(
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region, [&](mlir::Operation *op) {
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if (!isa<cir::BreakOp>(op))
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return mlir::WalkResult::advance();
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lowerTerminator(op, exitBlock, rewriter);
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return mlir::WalkResult::skip();
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});
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// Track fallthrough in cases.
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for (mlir::Block &blk : region.getBlocks()) {
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if (blk.getNumSuccessors())
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continue;
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if (auto yieldOp = dyn_cast<cir::YieldOp>(blk.getTerminator())) {
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mlir::Operation *nextOp = caseOp->getNextNode();
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assert(nextOp && "caseOp is not expected to be the last op");
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mlir::Block *oldBlock = nextOp->getBlock();
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mlir::Block *newBlock =
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rewriter.splitBlock(oldBlock, nextOp->getIterator());
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rewriter.setInsertionPointToEnd(oldBlock);
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rewriter.create<cir::BrOp>(nextOp->getLoc(), mlir::ValueRange(),
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newBlock);
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rewriteYieldOp(rewriter, yieldOp, newBlock);
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}
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}
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mlir::Block *oldBlock = caseOp->getBlock();
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mlir::Block *newBlock =
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rewriter.splitBlock(oldBlock, caseOp->getIterator());
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mlir::Block &entryBlock = caseOp.getCaseRegion().front();
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rewriter.inlineRegionBefore(caseOp.getCaseRegion(), newBlock);
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// Create a branch to the entry of the inlined region.
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rewriter.setInsertionPointToEnd(oldBlock);
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rewriter.create<cir::BrOp>(caseOp.getLoc(), &entryBlock);
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}
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// Remove all cases since we've inlined the regions.
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for (cir::CaseOp caseOp : cases) {
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mlir::Block *caseBlock = caseOp->getBlock();
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// Erase the block with no predecessors here to make the generated code
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// simpler a little bit.
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if (caseBlock->hasNoPredecessors())
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rewriter.eraseBlock(caseBlock);
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else
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rewriter.eraseOp(caseOp);
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}
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for (auto [rangeVal, operand, destination] :
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llvm::zip(rangeValues, rangeOperands, rangeDestinations)) {
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APInt lowerBound = rangeVal.first;
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APInt upperBound = rangeVal.second;
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// The case range is unreachable, skip it.
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if (lowerBound.sgt(upperBound))
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continue;
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// If range is small, add multiple switch instruction cases.
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// This magical number is from the original CGStmt code.
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constexpr int kSmallRangeThreshold = 64;
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if ((upperBound - lowerBound)
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.ult(llvm::APInt(32, kSmallRangeThreshold))) {
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for (APInt iValue = lowerBound; iValue.sle(upperBound); ++iValue) {
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caseValues.push_back(iValue);
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caseOperands.push_back(operand);
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caseDestinations.push_back(destination);
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}
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continue;
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}
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defaultDestination =
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condBrToRangeDestination(op, rewriter, destination,
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defaultDestination, lowerBound, upperBound);
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defaultOperands = operand;
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}
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// Set switch op to branch to the newly created blocks.
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rewriter.setInsertionPoint(op);
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rewriter.replaceOpWithNewOp<cir::SwitchFlatOp>(
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op, op.getCondition(), defaultDestination, defaultOperands, caseValues,
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caseDestinations, caseOperands);
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return mlir::success();
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}
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};
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class CIRLoopOpInterfaceFlattening
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: public mlir::OpInterfaceRewritePattern<cir::LoopOpInterface> {
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public:
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using mlir::OpInterfaceRewritePattern<
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cir::LoopOpInterface>::OpInterfaceRewritePattern;
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inline void lowerConditionOp(cir::ConditionOp op, mlir::Block *body,
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mlir::Block *exit,
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mlir::PatternRewriter &rewriter) const {
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mlir::OpBuilder::InsertionGuard guard(rewriter);
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rewriter.setInsertionPoint(op);
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rewriter.replaceOpWithNewOp<cir::BrCondOp>(op, op.getCondition(), body,
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exit);
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}
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mlir::LogicalResult
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matchAndRewrite(cir::LoopOpInterface op,
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mlir::PatternRewriter &rewriter) const final {
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// Setup CFG blocks.
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mlir::Block *entry = rewriter.getInsertionBlock();
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mlir::Block *exit =
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rewriter.splitBlock(entry, rewriter.getInsertionPoint());
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mlir::Block *cond = &op.getCond().front();
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mlir::Block *body = &op.getBody().front();
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mlir::Block *step =
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(op.maybeGetStep() ? &op.maybeGetStep()->front() : nullptr);
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// Setup loop entry branch.
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rewriter.setInsertionPointToEnd(entry);
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rewriter.create<cir::BrOp>(op.getLoc(), &op.getEntry().front());
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// Branch from condition region to body or exit.
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auto conditionOp = cast<cir::ConditionOp>(cond->getTerminator());
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lowerConditionOp(conditionOp, body, exit, rewriter);
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// TODO(cir): Remove the walks below. It visits operations unnecessarily.
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// However, to solve this we would likely need a custom DialectConversion
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// driver to customize the order that operations are visited.
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// Lower continue statements.
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mlir::Block *dest = (step ? step : cond);
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op.walkBodySkippingNestedLoops([&](mlir::Operation *op) {
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if (!isa<cir::ContinueOp>(op))
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return mlir::WalkResult::advance();
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lowerTerminator(op, dest, rewriter);
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return mlir::WalkResult::skip();
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});
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// Lower break statements.
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assert(!cir::MissingFeatures::switchOp());
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walkRegionSkipping<cir::LoopOpInterface>(
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op.getBody(), [&](mlir::Operation *op) {
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if (!isa<cir::BreakOp>(op))
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return mlir::WalkResult::advance();
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lowerTerminator(op, exit, rewriter);
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return mlir::WalkResult::skip();
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});
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// Lower optional body region yield.
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for (mlir::Block &blk : op.getBody().getBlocks()) {
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auto bodyYield = dyn_cast<cir::YieldOp>(blk.getTerminator());
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if (bodyYield)
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lowerTerminator(bodyYield, (step ? step : cond), rewriter);
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}
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// Lower mandatory step region yield.
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if (step)
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lowerTerminator(cast<cir::YieldOp>(step->getTerminator()), cond,
|
|
rewriter);
|
|
|
|
// Move region contents out of the loop op.
|
|
rewriter.inlineRegionBefore(op.getCond(), exit);
|
|
rewriter.inlineRegionBefore(op.getBody(), exit);
|
|
if (step)
|
|
rewriter.inlineRegionBefore(*op.maybeGetStep(), exit);
|
|
|
|
rewriter.eraseOp(op);
|
|
return mlir::success();
|
|
}
|
|
};
|
|
|
|
class CIRTernaryOpFlattening : public mlir::OpRewritePattern<cir::TernaryOp> {
|
|
public:
|
|
using OpRewritePattern<cir::TernaryOp>::OpRewritePattern;
|
|
|
|
mlir::LogicalResult
|
|
matchAndRewrite(cir::TernaryOp op,
|
|
mlir::PatternRewriter &rewriter) const override {
|
|
Location loc = op->getLoc();
|
|
Block *condBlock = rewriter.getInsertionBlock();
|
|
Block::iterator opPosition = rewriter.getInsertionPoint();
|
|
Block *remainingOpsBlock = rewriter.splitBlock(condBlock, opPosition);
|
|
llvm::SmallVector<mlir::Location, 2> locs;
|
|
// Ternary result is optional, make sure to populate the location only
|
|
// when relevant.
|
|
if (op->getResultTypes().size())
|
|
locs.push_back(loc);
|
|
Block *continueBlock =
|
|
rewriter.createBlock(remainingOpsBlock, op->getResultTypes(), locs);
|
|
rewriter.create<cir::BrOp>(loc, remainingOpsBlock);
|
|
|
|
Region &trueRegion = op.getTrueRegion();
|
|
Block *trueBlock = &trueRegion.front();
|
|
mlir::Operation *trueTerminator = trueRegion.back().getTerminator();
|
|
rewriter.setInsertionPointToEnd(&trueRegion.back());
|
|
auto trueYieldOp = dyn_cast<cir::YieldOp>(trueTerminator);
|
|
|
|
rewriter.replaceOpWithNewOp<cir::BrOp>(trueYieldOp, trueYieldOp.getArgs(),
|
|
continueBlock);
|
|
rewriter.inlineRegionBefore(trueRegion, continueBlock);
|
|
|
|
Block *falseBlock = continueBlock;
|
|
Region &falseRegion = op.getFalseRegion();
|
|
|
|
falseBlock = &falseRegion.front();
|
|
mlir::Operation *falseTerminator = falseRegion.back().getTerminator();
|
|
rewriter.setInsertionPointToEnd(&falseRegion.back());
|
|
auto falseYieldOp = dyn_cast<cir::YieldOp>(falseTerminator);
|
|
rewriter.replaceOpWithNewOp<cir::BrOp>(falseYieldOp, falseYieldOp.getArgs(),
|
|
continueBlock);
|
|
rewriter.inlineRegionBefore(falseRegion, continueBlock);
|
|
|
|
rewriter.setInsertionPointToEnd(condBlock);
|
|
rewriter.create<cir::BrCondOp>(loc, op.getCond(), trueBlock, falseBlock);
|
|
|
|
rewriter.replaceOp(op, continueBlock->getArguments());
|
|
|
|
// Ok, we're done!
|
|
return mlir::success();
|
|
}
|
|
};
|
|
|
|
void populateFlattenCFGPatterns(RewritePatternSet &patterns) {
|
|
patterns
|
|
.add<CIRIfFlattening, CIRLoopOpInterfaceFlattening, CIRScopeOpFlattening,
|
|
CIRSwitchOpFlattening, CIRTernaryOpFlattening>(
|
|
patterns.getContext());
|
|
}
|
|
|
|
void CIRFlattenCFGPass::runOnOperation() {
|
|
RewritePatternSet patterns(&getContext());
|
|
populateFlattenCFGPatterns(patterns);
|
|
|
|
// Collect operations to apply patterns.
|
|
llvm::SmallVector<Operation *, 16> ops;
|
|
getOperation()->walk<mlir::WalkOrder::PostOrder>([&](Operation *op) {
|
|
assert(!cir::MissingFeatures::ifOp());
|
|
assert(!cir::MissingFeatures::switchOp());
|
|
assert(!cir::MissingFeatures::tryOp());
|
|
if (isa<IfOp, ScopeOp, SwitchOp, LoopOpInterface, TernaryOp>(op))
|
|
ops.push_back(op);
|
|
});
|
|
|
|
// Apply patterns.
|
|
if (applyOpPatternsGreedily(ops, std::move(patterns)).failed())
|
|
signalPassFailure();
|
|
}
|
|
|
|
} // namespace
|
|
|
|
namespace mlir {
|
|
|
|
std::unique_ptr<Pass> createCIRFlattenCFGPass() {
|
|
return std::make_unique<CIRFlattenCFGPass>();
|
|
}
|
|
|
|
} // namespace mlir
|