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powerpc/mpc85xx: Add workaround for erratum A006379

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Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
	T4240 rev 1.0
	B4860 rev 1.0, 2.0

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2013-09-16 12:49:31 -07:00
parent e512c50bc9
commit 133fbfa9e6
5 changed files with 40 additions and 0 deletions
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25
arch/powerpc/include/asm/fsl_errata.h Normal file
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@ -0,0 +1,25 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_FSL_ERRATA_H
#define _ASM_FSL_ERRATA_H
#include <common.h>
#include <asm/processor.h>
#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
static inline bool has_erratum_a006379(void)
{
u32 svr = get_svr();
if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2))
return true;
return false;
}
#endif
#endif