powerpc/85xx: Add P2041 processor support

The P2041 is similar to P2040, however has a 10G port and backside L2

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

arch/powerpc/cpu/mpc85xx/Makefile

@@ -65,6 +65,7 @@ COBJS-$(CONFIG_P1025)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P2040)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
@@ -78,6 +79,7 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
 COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o
+COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
@@ -110,6 +112,7 @@ COBJS-$(CONFIG_P1025)	+= p1021_serdes.o
 COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
 COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
 COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o
+COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o

arch/powerpc/cpu/mpc85xx/p2040_ids.c

@@ -77,6 +77,9 @@ struct liodn_id_table fman1_liodn_tbl[] = {
 	SET_FMAN_RX_1G_LIODN(1, 2, 12),
 	SET_FMAN_RX_1G_LIODN(1, 3, 13),
 	SET_FMAN_RX_1G_LIODN(1, 4, 14),
+#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
+	SET_FMAN_RX_10G_LIODN(1, 0, 15),
+#endif
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 #endif

arch/powerpc/cpu/mpc8xxx/cpu.c

@@ -98,6 +98,8 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P2020, P2020_E, 2),
 	CPU_TYPE_ENTRY(P2040, P2040, 4),
 	CPU_TYPE_ENTRY(P2040, P2040_E, 4),
+	CPU_TYPE_ENTRY(P2041, P2041, 4),
+	CPU_TYPE_ENTRY(P2041, P2041_E, 4),
 	CPU_TYPE_ENTRY(P3041, P3041, 4),
 	CPU_TYPE_ENTRY(P3041, P3041_E, 4),
 	CPU_TYPE_ENTRY(P4040, P4040, 4),

arch/powerpc/include/asm/config_mpc85xx.h

@@ -273,6 +273,22 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_PPC_P2041)
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2

arch/powerpc/include/asm/processor.h

@@ -1103,6 +1103,8 @@
 #define SVR_P2020_E	0x80EA00
 #define SVR_P2040	0x821000
 #define SVR_P2040_E	0x821800
+#define SVR_P2041	0x821001
+#define SVR_P2041_E	0x821801
 #define SVR_P3041	0x821103
 #define SVR_P3041_E	0x821903
 #define SVR_P4040	0x820100