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NET: Cosmetic changes
Signed-off-by: Larry Johnson <lrj@acm.org> Signed-off-by: Ben Warren <bwarren@qstreams.com>
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Larry Johnson
committed by
Ben Warren
Ben Warren
parent
881cf02f47
commit
298035df49
@ -26,56 +26,48 @@
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 04-May-99 Created MKW
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| 07-Jul-99 Added full duplex support MKW
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| 08-Sep-01 Tweaks gvb
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+----------------------------------------------------------------------------*/
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#ifndef _miiphy_h_
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#define _miiphy_h_
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#include <net.h>
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int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
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unsigned short *value);
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int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
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unsigned short value);
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int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
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unsigned char *model, unsigned char *rev);
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int miiphy_reset(char *devname, unsigned char addr);
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int miiphy_speed(char *devname, unsigned char addr);
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int miiphy_duplex(char *devname, unsigned char addr);
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int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
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unsigned short *value);
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int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
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unsigned short value);
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int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
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unsigned char *model, unsigned char *rev);
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int miiphy_reset (char *devname, unsigned char addr);
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int miiphy_speed (char *devname, unsigned char addr);
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int miiphy_duplex (char *devname, unsigned char addr);
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#ifdef CFG_FAULT_ECHO_LINK_DOWN
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int miiphy_link(char *devname, unsigned char addr);
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int miiphy_link (char *devname, unsigned char addr);
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#endif
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void miiphy_init(void);
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void miiphy_init (void);
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void miiphy_register(char *devname,
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int (* read)(char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value),
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int (* write)(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value));
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void miiphy_register (char *devname,
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int (*read) (char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value),
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int (*write) (char *devname, unsigned char addr,
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unsigned char reg, unsigned short value));
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int miiphy_set_current_dev(char *devname);
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char *miiphy_get_current_dev(void);
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int miiphy_set_current_dev (char *devname);
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char *miiphy_get_current_dev (void);
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void miiphy_listdev(void);
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void miiphy_listdev (void);
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#define BB_MII_DEVNAME "bbmii"
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int bb_miiphy_read (char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value);
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unsigned char reg, unsigned short *value);
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int bb_miiphy_write (char *devname, unsigned char addr,
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unsigned char reg, unsigned short value);
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unsigned char reg, unsigned short value);
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/* phy seed setup */
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#define AUTO 99
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#define _1000BASET 1000
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#define _1000BASET 1000
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#define _100BASET 100
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#define _10BASET 10
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#define HALF 22
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@ -90,9 +82,9 @@ int bb_miiphy_write (char *devname, unsigned char addr,
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#define PHY_ANLPAR 0x05
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#define PHY_ANER 0x06
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#define PHY_ANNPTR 0x07
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#define PHY_ANLPNP 0x08
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#define PHY_1000BTCR 0x09
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#define PHY_1000BTSR 0x0A
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#define PHY_ANLPNP 0x08
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#define PHY_1000BTCR 0x09
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#define PHY_1000BTSR 0x0A
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#define PHY_PHYSTS 0x10
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#define PHY_MIPSCR 0x11
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#define PHY_MIPGSR 0x12
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@ -115,10 +107,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
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#define PHY_BMCR_DPLX 0x0100
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#define PHY_BMCR_COL_TST 0x0080
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#define PHY_BMCR_SPEED_MASK 0x2040
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#define PHY_BMCR_1000_MBPS 0x0040
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#define PHY_BMCR_100_MBPS 0x2000
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#define PHY_BMCR_10_MBPS 0x0000
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#define PHY_BMCR_SPEED_MASK 0x2040
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#define PHY_BMCR_1000_MBPS 0x0040
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#define PHY_BMCR_100_MBPS 0x2000
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#define PHY_BMCR_10_MBPS 0x0000
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/* phy BMSR */
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#define PHY_BMSR_100T4 0x8000
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@ -143,18 +135,18 @@ int bb_miiphy_write (char *devname, unsigned char addr,
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#define PHY_ANLPAR_TX 0x0080
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#define PHY_ANLPAR_10FD 0x0040
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#define PHY_ANLPAR_10 0x0020
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
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#define PHY_ANLPAR_PSB_MASK 0x001f
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#define PHY_ANLPAR_PSB_802_3 0x0001
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#define PHY_ANLPAR_PSB_802_9 0x0002
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#define PHY_ANLPAR_PSB_MASK 0x001f
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#define PHY_ANLPAR_PSB_802_3 0x0001
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#define PHY_ANLPAR_PSB_802_9 0x0002
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/* PHY_1000BTSR */
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#define PHY_1000BTSR_MSCF 0x8000
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#define PHY_1000BTSR_MSCR 0x4000
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#define PHY_1000BTSR_LRS 0x2000
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#define PHY_1000BTSR_RRS 0x1000
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#define PHY_1000BTSR_1000FD 0x0800
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#define PHY_1000BTSR_1000HD 0x0400
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/* phy 1000BTSR */
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#define PHY_1000BTSR_MSCF 0x8000
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#define PHY_1000BTSR_MSCR 0x4000
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#define PHY_1000BTSR_LRS 0x2000
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#define PHY_1000BTSR_RRS 0x1000
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#define PHY_1000BTSR_1000FD 0x0800
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#define PHY_1000BTSR_1000HD 0x0400
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#endif
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