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serial: sh: fix internal clock source on SCIF

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The formula to calculate SCIF BRR for R-Car H2/M2/E2 SoCs is as follows:

BRR = pclk / (64 * 2^(2n-1) * baudrate) - 1,
the prescaler is 0 due to SCSMR settings, hence n=0

Also SCSCR must be set to use internal or external clock source.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Vladimir Barinov
2015-02-14 01:05:18 +03:00
committed by Nobuhiro Iwamatsu
parent 89f99a62c1
commit 2cbb17c0e9
1 changed files with 3 additions and 2 deletions
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5
drivers/serial/serial_sh.h
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@ -227,7 +227,8 @@ struct uart_port {
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001 # define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else #else
# error CPU subtype not defined # error CPU subtype not defined
#endif #endif
@ -742,7 +743,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */ #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
#else /* Generic SH */ #else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif #endif