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mmc: omap_hsmmc: Workaround for errata id i802

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According to errata i802, DCRC error interrupts
(MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure.

The DCRC interrupt, occurs when the last tuning block fails
(the last ratio tested). The delay from CRC check until the
interrupt is asserted is bigger than the delay until assertion
of the tuning end flag. Assertion of tuning end flag is what
masks the interrupts. Because of this race, an erroneous DCRC
interrupt occurs.

The suggested  workaround is to disable DCRC interrupts during
the tuning procedure which is implemented here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This commit is contained in:
Jean-Jacques Hiblot
2018-01-30 16:01:36 +01:00
committed by Jaehoon Chung
parent 14761caeee
commit 2faa1a302b
2 changed files with 26 additions and 6 deletions
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4
arch/arm/include/asm/omap_mmc.h
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@ -219,6 +219,10 @@ struct omap_hsmmc_plat {
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
IE_BRR | IE_BWR | IE_TC | IE_CC)
int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
int wp_gpio);