@ -1,437 +0,0 @@
/ *
* Most o f t h i s t a k e n f r o m R e d b o o t h a l _ p l a t f o r m _ s e t u p . h w i t h c l e a n u p
*
* NOTE : I h a v e n ' t c l e a n t h i s u p c o n s i d e r a b l y , j u s t e n o u g h t o g e t i t
* running. S e e h a l _ p l a t f o r m _ s e t u p . h f o r t h e s o u r c e . S e e
* board/ c r a d l e / l o w l e v e l _ i n i t . S f o r a n o t h e r P X A 2 5 0 s e t u p t h a t i s
* much c l e a n e r .
*
* See f i l e C R E D I T S f o r l i s t o f p e o p l e w h o c o n t r i b u t e d t o t h i s
* project.
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or
* modify i t u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n ; either version 2 of
* the L i c e n s e , o r ( a t y o u r o p t i o n ) a n y l a t e r v e r s i o n .
*
* This p r o g r a m i s d i s t r i b u t e d i n t h e h o p e t h a t i t w i l l b e u s e f u l ,
* but W I T H O U T A N Y W A R R A N T Y ; without even the implied warranty of
* MERCHANTABILITY o r F I T N E S S F O R A P A R T I C U L A R P U R P O S E . S e e t h e
* GNU G e n e r a l P u b l i c L i c e n s e f o r m o r e d e t a i l s .
*
* You s h o u l d h a v e r e c e i v e d a c o p y o f t h e G N U G e n e r a l P u b l i c L i c e n s e
* along w i t h t h i s p r o g r a m ; if not, write to the Free Software
* Foundation, I n c . , 5 9 T e m p l e P l a c e , S u i t e 3 3 0 , B o s t o n ,
* MA 0 2 1 1 1 - 1 3 0 7 U S A
* /
# include < c o n f i g . h >
# include < v e r s i o n . h >
# include < a s m / a r c h / p x a - r e g s . h >
DRAM_SIZE : .long C O N F I G _ S Y S _ D R A M _ S I Z E
/* wait for coprocessor write complete */
.macro CPWAIT reg
mrc p15 ,0 ,\ r e g ,c2 ,c0 ,0
mov \ r e g ,\ r e g
sub p c ,p c ,#4
.endm
_TEXT_BASE :
.word C O N F I G _ S Y S _ T E X T _ B A S E
/ *
* Memory s e t u p
* /
.globl lowlevel_init
lowlevel_init :
mov r10 , l r
/* Set up GPIO pins first ----------------------------------------- */
ldr r0 , =GPSR0
ldr r1 , =CONFIG_SYS_GPSR0_VAL
str r1 , [ r0 ]
ldr r0 , =GPSR1
ldr r1 , =CONFIG_SYS_GPSR1_VAL
str r1 , [ r0 ]
ldr r0 , =GPSR2
ldr r1 , =CONFIG_SYS_GPSR2_VAL
str r1 , [ r0 ]
ldr r0 , =GPCR0
ldr r1 , =CONFIG_SYS_GPCR0_VAL
str r1 , [ r0 ]
ldr r0 , =GPCR1
ldr r1 , =CONFIG_SYS_GPCR1_VAL
str r1 , [ r0 ]
ldr r0 , =GPCR2
ldr r1 , =CONFIG_SYS_GPCR2_VAL
str r1 , [ r0 ]
ldr r0 , =GPDR0
ldr r1 , =CONFIG_SYS_GPDR0_VAL
str r1 , [ r0 ]
ldr r0 , =GPDR1
ldr r1 , =CONFIG_SYS_GPDR1_VAL
str r1 , [ r0 ]
ldr r0 , =GPDR2
ldr r1 , =CONFIG_SYS_GPDR2_VAL
str r1 , [ r0 ]
ldr r0 , =GAFR0_L
ldr r1 , =CONFIG_SYS_GAFR0_L_VAL
str r1 , [ r0 ]
ldr r0 , =GAFR0_U
ldr r1 , =CONFIG_SYS_GAFR0_U_VAL
str r1 , [ r0 ]
ldr r0 , =GAFR1_L
ldr r1 , =CONFIG_SYS_GAFR1_L_VAL
str r1 , [ r0 ]
ldr r0 , =GAFR1_U
ldr r1 , =CONFIG_SYS_GAFR1_U_VAL
str r1 , [ r0 ]
ldr r0 , =GAFR2_L
ldr r1 , =CONFIG_SYS_GAFR2_L_VAL
str r1 , [ r0 ]
ldr r0 , =GAFR2_U
ldr r1 , =CONFIG_SYS_GAFR2_U_VAL
str r1 , [ r0 ]
ldr r0 , =PSSR / * e n a b l e G P I O p i n s * /
ldr r1 , =CONFIG_SYS_PSSR_VAL
str r1 , [ r0 ]
/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */
/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
/* */
/* ldr r1, =LED_BLANK */
/* mov r0, #0xFF */
/* str r0, [r1] / turn on hex leds */
/* */
/*loop: */
/* */
/* ldr r0, =0xB0070001 */
/* ldr r1, =_LED */
/* str r0, [r1] / hex display */
/* ---------------------------------------------------------------- */
/* Enable memory interface */
/* */
/* The sequence below is based on the recommended init steps */
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
/* Chapter 10. */
/* ---------------------------------------------------------------- */
/* ---------------------------------------------------------------- */
/* Step 1: Wait for at least 200 microsedonds to allow internal */
/* clocks to settle. Only necessary after hard reset... */
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
ldr r3 , =OSCR / * r e s e t t h e O S T i m e r C o u n t t o z e r o * /
mov r2 , #0
str r2 , [ r3 ]
ldr r4 , =0x300 / * r e a l l y 0 x2 E 1 i s a b o u t 2 0 0 u s e c , * /
/* so 0x300 should be plenty */
1 :
ldr r2 , [ r3 ]
cmp r4 , r2
bgt 1 b
mem_init :
ldr r1 , =MEMC_BASE / * g e t m e m o r y c o n t r o l l e r b a s e a d d r . * /
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
/* ---------------------------------------------------------------- */
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
ldr r2 , =CONFIG_SYS_MSC0_VAL
str r2 , [ r1 , #M S C 0 _ O F F S E T ]
ldr r2 , [ r1 , #M S C 0 _ O F F S E T ] / * r e a d b a c k t o e n s u r e * /
/* that data latches */
/* MSC1: nCS(2,3) */
ldr r2 , =CONFIG_SYS_MSC1_VAL
str r2 , [ r1 , #M S C 1 _ O F F S E T ]
ldr r2 , [ r1 , #M S C 1 _ O F F S E T ]
/* MSC2: nCS(4,5) */
ldr r2 , =CONFIG_SYS_MSC2_VAL
str r2 , [ r1 , #M S C 2 _ O F F S E T ]
ldr r2 , [ r1 , #M S C 2 _ O F F S E T ]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
ldr r2 , =CONFIG_SYS_MECR_VAL
str r2 , [ r1 , #M E C R _ O F F S E T ]
ldr r2 , [ r1 , #M E C R _ O F F S E T ]
/* MCMEM0: Card Interface slot 0 timing */
ldr r2 , =CONFIG_SYS_MCMEM0_VAL
str r2 , [ r1 , #M C M E M 0 _ O F F S E T ]
ldr r2 , [ r1 , #M C M E M 0 _ O F F S E T ]
/* MCMEM1: Card Interface slot 1 timing */
ldr r2 , =CONFIG_SYS_MCMEM1_VAL
str r2 , [ r1 , #M C M E M 1 _ O F F S E T ]
ldr r2 , [ r1 , #M C M E M 1 _ O F F S E T ]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
ldr r2 , =CONFIG_SYS_MCATT0_VAL
str r2 , [ r1 , #M C A T T 0 _ O F F S E T ]
ldr r2 , [ r1 , #M C A T T 0 _ O F F S E T ]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
ldr r2 , =CONFIG_SYS_MCATT1_VAL
str r2 , [ r1 , #M C A T T 1 _ O F F S E T ]
ldr r2 , [ r1 , #M C A T T 1 _ O F F S E T ]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
ldr r2 , =CONFIG_SYS_MCIO0_VAL
str r2 , [ r1 , #M C I O 0 _ O F F S E T ]
ldr r2 , [ r1 , #M C I O 0 _ O F F S E T ]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
ldr r2 , =CONFIG_SYS_MCIO1_VAL
str r2 , [ r1 , #M C I O 1 _ O F F S E T ]
ldr r2 , [ r1 , #M C I O 1 _ O F F S E T ]
/* ---------------------------------------------------------------- */
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
/* ---------------------------------------------------------------- */
/* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
adr r3 , m e m _ i n i t / * r0 < - c u r r e n t p o s i t i o n o f c o d e * /
ldr r2 , =mem_init
cmp r3 , r2 / * s k i p i n i t i f i n p l a c e * /
beq i n i t i r q s
/* ---------------------------------------------------------------- */
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
/* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
ldr r3 , =CONFIG_SYS_MDREFR_VAL
ldr r2 , =0xFFF
and r3 , r3 , r2
ldr r4 , =0x03ca4000
orr r4 , r4 , r3
str r4 , [ r1 , #M D R E F R _ O F F S E T ] / * w r i t e b a c k M D R E F R * /
ldr r4 , [ r1 , #M D R E F R _ O F F S E T ]
/* ---------------------------------------------------------------- */
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
/* ---------------------------------------------------------------- */
/* Initialize SXCNFG register. Assert the enable bits */
/* Write SXMRS to cause an MRS command to all enabled banks of */
/* synchronous static memory. Note that SXLCR need not be written */
/* at this time. */
/* FIXME: we use async mode for now */
/* ---------------------------------------------------------------- */
/* Step 4: Initialize SDRAM */
/* ---------------------------------------------------------------- */
/* Step 4a: assert MDREFR:K?RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
ldr r4 , =CONFIG_SYS_MDREFR_VAL
str r4 , [ r1 , #M D R E F R _ O F F S E T ] / * w r i t e b a c k M D R E F R * /
ldr r4 , [ r1 , #M D R E F R _ O F F S E T ]
/* Step 4b: de-assert MDREFR:SLFRSH. */
bic r4 , r4 , #( M D R E F R _ S L F R S H )
str r4 , [ r1 , #M D R E F R _ O F F S E T ] / * w r i t e b a c k M D R E F R * /
ldr r4 , [ r1 , #M D R E F R _ O F F S E T ]
/* Step 4c: assert MDREFR:E1PIN and E0PIO */
orr r4 , r4 , #( M D R E F R _ E 1 P I N | M D R E F R _ E 0 P I N )
str r4 , [ r1 , #M D R E F R _ O F F S E T ] / * w r i t e b a c k M D R E F R * /
ldr r4 , [ r1 , #M D R E F R _ O F F S E T ]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
ldr r4 , =CONFIG_SYS_MDCNFG_VAL
bic r4 , r4 , #( M D C N F G _ D E 0 | M D C N F G _ D E 1 )
str r4 , [ r1 , #M D C N F G _ O F F S E T ] / * w r i t e b a c k M D C N F G * /
ldr r4 , [ r1 , #M D C N F G _ O F F S E T ]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
/* 100..200 <20> sec. */
ldr r3 , =OSCR / * r e s e t t h e O S T i m e r C o u n t t o z e r o * /
mov r2 , #0
str r2 , [ r3 ]
ldr r4 , =0x300 / * r e a l l y 0 x2 E 1 i s a b o u t 2 0 0 u s e c , * /
/* so 0x300 should be plenty */
1 :
ldr r2 , [ r3 ]
cmp r4 , r2
bgt 1 b
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */
/* SDRAM, as commonly specified in the power up sequence */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
/* There should 9 writes, since the first write doesn't */
/* trigger a refresh cycle on PXA250. See Intel PXA250 and */
/* PXA210 Processors Specification Update, */
/* Jan 2003, Errata #116, page 30. */
ldr r3 , =CONFIG_SYS_DRAM_BASE
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
str r2 , [ r3 ]
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
ldr r3 , [ r1 , #M D C N F G _ O F F S E T ]
orr r3 , r3 , #( M D C N F G _ D E 0 | M D C N F G _ D E 1 )
str r3 , [ r1 , #M D C N F G _ O F F S E T ]
/* Step 4h: Write MDMRS. */
ldr r2 , =CONFIG_SYS_MDMRS_VAL
str r2 , [ r1 , #M D M R S _ O F F S E T ]
/* We are finished with Intel's memory controller initialisation */
/* ---------------------------------------------------------------- */
/* Disable (mask) all interrupts at interrupt controller */
/* ---------------------------------------------------------------- */
initirqs :
mov r1 , #0 / * c l e a r i n t . l e v e l r e g i s t e r ( I R Q , n o t F I Q ) * /
ldr r2 , =ICLR
str r1 , [ r2 ]
ldr r2 , =ICMR / * m a s k a l l i n t e r r u p t s a t t h e c o n t r o l l e r * /
str r1 , [ r2 ]
/* ---------------------------------------------------------------- */
/* Clock initialisation */
/* ---------------------------------------------------------------- */
initclks :
/* Disable the peripheral clocks, and set the core clock frequency */
/* (hard-coding at 398.12MHz for now). */
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
ldr r1 , =CKEN
mov r2 , #0
str r2 , [ r1 ]
/* default value in case no valid rotary switch setting is found */
ldr r2 , = ( C C C R _ L 2 7 | C C C R _ M 2 | C C C R _ N 1 0 ) / * D E F A U L T : { 2 0 0 / 2 0 0 / 1 0 0 } * /
/* ... and write the core clock config register */
ldr r1 , =CCCR
str r2 , [ r1 ]
/* enable the 32Khz oscillator for RTC and PowerManager */
/ *
ldr r1 , =OSCC
mov r2 , #O S C C _ O O N
str r2 , [ r1 ]
* /
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60 :
ldr r2 , [ r1 ]
ands r2 , r2 , #1
beq 6 0 b
/* ---------------------------------------------------------------- */
/* */
/* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1 , =DRAM_SIZE
str r8 , [ r1 ]
/* Interrupt init: Mask all interrupts */
ldr r0 , =ICMR / * e n a b l e n o s o u r c e s * /
mov r1 , #0
str r1 , [ r0 ]
/* FIXME */
# ifndef D E B U G
/*Disable software and data breakpoints */
mov r0 ,#0
mcr p15 ,0 ,r0 ,c14 ,c8 ,0 / * i b c r0 * /
mcr p15 ,0 ,r0 ,c14 ,c9 ,0 / * i b c r1 * /
mcr p15 ,0 ,r0 ,c14 ,c4 ,0 / * d b c o n * /
/*Enable all debug functionality */
mov r0 ,#0x80000000
mcr p14 ,0 ,r0 ,c10 ,c0 ,0 / * d c s r * /
# endif
/* ---------------------------------------------------------------- */
/* End lowlevel_init */
/* ---------------------------------------------------------------- */
endlowlevel_init :
mov p c , l r
Marek Vasut