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Some code cleanup.

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This commit is contained in:
Wolfgang Denk
2007-03-04 01:36:05 +01:00
committed by Wolfgang Denk
parent b24444f1b3
commit 647d3c3eed
8 changed files with 78 additions and 94 deletions
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10
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -168,8 +168,8 @@ static void program_codt(unsigned long *dimm_populated,
static void program_mode(unsigned long *dimm_populated, static void program_mode(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks, unsigned long num_dimm_banks,
ddr_cas_id_t *selected_cas, ddr_cas_id_t *selected_cas,
int *write_recovery); int *write_recovery);
static void program_tr(unsigned long *dimm_populated, static void program_tr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks); unsigned long num_dimm_banks);
@ -185,7 +185,7 @@ static void program_copt1(unsigned long *dimm_populated,
static void program_initplr(unsigned long *dimm_populated, static void program_initplr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks, unsigned long num_dimm_banks,
ddr_cas_id_t selected_cas, ddr_cas_id_t selected_cas,
int write_recovery); int write_recovery);
static unsigned long is_ecc_enabled(void); static unsigned long is_ecc_enabled(void);
static void program_ecc(unsigned long *dimm_populated, static void program_ecc(unsigned long *dimm_populated,
@ -1110,7 +1110,7 @@ static void program_codt(unsigned long *dimm_populated,
modt3 = 0x00000000; modt3 = 0x00000000;
} }
} }
} else { } else {
codt |= SDRAM_CODT_DQS_2_5_V_DDR1; codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
modt0 = 0x00000000; modt0 = 0x00000000;
modt1 = 0x00000000; modt1 = 0x00000000;
@ -1149,7 +1149,7 @@ static void program_codt(unsigned long *dimm_populated,
static void program_initplr(unsigned long *dimm_populated, static void program_initplr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks, unsigned long num_dimm_banks,
ddr_cas_id_t selected_cas, ddr_cas_id_t selected_cas,
int write_recovery) int write_recovery)
{ {
u32 cas = 0; u32 cas = 0;

72
cpu/ppc4xx/start.S
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@ -1858,11 +1858,11 @@ pll_wait:
#endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */
#if defined(CONFIG_440) #if defined(CONFIG_440)
#define function_prolog(func_name) .text; \ #define function_prolog(func_name) .text; \
.align 2; \ .align 2; \
.globl func_name; \ .globl func_name; \
func_name: func_name:
#define function_epilog(func_name) .type func_name,@function; \ #define function_epilog(func_name) .type func_name,@function; \
.size func_name,.-func_name .size func_name,.-func_name
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
@ -1916,43 +1916,43 @@ pll_wait:
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
| dcbz_area. | dcbz_area.
+----------------------------------------------------------------------------*/ +----------------------------------------------------------------------------*/
function_prolog(dcbz_area) function_prolog(dcbz_area)
rlwinm. r5,r4,0,27,31 rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31 rlwinm r5,r4,27,5,31
beq ..d_ra2 beq ..d_ra2
addi r5,r5,0x0001 addi r5,r5,0x0001
..d_ra2:mtctr r5 ..d_ra2:mtctr r5
..d_ag2:dcbz r0,r3 ..d_ag2:dcbz r0,r3
addi r3,r3,32 addi r3,r3,32
bdnz ..d_ag2 bdnz ..d_ag2
sync sync
blr blr
function_epilog(dcbz_area) function_epilog(dcbz_area)
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
| dflush. Assume 32K at vector address is cachable. | dflush. Assume 32K at vector address is cachable.
+----------------------------------------------------------------------------*/ +----------------------------------------------------------------------------*/
function_prolog(dflush) function_prolog(dflush)
mfmsr r9 mfmsr r9
rlwinm r8,r9,0,15,13 rlwinm r8,r9,0,15,13
rlwinm r8,r8,0,17,15 rlwinm r8,r8,0,17,15
mtmsr r8 mtmsr r8
addi r3,r0,0x0000 addi r3,r0,0x0000
mtspr dvlim,r3 mtspr dvlim,r3
mfspr r3,ivpr mfspr r3,ivpr
addi r4,r0,1024 addi r4,r0,1024
mtctr r4 mtctr r4
..dflush_loop: ..dflush_loop:
lwz r6,0x0(r3) lwz r6,0x0(r3)
addi r3,r3,32 addi r3,r3,32
bdnz ..dflush_loop bdnz ..dflush_loop
addi r3,r3,-32 addi r3,r3,-32
mtctr r4 mtctr r4
..ag: dcbf r0,r3 ..ag: dcbf r0,r3
addi r3,r3,-32 addi r3,r3,-32
bdnz ..ag bdnz ..ag
sync sync
mtmsr r9 mtmsr r9
blr blr
function_epilog(dflush) function_epilog(dflush)
#endif /* CONFIG_440 */ #endif /* CONFIG_440 */

1
doc/README.mpc7448hpc2
View File

@ -182,4 +182,3 @@ SW4[7-8]: PCI/PCI-X frequency control
- -
SW4=0 PCI-X mode at 133 MHz allowed SW4=0 PCI-X mode at 133 MHz allowed
SW4=1 PCI-X mode limited to 100 MHz SW4=1 PCI-X mode limited to 100 MHz

31
drivers/tsi108_i2c.c
View File

@ -82,15 +82,10 @@ static int i2c_read_byte (
/* Wait until operation completed */ /* Wait until operation completed */
do { do {
/* Read I2C operation status */ /* Read I2C operation status */
temp = temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
*(u32 *) (CFG_TSI108_CSR_BASE + chan_offset +
I2C_CNTRL2);
if (0 == if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
(temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) if (0 == (temp &
{
if (0 ==
(temp &
(I2C_CNTRL2_I2C_CFGERR | (I2C_CNTRL2_I2C_CFGERR |
I2C_CNTRL2_I2C_TO_ERR)) I2C_CNTRL2_I2C_TO_ERR))
) { ) {
@ -152,9 +147,7 @@ int i2c_read (uchar chip_addr, uint byte_addr, int alen,
/* Check for valid I2C address */ /* Check for valid I2C address */
if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
while (len--) { while (len--) {
op_status = op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
i2c_read_byte(i2c_if, chip_addr, byte_addr++,
buffer++);
if (TSI108_I2C_SUCCESS != op_status) { if (TSI108_I2C_SUCCESS != op_status) {
DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
@ -182,10 +175,7 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
/* Check if I2C operation is in progress */ /* Check if I2C operation is in progress */
temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
if (0 == if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
(temp &
(I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
{
/* Place data into the I2C Tx Register */ /* Place data into the I2C Tx Register */
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_TX_DATA) = (u32) * buffer; I2C_TX_DATA) = (u32) * buffer;
@ -209,15 +199,10 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
/* Wait until operation completed */ /* Wait until operation completed */
do { do {
/* Read I2C operation status */ /* Read I2C operation status */
temp = temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2);
if (0 == if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
(temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) if (0 == (temp &
{
if (0 ==
(temp &
(I2C_CNTRL2_I2C_CFGERR | (I2C_CNTRL2_I2C_CFGERR |
I2C_CNTRL2_I2C_TO_ERR))) { I2C_CNTRL2_I2C_TO_ERR))) {
op_status = TSI108_I2C_SUCCESS; op_status = TSI108_I2C_SUCCESS;