From 772f8765d71a1929111288a2ed9b5577740b1538 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Mon, 25 Sep 2017 16:39:57 +0800 Subject: [PATCH 1/3] ARM: socfpga: add bindings doc for arria10 fpga manager This DT binding doc is porting from Linux DT binding doc. commit 1adcbea4201a6852362aa5ece573f1f169b28113 Add a device tree bindings document for the SoCFPGA Arria10 FPGA Manager driver. Signed-off-by: Alan Tull Acked-by: Rob Herring Acked-By: Moritz Fischer Signed-off-by: Rob Herring Signed-off-by: Tien Fong Chee --- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt new file mode 100644 index 0000000000..2fd8e7a847 --- /dev/null +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -0,0 +1,19 @@ +Altera SOCFPGA Arria10 FPGA Manager + +Required properties: +- compatible : should contain "altr,socfpga-a10-fpga-mgr" +- reg : base address and size for memory mapped io. + - The first index is for FPGA manager register access. + - The second index is for writing FPGA configuration data. +- resets : Phandle and reset specifier for the device's reset. +- clocks : Clocks used by the device. + +Example: + + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + }; From bd08ce8f5e2bedd5e2ba51891bba09dc10760004 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Mon, 25 Sep 2017 16:40:01 +0800 Subject: [PATCH 2/3] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes Existing FPGA program write is always assume RBF data >= 32 bytes, so any rbf data less than 32 bytes writing to FPGA would be failed. This patch enhances the FPGA program write to support rbf data with size >= 4 bytes. Signed-off-by: Tien Fong Chee --- drivers/fpga/socfpga.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 28fa16b944..6e14ebd26d 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2017 Altera Corporation * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4); asm volatile( + " cmp %2, #0\n" + " beq 2f\n" "1: ldmia %0!, {r0-r7}\n" " stmia %1!, {r0-r7}\n" " sub %1, #32\n" " subs %2, #1\n" " bne 1b\n" - " cmp %3, #0\n" - " beq 3f\n" - "2: ldr %2, [%0], #4\n" + "2: cmp %3, #0\n" + " beq 4f\n" + "3: ldr %2, [%0], #4\n" " str %2, [%1]\n" " subs %3, #1\n" - " bne 2b\n" - "3: nop\n" + " bne 3b\n" + "4: nop\n" : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) : : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc"); } From eb57c0be14d114c7d0965918154fdfb414634108 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Mon, 25 Sep 2017 16:40:03 +0800 Subject: [PATCH 3/3] fdt: Add compatible strings for Arria 10 Add compatible strings for Intel Arria 10 SoCFPGA device. Signed-off-by: Tien Fong Chee --- include/fdtdec.h | 2 ++ lib/fdtdec.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/fdtdec.h b/include/fdtdec.h index 1ba02be8e1..0fb3e07212 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -159,6 +159,8 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ + COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */ + COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 45f3fe7baf..c4582eacca 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -71,6 +71,8 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"), COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"), COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), + COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"), + COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id)