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powerpc/8xxx: share PIC defines among 85xx and 86xx

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fixes breakeage introduced by commit
a37c36f4e7 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kim Phillips
2010-08-09 18:39:57 -05:00
committed by Kumar Gala
parent bd23130781
commit 680c613a5c
8 changed files with 19 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/cpu/mpc85xx/cpu.c
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@ -74,7 +74,7 @@ int checkcpu (void)
puts("Unicore software on multiprocessor system!!\n" puts("Unicore software on multiprocessor system!!\n"
"To enable mutlticore build define CONFIG_MP\n"); "To enable mutlticore build define CONFIG_MP\n");
#endif #endif
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
printf("CPU%d: ", pic->whoami); printf("CPU%d: ", pic->whoami);
} else { } else {
puts("CPU: "); puts("CPU: ");

2
arch/powerpc/cpu/mpc85xx/cpu_init.c
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@ -179,7 +179,7 @@ static void corenet_tb_init(void)
volatile ccsr_rcpm_t *rcpm = volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic = volatile ccsr_pic_t *pic =
(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami); u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */ /* Enable the timebase register for this core */

2
arch/powerpc/cpu/mpc85xx/interrupts.c
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@ -35,7 +35,7 @@
int interrupt_init_cpu(unsigned int *decrementer_count) int interrupt_init_cpu(unsigned int *decrementer_count)
{ {
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
out_be32(&pic->gcr, MPC85xx_PICGCR_RST); out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)

6
arch/powerpc/cpu/mpc85xx/mp.c
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@ -38,7 +38,7 @@ u32 get_my_id()
int cpu_reset(int nr) int cpu_reset(int nr)
{ {
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
out_be32(&pic->pir, 1 << nr); out_be32(&pic->pir, 1 << nr);
/* the dummy read works around an errata on early 85xx MP PICs */ /* the dummy read works around an errata on early 85xx MP PICs */
(void)in_be32(&pic->pir); (void)in_be32(&pic->pir);
@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg)
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg)
volatile u32 bpcr; volatile u32 bpcr;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
u32 devdisr; u32 devdisr;
int timeout = 10; int timeout = 10;

2
arch/powerpc/cpu/mpc85xx/traps.c
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@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs)
void void
ExtIntException(struct pt_regs *regs) ExtIntException(struct pt_regs *regs)
{ {
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
uint vect; uint vect;

8
arch/powerpc/cpu/mpc8xxx/cpu.c
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@ -110,13 +110,15 @@ struct cpu_type *identify_cpu(u32 ver)
} }
int cpu_numcores() { int cpu_numcores() {
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->cpu; struct cpu_type *cpu = gd->cpu;
/* better to query feature reporting register than just assume 1 */ /* better to query feature reporting register than just assume 1 */
#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
#define MPC8xxx_PICFRR_NCPU_SHIFT 8
if (cpu == &cpu_type_unknown) if (cpu == &cpu_type_unknown)
return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >> return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
MPC85xx_PICFRR_NCPU_SHIFT) + 1; MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
return cpu->num_cores; return cpu->num_cores;
} }

4
arch/powerpc/include/asm/immap_85xx.h
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@ -760,8 +760,6 @@ typedef struct ccsr_pic {
u32 eoi; /* End Of IRQ */ u32 eoi; /* End Of IRQ */
u8 res9[3916]; u8 res9[3916];
u32 frr; /* Feature Reporting */ u32 frr; /* Feature Reporting */
#define MPC85xx_PICFRR_NCPU_MASK 0x00001f00
#define MPC85xx_PICFRR_NCPU_SHIFT 8
u8 res10[28]; u8 res10[28];
u32 gcr; /* Global Configuration */ u32 gcr; /* Global Configuration */
#define MPC85xx_PICGCR_RST 0x80000000 #define MPC85xx_PICGCR_RST 0x80000000
@ -2301,7 +2299,7 @@ typedef struct ccsr_pme {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
#define CONFIG_SYS_MPC85xx_PIC_ADDR \ #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
#define CONFIG_SYS_MPC85xx_CPM_ADDR \ #define CONFIG_SYS_MPC85xx_CPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)

9
arch/powerpc/include/asm/immap_86xx.h
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@ -1250,12 +1250,15 @@ typedef struct immap {
extern immap_t *immr; extern immap_t *immr;
#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) #define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) #define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) #define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
#ifdef CONFIG_MPC8610 #ifdef CONFIG_MPC8610