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ddr: altera: Configuring SDRAM extra cycles timing parameters

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To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Chin Liang See
2016-09-21 10:25:56 +08:00
committed by Marek Vasut
parent 5ac5861c4b
commit 89a54abf1b
4 changed files with 18 additions and 2 deletions
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3
drivers/ddr/altera/sdram.c
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@ -418,6 +418,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
debug("Configuring DRAMODT\n");
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
debug("Configuring EXTRATIME1\n");
writel(cfg->extratime1, &sdr_ctrl->extratime1);
}
/**