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Fman/t4240: some fix for 10G XAUI

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1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Shaohui Xie
2013-03-25 07:33:17 +00:00
committed by Andy Fleming
parent 4e5c9261be
commit 944b6ccf1b
4 changed files with 20 additions and 6 deletions
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2
drivers/net/fm/eth.c
View File

@ -568,6 +568,8 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
num = fm_eth->num;
#ifdef CONFIG_SYS_FMAN_V3
if (fm_eth->type == FM_ETH_10G_E)
num += 8;
base = &reg->memac[num].fm_memac;
phyregs = &reg->memac[num].fm_memac_mdio;
#else

6
drivers/net/fm/init.c
View File

@ -74,9 +74,15 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(1, 2),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(2, 2),
#endif
};
int fm_standard_init(bd_t *bis)

14
drivers/net/fm/t4240.c
View File

@ -70,12 +70,18 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1 || port == FM1_10GEC2)
&& (is_serdes_configured(XAUI_FM1)))
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
(is_serdes_configured(XAUI_FM1_MAC10)) ||
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM2_10GEC1 || port == FM2_10GEC2)
&& (is_serdes_configured(XAUI_FM2)))
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
((is_serdes_configured(XAUI_FM2_MAC9)) ||
(is_serdes_configured(XAUI_FM2_MAC10)) ||
(is_serdes_configured(XFI_FM2_MAC9)) ||
(is_serdes_configured(XFI_FM2_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */