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fsl-ddr: Add extra cycle to turnaround times

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Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Dave Liu
2009-12-08 11:56:48 +08:00
committed by Kumar Gala
parent f8d05e5e58
commit 99bac479dd
1 changed files with 2 additions and 0 deletions
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2
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
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@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
#else /* CONFIG_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?