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arc/cache: Flush & invalidate all caches right before enabling IOC

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According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
2016-06-08 08:04:03 +03:00
parent bd91508b50
commit a4a43fcf9c
1 changed files with 3 additions and 0 deletions
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3
arch/arc/lib/cache.c
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@ -209,6 +209,9 @@ void cache_init(void)
read_decode_cache_bcr_arcv2(); read_decode_cache_bcr_arcv2();
if (ioc_exists) { if (ioc_exists) {
flush_dcache_all();
invalidate_dcache_all();
/* IO coherency base - 0x8z */ /* IO coherency base - 0x8z */
write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000); write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
/* IO coherency aperture size - 512Mb: 0x8z-0xAz */ /* IO coherency aperture size - 512Mb: 0x8z-0xAz */