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ARM: socfpga: Rename MCVEVK

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The board is now manufactured by Aries Embedded GmbH , rename it.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut
2017-04-05 13:17:03 +02:00
parent 4c0f3e7f7b
commit a548bc511f
11 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/socfpga_cyclone5_mcvevk.dts
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@ -7,7 +7,7 @@
#include "socfpga_cyclone5.dtsi" #include "socfpga_cyclone5.dtsi"
/ { / {
model = "DENX MCVEVK"; model = "Aries MCVEVK";
compatible = "altr,socfpga-cyclone5", "altr,socfpga"; compatible = "altr,socfpga-cyclone5", "altr,socfpga";
chosen { chosen {

10
arch/arm/mach-socfpga/Kconfig
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@ -56,8 +56,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)" bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5 select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_DENX_MCVEVK config TARGET_SOCFPGA_ARIES_MCVEVK
bool "DENX MCVEVK (Cyclone V)" bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5 select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_EBV_SOCRATES config TARGET_SOCFPGA_EBV_SOCRATES
@ -97,7 +97,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "is1" if TARGET_SOCFPGA_IS1 default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500 default "sr1500" if TARGET_SOCFPGA_SR1500
@ -106,7 +106,7 @@ config SYS_BOARD
config SYS_VENDOR config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@ -122,7 +122,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_is1" if TARGET_SOCFPGA_IS1 default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500

4
board/denx/mcvevk/MAINTAINERS → board/aries/mcvevk/MAINTAINERS
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@ -1,5 +1,5 @@
SOCKIT BOARD Aries MCVEVK BOARD
M: Marek Vasut <marex@denx.de> M: Marek Vasut <marek.vasut@gmail.com>
S: Maintained S: Maintained
F: include/configs/socfpga_mcvevk.h F: include/configs/socfpga_mcvevk.h
F: configs/socfpga_mcvevk_defconfig F: configs/socfpga_mcvevk_defconfig

0
board/denx/mcvevk/Makefile → board/aries/mcvevk/Makefile
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0
board/denx/mcvevk/qts/iocsr_config.h → board/aries/mcvevk/qts/iocsr_config.h
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0
board/denx/mcvevk/qts/pinmux_config.h → board/aries/mcvevk/qts/pinmux_config.h
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0
board/denx/mcvevk/qts/pll_config.h → board/aries/mcvevk/qts/pll_config.h
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0
board/denx/mcvevk/qts/sdram_config.h → board/aries/mcvevk/qts/sdram_config.h
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0
board/denx/mcvevk/socfpga.c → board/aries/mcvevk/socfpga.c
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2
configs/socfpga_mcvevk_defconfig
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@ -1,7 +1,7 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y
CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_SPL_STACK_R_ADDR=0x00800000
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
CONFIG_FIT=y CONFIG_FIT=y

6
include/configs/socfpga_mcvevk.h
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@ -3,8 +3,8 @@
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#ifndef __CONFIG_DENX_MCVEVK_H__ #ifndef __CONFIG_ARIES_MCVEVK_H__
#define __CONFIG_DENX_MCVEVK_H__ #define __CONFIG_ARIES_MCVEVK_H__
#include <asm/arch/base_addr_ac5.h> #include <asm/arch/base_addr_ac5.h>
@ -105,4 +105,4 @@
/* The rest of the configuration is shared */ /* The rest of the configuration is shared */
#include <configs/socfpga_common.h> #include <configs/socfpga_common.h>
#endif /* __CONFIG_DENX_MCVEVK_H__ */ #endif /* __CONFIG_ARIES_MCVEVK_H__ */