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powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs

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The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Prabhakar Kushwaha
2011-02-01 15:55:58 +00:00
committed by Kumar Gala
parent 2d7534a344
commit b03a466d6c
4 changed files with 60 additions and 1 deletions
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include/pci.h
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@ -306,6 +306,7 @@
#define PCI_DCR 0x54 /* PCIe Device Control Register */
#define PCI_DSR 0x56 /* PCIe Device Status Register */
#define PCI_LSR 0x5e /* PCIe Link Status Register */
#define PCI_LCR 0x5c /* PCIe Link Control Register */
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
#define PCI_LTSSM_L0 0x16 /* L0 state */