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powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]

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The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but
the mask omitted the LSB.  This patch provides a 2-bit wide mask.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
James Yang
2013-07-22 09:35:26 -07:00
committed by York Sun
parent a8d9758d01
commit c45f5c08b7
1 changed files with 1 additions and 1 deletions
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2
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
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@ -364,7 +364,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
ddr->timing_cfg_3 = (0
| ((ext_pretoact & 0x1) << 28)
| ((ext_acttopre & 0x2) << 24)
| ((ext_acttopre & 0x3) << 24)
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)