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spi: stm32_qspi: assign functional operation mode in _stm32_qspi_gen_ccr

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This patch assigns the functional operation mode in _stm32_qspi_gen_ccr
function.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Christophe Kerello
2018-07-09 15:32:37 +02:00
committed by Tom Rini
parent f53424e650
commit ceff933e1e
1 changed files with 8 additions and 9 deletions
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17
drivers/spi/stm32_qspi.c
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@ -220,7 +220,7 @@ static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
cs ? STM32_QSPI_CR_FSEL : 0); cs ? STM32_QSPI_CR_FSEL : 0);
} }
static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)
{ {
unsigned int ccr_reg = 0; unsigned int ccr_reg = 0;
u8 imode, admode, dmode; u8 imode, admode, dmode;
@ -258,8 +258,11 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
<< STM32_QSPI_CCR_ADSIZE_SHIFT); << STM32_QSPI_CCR_ADSIZE_SHIFT);
ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT); ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
} }
ccr_reg |= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);
ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT); ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
ccr_reg |= cmd; ccr_reg |= cmd;
return ccr_reg; return ccr_reg;
} }
@ -272,8 +275,7 @@ static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
| CMD_HAS_DUMMY; | CMD_HAS_DUMMY;
priv->dummycycles = flash->dummy_byte * 8; priv->dummycycles = flash->dummy_byte * 8;
ccr_reg = _stm32_qspi_gen_ccr(priv); ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
_stm32_qspi_wait_for_not_busy(priv); _stm32_qspi_wait_for_not_busy(priv);
@ -359,9 +361,8 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
} }
if (flags & SPI_XFER_END) { if (flags & SPI_XFER_END) {
ccr_reg = _stm32_qspi_gen_ccr(priv); ccr_reg = _stm32_qspi_gen_ccr(priv,
ccr_reg |= STM32_QSPI_CCR_IND_WRITE STM32_QSPI_CCR_IND_WRITE);
<< STM32_QSPI_CCR_FMODE_SHIFT;
_stm32_qspi_wait_for_not_busy(priv); _stm32_qspi_wait_for_not_busy(priv);
@ -392,9 +393,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
} }
} }
} else if (din) { } else if (din) {
ccr_reg = _stm32_qspi_gen_ccr(priv); ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);
ccr_reg |= STM32_QSPI_CCR_IND_READ
<< STM32_QSPI_CCR_FMODE_SHIFT;
_stm32_qspi_wait_for_not_busy(priv); _stm32_qspi_wait_for_not_busy(priv);