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powerpc/mpc85xx: Workaround for A-005812

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Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2013-06-25 11:37:49 -07:00
parent c63e137014
commit d217a9ad01
4 changed files with 29 additions and 0 deletions
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15
arch/powerpc/cpu/mpc85xx/release.S
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@ -226,6 +226,21 @@ __secondary_start_page:
2:
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
/*
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
* write shadow mode. This code should run after other code setting
* DCWS.
*/
mfspr r3,L1CSR2
andis. r3,r3,(L1CSR2_DCWS)@h
beq 1f
mfspr r3, SPRN_HDBCR0
oris r3, r3, 0x8000
mtspr SPRN_HDBCR0, r3
1:
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
mfspr r3,SPRN_SVR