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Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

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Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2018-12-10 17:12:52 -05:00
parent 2918f58faa 4909b89ec7
commit d94604d558
112 changed files with 4104 additions and 543 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
board/freescale/common/vid.c
View File

@ -318,6 +318,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
static int set_voltage_to_LTC(int i2caddress, int vdd)
{
int ret, vdd_last, vdd_target = vdd;
int count = 100, temp = 0;
/* Scale up to the LTC resolution is 1/4096V */
vdd = (vdd * 4096) / 1000;
@ -343,7 +344,9 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
printf("VID: Couldn't read sensor abort VID adjust\n");
return -1;
}
} while (vdd_last != vdd_target);
count--;
temp = vdd_last - vdd_target;
} while ((abs(temp) > 2) && (count > 0));
return vdd_last;
}
@ -379,6 +382,42 @@ int adjust_vdd(ulong vdd_override)
int ret, i2caddress;
unsigned long vdd_string_override;
char *vdd_string;
#ifdef CONFIG_ARCH_LX2160A
static const u16 vdd[32] = {
8250,
7875,
7750,
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
8000,
8125,
8250,
0, /* reserved */
8500,
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
0, /* reserved */
};
#else
#ifdef CONFIG_ARCH_LS1088A
static const uint16_t vdd[32] = {
10250,
@ -450,6 +489,7 @@ int adjust_vdd(ulong vdd_override)
0, /* reserved */
0, /* reserved */
};
#endif
#endif
struct vdd_drive {
u8 vid;

4
board/freescale/ls1012afrdm/MAINTAINERS
View File

@ -1,9 +1,13 @@
LS1012AFRDM BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1012afrdm/
F: include/configs/ls1012afrdm.h
F: configs/ls1012afrdm_qspi_defconfig
F: configs/ls1012afrdm_tfa_defconfig
F: configs/ls1012afrwy_tfa_defconfig
F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
LS1012AFRWY BOARD
M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>

28
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@ -80,6 +80,30 @@ int esdhc_status_fixup(void *blob, const char *compat)
}
#endif
#ifdef CONFIG_TFABOOT
int dram_init(void)
{
#ifdef CONFIG_TARGET_LS1012AFRWY
int board_rev;
#endif
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size) {
#ifdef CONFIG_TARGET_LS1012AFRWY
board_rev = get_board_version();
if (board_rev & BOARD_REV_C)
gd->ram_size = SYS_SDRAM_SIZE_1024;
else
gd->ram_size = SYS_SDRAM_SIZE_512;
#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#endif
}
return 0;
}
#else
int dram_init(void)
{
#ifdef CONFIG_TARGET_LS1012AFRWY
@ -122,6 +146,7 @@ int dram_init(void)
return 0;
}
#endif
int board_early_init_f(void)
{
@ -139,7 +164,8 @@ int board_init(void)
* Set CCI-400 control override register to enable barrier
* transaction
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];

10
board/freescale/ls1012aqds/Kconfig
View File

@ -16,6 +16,12 @@ config SYS_LS_PPA_FW_ADDR
hex "PPA Firmware Addr"
default 0x40400000
if CHAIN_OF_TRUST
config SYS_LS_PPA_ESBC_ADDR
hex "PPA Firmware HDR Addr"
default 0x40680000
endif
if FSL_PFE
config BOARD_SPECIFIC_OPTIONS # dummy
@ -33,6 +39,10 @@ config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40a00000
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
default 0x40700000
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
default 0x03800000

3
board/freescale/ls1012aqds/MAINTAINERS
View File

@ -1,6 +1,9 @@
LS1012AQDS BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1012aqds/
F: include/configs/ls1012aqds.h
F: configs/ls1012aqds_qspi_defconfig
F: configs/ls1012aqds_tfa_defconfig
F: configs/ls1012aqds_tfa_SECURE_BOOT_defconfig

23
board/freescale/ls1012aqds/ls1012aqds.c
View File

@ -18,12 +18,14 @@
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
#include <environment.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
@ -55,6 +57,16 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_TFABOOT
int dram_init(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
#else
int dram_init(void)
{
static const struct fsl_mmdc_info mparam = {
@ -74,7 +86,6 @@ int dram_init(void)
};
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
@ -83,6 +94,7 @@ int dram_init(void)
return 0;
}
#endif
int board_early_init_f(void)
{
@ -110,8 +122,9 @@ int board_init(void)
/* Set CCI-400 control override register to enable barrier
* transaction */
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
if (current_el() == 3)
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
@ -121,6 +134,10 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0];
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

4
board/freescale/ls1012ardb/Kconfig
View File

@ -33,6 +33,10 @@ config SYS_LS_PFE_FW_ADDR
hex "Flash address of PFE firmware"
default 0x40a00000
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
default 0x40700000
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
default 0x03800000

4
board/freescale/ls1012ardb/MAINTAINERS
View File

@ -1,9 +1,13 @@
LS1012ARDB BOARD
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
F: include/configs/ls1012ardb.h
F: configs/ls1012ardb_qspi_defconfig
F: configs/ls1012ardb_tfa_defconfig
F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
F: configs/ls1012a2g5rdb_tfa_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained

16
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -87,8 +87,19 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_TFABOOT
int dram_init(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
#else
int dram_init(void)
{
#ifndef CONFIG_TFABOOT
static const struct fsl_mmdc_info mparam = {
0x05180000, /* mdctl */
0x00030035, /* mdpdc */
@ -106,6 +117,7 @@ int dram_init(void)
};
mmdc_init(&mparam);
#endif
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
@ -115,6 +127,7 @@ int dram_init(void)
return 0;
}
#endif
int board_early_init_f(void)
@ -132,7 +145,8 @@ int board_init(void)
* Set CCI-400 control override register to enable barrier
* transaction
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();

1
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -244,6 +244,7 @@ void board_init_f(ulong dummy)
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
timer_init();
dram_init();
/* Allow OCRAM access permission as R/W */

1
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -467,6 +467,7 @@ void board_init_f(ulong dummy)
preloader_console_init();
timer_init();
dram_init();
/* Allow OCRAM access permission as R/W */

3
board/freescale/ls1043aqds/MAINTAINERS
View File

@ -1,5 +1,6 @@
LS1043AQDS BOARD
M: Mingkai Hu <mingkai.hu@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1043aqds/
F: include/configs/ls1043aqds.h
@ -10,3 +11,5 @@ F: configs/ls1043aqds_sdcard_ifc_defconfig
F: configs/ls1043aqds_sdcard_qspi_defconfig
F: configs/ls1043aqds_qspi_defconfig
F: configs/ls1043aqds_lpuart_defconfig
F: configs/ls1043aqds_tfa_defconfig
F: configs/ls1043aqds_tfa_SECURE_BOOT_defconfig

11
board/freescale/ls1043aqds/ddr.c
View File

@ -108,6 +108,16 @@ found:
#endif
}
#ifdef CONFIG_TFABOOT
int fsl_initdram(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
}
#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@ -131,3 +141,4 @@ int fsl_initdram(void)
return 0;
}
#endif

147
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -13,6 +13,7 @@
#include <asm/arch/ppa.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
@ -46,8 +47,135 @@ enum {
#define CFG_UART_MUX_SHIFT 1
#define CFG_LPUART_EN 0x1
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
CONFIG_SYS_NOR0_CSPR,
CONFIG_SYS_NOR0_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nor1",
CONFIG_SYS_NOR1_CSPR,
CONFIG_SYS_NOR1_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
},
},
{
"fpga",
CONFIG_SYS_FPGA_CSPR,
CONFIG_SYS_FPGA_CSPR_EXT,
CONFIG_SYS_FPGA_AMASK,
CONFIG_SYS_FPGA_CSOR,
{
CONFIG_SYS_FPGA_FTIM0,
CONFIG_SYS_FPGA_FTIM1,
CONFIG_SYS_FPGA_FTIM2,
CONFIG_SYS_FPGA_FTIM3
},
}
};
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
},
},
{
"nor0",
CONFIG_SYS_NOR0_CSPR,
CONFIG_SYS_NOR0_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nor1",
CONFIG_SYS_NOR1_CSPR,
CONFIG_SYS_NOR1_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"fpga",
CONFIG_SYS_FPGA_CSPR,
CONFIG_SYS_FPGA_CSPR_EXT,
CONFIG_SYS_FPGA_AMASK,
CONFIG_SYS_FPGA_CSOR,
{
CONFIG_SYS_FPGA_FTIM0,
CONFIG_SYS_FPGA_FTIM1,
CONFIG_SYS_FPGA_FTIM2,
CONFIG_SYS_FPGA_FTIM3
},
}
};
void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
{
enum boot_src src = get_boot_src();
if (src == BOOT_SOURCE_IFC_NAND)
regs_info->regs = ifc_cfg_nand_boot;
else
regs_info->regs = ifc_cfg_nor_boot;
regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
}
#endif
int checkboard(void)
{
#ifdef CONFIG_TFABOOT
enum boot_src src = get_boot_src();
#endif
char buf[64];
#ifndef CONFIG_SD_BOOT
u8 sw;
@ -55,6 +183,12 @@ int checkboard(void)
puts("Board: LS1043AQDS, boot from ");
#ifdef CONFIG_TFABOOT
if (src == BOOT_SOURCE_SD_MMC)
puts("SD\n");
else {
#endif
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
@ -73,6 +207,9 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
#ifdef CONFIG_TFABOOT
}
#endif
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
@ -156,7 +293,8 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
@ -386,3 +524,10 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
#ifdef CONFIG_TFABOOT
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif

3
board/freescale/ls1043ardb/MAINTAINERS
View File

@ -1,5 +1,6 @@
LS1043A BOARD
M: Mingkai Hu <mingkai.hu@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1043ardb/
F: board/freescale/ls1043ardb/ls1043ardb.c
@ -7,6 +8,8 @@ F: include/configs/ls1043ardb.h
F: configs/ls1043ardb_defconfig
F: configs/ls1043ardb_nand_defconfig
F: configs/ls1043ardb_sdcard_defconfig
F: configs/ls1043ardb_tfa_defconfig
F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
LS1043A_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>

14
board/freescale/ls1043ardb/ddr.c
View File

@ -205,6 +205,19 @@ phys_size_t fixed_sdram(void)
}
#endif
#ifdef CONFIG_TFABOOT
int fsl_initdram(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
#ifdef CONFIG_SYS_DDR_RAW_TIMING
gd->ram_size = fsl_ddr_sdram_size();
#else
gd->ram_size = 0x80000000;
#endif
return 0;
}
#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@ -236,3 +249,4 @@ int fsl_initdram(void)
return 0;
}
#endif

110
board/freescale/ls1043ardb/ls1043ardb.c
View File

@ -27,6 +27,104 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor",
CONFIG_SYS_NOR_CSPR,
CONFIG_SYS_NOR_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
},
},
{
"cpld",
CONFIG_SYS_CPLD_CSPR,
CONFIG_SYS_CPLD_CSPR_EXT,
CONFIG_SYS_CPLD_AMASK,
CONFIG_SYS_CPLD_CSOR,
{
CONFIG_SYS_CPLD_FTIM0,
CONFIG_SYS_CPLD_FTIM1,
CONFIG_SYS_CPLD_FTIM2,
CONFIG_SYS_CPLD_FTIM3
},
}
};
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
},
},
{
"nor",
CONFIG_SYS_NOR_CSPR,
CONFIG_SYS_NOR_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"cpld",
CONFIG_SYS_CPLD_CSPR,
CONFIG_SYS_CPLD_CSPR_EXT,
CONFIG_SYS_CPLD_AMASK,
CONFIG_SYS_CPLD_CSOR,
{
CONFIG_SYS_CPLD_FTIM0,
CONFIG_SYS_CPLD_FTIM1,
CONFIG_SYS_CPLD_FTIM2,
CONFIG_SYS_CPLD_FTIM3
},
}
};
void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
{
enum boot_src src = get_boot_src();
if (src == BOOT_SOURCE_IFC_NAND)
regs_info->regs = ifc_cfg_nand_boot;
else
regs_info->regs = ifc_cfg_nor_boot;
regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
}
#endif
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
@ -38,6 +136,9 @@ int board_early_init_f(void)
int checkboard(void)
{
#ifdef CONFIG_TFABOOT
enum boot_src src = get_boot_src();
#endif
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
@ -47,6 +148,12 @@ int checkboard(void)
printf("Board: LS1043ARDB, boot from ");
#ifdef CONFIG_TFABOOT
if (src == BOOT_SOURCE_SD_MMC)
puts("SD\n");
else {
#endif
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
@ -64,6 +171,9 @@ int checkboard(void)
printf("Invalid setting of SW4\n");
#endif
#ifdef CONFIG_TFABOOT
}
#endif
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));

3
board/freescale/ls1046aqds/MAINTAINERS
View File

@ -1,5 +1,6 @@
LS1046AQDS BOARD
M: Mingkai Hu <Mingkai.Hu@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1046aqds/
F: include/configs/ls1046aqds.h
@ -9,6 +10,8 @@ F: configs/ls1046aqds_sdcard_ifc_defconfig
F: configs/ls1046aqds_sdcard_qspi_defconfig
F: configs/ls1046aqds_qspi_defconfig
F: configs/ls1046aqds_lpuart_defconfig
F: configs/ls1046aqds_tfa_defconfig
F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
M: Sumit Garg <sumit.garg@nxp.com>
S: Maintained

11
board/freescale/ls1046aqds/ddr.c
View File

@ -92,6 +92,16 @@ found:
popts->cpo_sample = 0x70;
}
#ifdef CONFIG_TFABOOT
int fsl_initdram(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
}
#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@ -116,3 +126,4 @@ int fsl_initdram(void)
return 0;
}
#endif

148
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -13,6 +13,7 @@
#include <asm/arch/ppa.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
@ -32,12 +33,140 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nor0",
CONFIG_SYS_NOR0_CSPR,
CONFIG_SYS_NOR0_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nor1",
CONFIG_SYS_NOR1_CSPR,
CONFIG_SYS_NOR1_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
},
},
{
"fpga",
CONFIG_SYS_FPGA_CSPR,
CONFIG_SYS_FPGA_CSPR_EXT,
CONFIG_SYS_FPGA_AMASK,
CONFIG_SYS_FPGA_CSOR,
{
CONFIG_SYS_FPGA_FTIM0,
CONFIG_SYS_FPGA_FTIM1,
CONFIG_SYS_FPGA_FTIM2,
CONFIG_SYS_FPGA_FTIM3
},
}
};
struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
"nand",
CONFIG_SYS_NAND_CSPR,
CONFIG_SYS_NAND_CSPR_EXT,
CONFIG_SYS_NAND_AMASK,
CONFIG_SYS_NAND_CSOR,
{
CONFIG_SYS_NAND_FTIM0,
CONFIG_SYS_NAND_FTIM1,
CONFIG_SYS_NAND_FTIM2,
CONFIG_SYS_NAND_FTIM3
},
},
{
"nor0",
CONFIG_SYS_NOR0_CSPR,
CONFIG_SYS_NOR0_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"nor1",
CONFIG_SYS_NOR1_CSPR,
CONFIG_SYS_NOR1_CSPR_EXT,
CONFIG_SYS_NOR_AMASK,
CONFIG_SYS_NOR_CSOR,
{
CONFIG_SYS_NOR_FTIM0,
CONFIG_SYS_NOR_FTIM1,
CONFIG_SYS_NOR_FTIM2,
CONFIG_SYS_NOR_FTIM3
},
},
{
"fpga",
CONFIG_SYS_FPGA_CSPR,
CONFIG_SYS_FPGA_CSPR_EXT,
CONFIG_SYS_FPGA_AMASK,
CONFIG_SYS_FPGA_CSOR,
{
CONFIG_SYS_FPGA_FTIM0,
CONFIG_SYS_FPGA_FTIM1,
CONFIG_SYS_FPGA_FTIM2,
CONFIG_SYS_FPGA_FTIM3
},
}
};
void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
{
enum boot_src src = get_boot_src();
if (src == BOOT_SOURCE_IFC_NAND)
regs_info->regs = ifc_cfg_nand_boot;
else
regs_info->regs = ifc_cfg_nor_boot;
regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
}
#endif
enum {
MUX_TYPE_GPIO,
};
int checkboard(void)
{
#ifdef CONFIG_TFABOOT
enum boot_src src = get_boot_src();
#endif
char buf[64];
#ifndef CONFIG_SD_BOOT
u8 sw;
@ -45,6 +174,12 @@ int checkboard(void)
puts("Board: LS1046AQDS, boot from ");
#ifdef CONFIG_TFABOOT
if (src == BOOT_SOURCE_SD_MMC)
puts("SD\n");
else {
#endif
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
@ -63,6 +198,9 @@ int checkboard(void)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
#ifdef CONFIG_TFABOOT
}
#endif
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
@ -153,7 +291,8 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
@ -342,3 +481,10 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
#ifdef CONFIG_TFABOOT
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif

3
board/freescale/ls1046ardb/MAINTAINERS
View File

@ -1,5 +1,6 @@
LS1046A BOARD
M: Mingkai Hu <mingkai.hu@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1046ardb/
F: board/freescale/ls1046ardb/ls1046ardb.c
@ -8,6 +9,8 @@ F: configs/ls1046ardb_qspi_defconfig
F: configs/ls1046ardb_qspi_spl_defconfig
F: configs/ls1046ardb_sdcard_defconfig
F: configs/ls1046ardb_emmc_defconfig
F: configs/ls1046ardb_tfa_defconfig
F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
LS1046A_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>

12
board/freescale/ls1046ardb/ddr.c
View File

@ -97,6 +97,17 @@ found:
popts->cpo_sample = 0x61;
}
#ifdef CONFIG_TFABOOT
int fsl_initdram(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = fsl_ddr_sdram_size();
return 0;
}
#else
int fsl_initdram(void)
{
phys_size_t dram_size;
@ -117,3 +128,4 @@ int fsl_initdram(void)
return 0;
}
#endif

27
board/freescale/ls1088a/ls1088a.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*/
#include <common.h>
#include <i2c.h>
@ -67,6 +67,24 @@ int init_func_vid(void)
}
#endif
int is_pb_board(void)
{
u8 board_id;
board_id = QIXIS_READ(id);
if (board_id == LS1088ARDB_PB_BOARD)
return 1;
else
return 0;
}
int fixup_ls1088ardb_pb_banner(void *fdt)
{
fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
return 0;
}
#if !defined(CONFIG_SPL_BUILD)
int checkboard(void)
{
@ -79,7 +97,10 @@ int checkboard(void)
#ifdef CONFIG_TARGET_LS1088AQDS
printf("Board: LS1088A-QDS, ");
#else
printf("Board: LS1088A-RDB, ");
if (is_pb_board())
printf("Board: LS1088ARDB-PB, ");
else
printf("Board: LS1088A-RDB, ");
#endif
sw = QIXIS_READ(arch);
@ -585,6 +606,8 @@ int ft_board_setup(void *blob, bd_t *bd)
if (err)
return err;
#endif
if (is_pb_board())
fixup_ls1088ardb_pb_banner(blob);
return 0;
}