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arm/ls1021a: Add workaround for DDR erratum A008378

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Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
2014-12-08 15:30:55 -08:00
parent 37b608a52d
commit dda3b610ee
3 changed files with 15 additions and 0 deletions
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6
include/fsl_ddr.h
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@ -23,9 +23,15 @@
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
#define ddr_out32(a, v) out_le32(a, v)
#define ddr_setbits32(a, v) setbits_le32(a, v)
#define ddr_clrbits32(a, v) clrbits_le32(a, v)
#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
#else
#define ddr_in32(a) in_be32(a)
#define ddr_out32(a, v) out_be32(a, v)
#define ddr_setbits32(a, v) setbits_be32(a, v)
#define ddr_clrbits32(a, v) clrbits_be32(a, v)
#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
#endif
#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR