York Sun 944537c56e drivers/ddr/fsl: Modify binding registers to save time on data init ...

DDR controllers always use binding register to determine the memory
space to perform data initialization. In case of controller interleaving,
the space is doubled, resulting twice long wait. It wasn't too bad until
the memory capacity increases. To reduce the wait time, reduce the
binding space to half and restore it after data initialization.
Three-way interleaving is no longer used and is removed.

Signed-off-by: York Sun <york.sun@nxp.com>

2018-01-30 09:14:07 -08:00

..

altera

ddr: altera: silence PHY calibration unless in debug mode

2018-01-25 09:59:37 +01:00

fsl

drivers/ddr/fsl: Modify binding registers to save time on data init

2018-01-30 09:14:07 -08:00

marvell

ddr: marvell: update ddr controller init and freq

2018-01-19 16:30:29 +01:00

microchip

wait_bit: use wait_for_bit_le32 and remove wait_for_bit

2018-01-24 12:03:43 +05:30

Kconfig

arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig

2017-04-14 14:06:57 +02:00