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Silicon/Rockchip: DwcSdhciDxe: Fix PHY DLL configuration

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HS400 appears to work reliably now.
This commit is contained in:
Mario Bălănică
2023-07-07 05:01:55 +03:00
parent 825f4f68f0
commit 01d7159814
2 changed files with 26 additions and 7 deletions
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23
edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.c
View File

@@ -100,6 +100,7 @@ EmmcSdMmcNotifyPhase (
SD_MMC_BUS_MODE *Timing;
UINTN MaxClockFreq;
UINT32 Value, i;
UINT32 TxClkTapNum;
DEBUG ((DEBUG_INFO, "%a\n", __FUNCTION__));
@@ -185,12 +186,26 @@ EmmcSdMmcNotifyPhase (
gBS->Stall (1);
}
MmioWrite32(EMMC_DLL_RXCLK, EMMC_DLL_DLYENA |
EMMC_DLL_RXCLK_NO_INVERTER);
TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_DEFAULT;
if (*Timing == SdMmcMmcHs400) {
TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_90_DEGREES;
MmioWrite32 (EMMC_DLL_CMDOUT, EMMC_DLL_CMDOUT_SRC_CLK_NEG |
EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG |
EMMC_DLL_DLYENA |
EMMC_DLL_CMDOUT_TAPNUM_90_DEGREES |
EMMC_DLL_TAPNUM_FROM_SW);
}
MmioWrite32(EMMC_DLL_RXCLK, EMMC_DLL_DLYENA);
MmioWrite32(EMMC_DLL_TXCLK, EMMC_DLL_DLYENA |
EMMC_DLL_TXCLK_TAPNUM_DEFAULT | EMMC_DLL_TXCLK_TAPNUM_FROM_SW);
TxClkTapNum | EMMC_DLL_TAPNUM_FROM_SW |
EMMC_DLL_NO_INVERTER);
MmioWrite32(EMMC_DLL_STRBIN, EMMC_DLL_DLYENA |
EMMC_DLL_STRBIN_TAPNUM_DEFAULT);
EMMC_DLL_STRBIN_TAPNUM_DEFAULT | EMMC_DLL_TAPNUM_FROM_SW);
break;
default:

10
edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.h
View File

@@ -39,18 +39,22 @@
#define EMMC_DLL_CTRL_START_POINT_DEFAULT (5 << 16)
#define EMMC_DLL_CTRL_INCREMENT_DEFAULT (2 << 8)
#define EMMC_DLL_NO_INVERTER BIT29
#define EMMC_DLL_DLYENA BIT27
#define EMMC_DLL_RXCLK_NO_INVERTER BIT29
#define EMMC_DLL_TAPNUM_FROM_SW BIT24
#define EMMC_DLL_TXCLK_TAPNUM_DEFAULT (0x10 << 0)
#define EMMC_DLL_TXCLK_TAPNUM_FROM_SW BIT24
#define EMMC_DLL_TXCLK_TAPNUM_90_DEGREES 0x9
#define EMMC_DLL_STRBIN_TAPNUM_DEFAULT (0x3 << 0)
#define EMMC_DLL_STRBIN_DELAY_NUM_SEL BIT26
#define EMMC_DLL_STRBIN_DELAY_NUM_OFFSET 16
#define EMMC_DLL_STRBIN_DELAY_NUM_DEFAULT 0x10
#define EMMC_DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
#define EMMC_DLL_CMDOUT_SRC_CLK_NEG BIT28
#define EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG BIT29
#define EMMC_DLL_STATUS0_DLL_LOCK BIT8
#define EMMC_DLL_STATUS0_DLL_TIMEOUT BIT9