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Add NanoPi M6 (#164)

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This commit is contained in:
LokiSharp
2024-12-05 17:13:43 +08:00
committed by GitHub
parent 53236151ca
commit 41af90239e
10 changed files with 614 additions and 0 deletions
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1
.github/workflows/build.yml vendored
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@@ -39,6 +39,7 @@ jobs:
- edge2
- nanopi-r6c
- nanopi-r6s
- nanopi-m6
- nanopc-t6
- nanopc-cm3588-nas
- blade3

2
README.md
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@@ -20,6 +20,7 @@ This repository contains an UEFI firmware implementation based on EDK2 for vario
- [FriendlyELEC NanoPC T6](https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6)
- [FriendlyELEC NanoPi R6C](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6C)
- [FriendlyELEC NanoPi R6S](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S)
- [FriendlyELEC NanoPi M6](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_M6)
- [Hinlink H88K](http://www.hinlink.com)
# Supported OSes
@@ -160,6 +161,7 @@ The paths above are relative to the root of the file system. That is, the `dtb`
| `rk3588-nanopc-cm3588-nas` | NanoPC CM3588-NAS |
| `rk3588s-nanopi-r6c` | NanoPi R6C |
| `rk3588s-nanopi-r6s` | NanoPi R6S |
| `rk3588s-nanopi-m6` | NanoPi M6 |
| `rk3588-hinlink-h88k` | H88K |
In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.

3
configs/nanopi-m6.conf Normal file
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@@ -0,0 +1,3 @@
DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.dsc
PLATFORM_NAME=NanoPi-M6
SOC=RK3588

BIN
edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopi-m6.dtb Normal file
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58
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/AcpiTables/AcpiTables.inf Normal file
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@@ -0,0 +1,58 @@
#/** @file
#
# ACPI table data and ASL sources required to boot the platform.
#
# Copyright (c) 2019-2021, ARM Limited. All rights reserved.
# Copyright (c) Microsoft Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = AcpiTables
FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
MODULE_TYPE = USER_DEFINED
VERSION_STRING = 1.0
RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = AARCH64
#
[Sources]
Dsdt.asl
$(RK_COMMON_ACPI_DIR)/Madt.aslc
$(RK_COMMON_ACPI_DIR)/Fadt.aslc
$(RK_COMMON_ACPI_DIR)/Gtdt.aslc
$(RK_COMMON_ACPI_DIR)/Spcr.aslc
$(RK_COMMON_ACPI_DIR)/Mcfg.aslc
$(RK_COMMON_ACPI_DIR)/Dbg2.aslc
$(RK_COMMON_ACPI_DIR)/Pptt.aslc
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Silicon/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gRK3588TokenSpaceGuid.PcdI2S0Supported
gRK3588TokenSpaceGuid.PcdI2S1Supported
gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken

39
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/AcpiTables/Dsdt.asl Normal file
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@@ -0,0 +1,39 @@
/** @file
*
* Differentiated System Definition Table (DSDT)
*
* Copyright (c) 2020, Pete Batard <pete@akeo.ie>
* Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588S", 2)
{
Scope (\_SB_)
{
include ("DsdtCommon.asl")
include ("Cpu.asl")
include ("Pcie.asl")
include ("Sata.asl")
include ("Emmc.asl")
include ("Sdhc.asl")
include ("Dma.asl")
include ("Gmac0.asl")
include ("Gpio.asl")
include ("I2c.asl")
include ("Uart.asl")
//include ("Spi.asl")
include ("Usb2Host.asl")
include ("Usb3Host0.asl")
include ("Usb3Host1.asl")
}
}

342
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/Library/RockchipPlatformLib/RockchipPlatformLib.c Normal file
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@@ -0,0 +1,342 @@
/** @file
*
* Copyright (c) 2021, Rockchip Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/GpioLib.h>
#include <Library/RK806.h>
#include <Library/Rk3588Pcie.h>
#include <Soc.h>
static struct regulator_init_data rk806_init_data[] = {
/* Master PMIC */
RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
//RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
/* No dual PMICs on this platform */
};
VOID
EFIAPI
SdmmcIoMux (
VOID
)
{
/* sdmmc0 iomux (microSD socket) */
BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
}
VOID
EFIAPI
SdhciEmmcIoMux (
VOID
)
{
/* sdhci0 iomux (eMMC socket) */
BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
}
#define NS_CRU_BASE 0xFD7C0000
#define CRU_CLKSEL_CON59 0x03EC
#define CRU_CLKSEL_CON78 0x0438
VOID
EFIAPI
Rk806SpiIomux (
VOID
)
{
/* io mux */
//BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
//BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
}
VOID
EFIAPI
Rk806Configure (
VOID
)
{
UINTN RegCfgIndex;
RK806Init();
for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
}
VOID
EFIAPI
SetCPULittleVoltage (
IN UINT32 Microvolts
)
{
struct regulator_init_data Rk806CpuLittleSupply =
RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
RK806RegulatorInit(Rk806CpuLittleSupply);
}
VOID
EFIAPI
NorFspiIomux (
VOID
)
{
/* io mux */
/* Do not override, set by earlier boot stages. */
}
VOID
EFIAPI
GmacIomux (
IN UINT32 Id
)
{
switch (Id) {
case 1:
/* gmac1 iomux */
BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
/* phy1 reset */
GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
break;
default:
break;
}
}
VOID
EFIAPI
GmacIoPhyReset (
UINT32 Id,
BOOLEAN Enable
)
{
switch (Id) {
case 1:
/* phy1 reset */
GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
break;
default:
break;
}
}
VOID
EFIAPI
NorFspiEnableClock (
UINT32 *CruBase
)
{
UINTN BaseAddr = (UINTN) CruBase;
MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
}
VOID
EFIAPI
I2cIomux (
UINT32 id
)
{
switch (id) {
case 0:
GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
break;
case 1:
break;
case 2:
GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
break;
case 3:
GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
break;
case 4:
break;
case 5:
break;
case 6:
GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
break;
case 7:
break;
default:
break;
}
}
VOID
EFIAPI
UsbPortPowerEnable (
VOID
)
{
DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
/* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */
GpioPinWrite (4, GPIO_PIN_PB5, TRUE);
GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
/* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */
GpioPinWrite (1, GPIO_PIN_PD2, TRUE);
GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT);
// DEBUG((DEBUG_INFO, "Trying to enable on-board LED WAN\n"));
// GpioPinWrite (1, GPIO_PIN_PC2, TRUE);
// GpioPinSetDirection (1, GPIO_PIN_PC2, GPIO_PIN_OUTPUT);
// DEBUG((DEBUG_INFO, "Trying to enable on-board LED LAN\n"));
// GpioPinWrite (1, GPIO_PIN_PC3, TRUE);
// GpioPinSetDirection (1, GPIO_PIN_PC3, GPIO_PIN_OUTPUT);
// DEBUG((DEBUG_INFO, "Trying to enable on-board LED1\n"));
// GpioPinWrite (1, GPIO_PIN_PC4, TRUE);
// GpioPinSetDirection (1, GPIO_PIN_PC4, GPIO_PIN_OUTPUT);
}
VOID
EFIAPI
Usb2PhyResume (
VOID
)
{
MmioWrite32(0xfd5d0008, 0x20000000);
MmioWrite32(0xfd5d4008, 0x20000000);
MmioWrite32(0xfd5d8008, 0x20000000);
MmioWrite32(0xfd5dc008, 0x20000000);
MmioWrite32(0xfd7f0a10, 0x07000700);
MmioWrite32(0xfd7f0a10, 0x07000000);
}
VOID
EFIAPI
PcieIoInit (
UINT32 Segment
)
{
/* Set reset and power IO to gpio output mode */
switch(Segment) {
case PCIE_SEGMENT_PCIE20L1: // RTL8152BG
// GPIO1_A7_u - PCIE20x1_1_PERSTn_M2
GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
break;
case PCIE_SEGMENT_PCIE20L2: // M.2 SSD
// GPIO3_D1_d - PCIE20X1_2_PERSTN_M0
GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
break;
default:
break;
}
}
VOID
EFIAPI
PciePowerEn (
UINT32 Segment,
BOOLEAN Enable
)
{
/* nothing to power on */
}
VOID
EFIAPI
PciePeReset (
UINT32 Segment,
BOOLEAN Enable
)
{
switch(Segment) {
case PCIE_SEGMENT_PCIE20L1:
GpioPinWrite (1, GPIO_PIN_PA7, !Enable);
break;
case PCIE_SEGMENT_PCIE20L2:
GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
break;
default:
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (
VOID
)
{
}
VOID
EFIAPI
PwmFanSetSpeed (
IN UINT32 Percentage
)
{
}
VOID
EFIAPI
PlatformInitLeds (
VOID
)
{
/* Status indicator */
GpioPinWrite (1, GPIO_PIN_PC1, FALSE);
GpioPinSetDirection (1, GPIO_PIN_PC1, GPIO_PIN_OUTPUT);
}
VOID
EFIAPI
PlatformSetStatusLed (
IN BOOLEAN Enable
)
{
GpioPinWrite (1, GPIO_PIN_PC1, Enable);
}
VOID
EFIAPI
PlatformEarlyInit (
VOID
)
{
// Configure various things specific to this platform
}

34
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/Library/RockchipPlatformLib/RockchipPlatformLib.inf Normal file
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#
# Copyright (c) 2021, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RockchipPlatformLib
FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RockchipPlatformLib
RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
CruLib
GpioLib
[Sources.common]
RockchipPlatformLib.c
$(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c

20
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.Modules.fdf.inc Normal file
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@@ -0,0 +1,20 @@
## @file
#
# Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
# Copyright (c) 2023, Sergey Tyuryukanov <s199p.wa1k9r@gmail.com>
# Copyright (c) 2024, LokiSharp <loki.sharp@gmail.com>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
# ACPI Support
INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
# Device Tree Support
FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-nanopi-m6.dtb
}
# Splash screen logo
INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf

115
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.dsc Normal file
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@@ -0,0 +1,115 @@
## @file
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
# Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
# Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
# Copyright (c) 2023, Sergey Tyuryukanov <s199p.wa1k9r@gmail.com>
# Copyright (c) 2024, LokiSharp <loki.sharp@gmail.com>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = NanoPi-M6
PLATFORM_VENDOR = FriendlyElec
PLATFORM_GUID = cf256089-670b-d7c7-1e82-8b2b99637832
PLATFORM_VERSION = 0.2
DSC_SPECIFICATION = 0x00010019
OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR)
PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
SUPPORTED_ARCHITECTURES = AARCH64
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf
RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
#
# HYM8563 RTC support
# I2C location configured by PCDs below.
#
DEFINE RK_RTC8563_ENABLE = TRUE
#
# RK3588S-based platform
#
!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc
################################################################################
#
# Library Class section - list of all Library Classes needed by this Platform.
#
################################################################################
[LibraryClasses.common]
RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
#
################################################################################
[PcdsFixedAtBuild.common]
# SMBIOS platform config
gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPi M6"
gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec"
gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi"
gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPi_M6"
gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-nanopi-m6"
# I2C
gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
#
# CPU Performance default values
#
gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
#
# PCIe/SATA/USB Combo PIPE PHY support flags and default values
#
gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE
gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE
gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE)
#
# USB/DP Combo PHY support flags and default values
#
gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
#
# GMAC
#
gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.
#
################################################################################
[Components.common]
# ACPI Support
$(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
# Splash screen logo
$(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf