EDK2/edk2-rk3588
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Allow platforms to specify all supported display connectors

Browse Source 
Particularly for HDMI and eDP as the other drivers could already bind to
multiple outputs.

The eDP driver is still disabled by default because it requires
EdpEnableBacklight() to be implemented in RockchipPlatformLib, but it
does appear to load fine and has been tested to work some time ago.

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
This commit is contained in:
Mario Bălănică
2025-02-03 00:33:46 +02:00
parent 48d52ef954
commit 5697f4400a
69 changed files with 1056 additions and 309 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
View File

@@ -99,6 +99,14 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -243,6 +243,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER2,
.ChannelID = PWM_CHANNEL3,

20
edk2-rockchip/Platform/BuzzTV/PowerStation6/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -317,6 +317,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

8
edk2-rockchip/Platform/BuzzTV/PowerStation6/PowerStation6.dsc
View File

@@ -95,6 +95,14 @@
gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

9
edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
View File

@@ -108,6 +108,15 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0,
VOP_OUTPUT_IF_DP1
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -411,6 +411,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER3,
.ChannelID = PWM_CHANNEL3,

10
edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
View File

@@ -99,6 +99,16 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0,
VOP_OUTPUT_IF_DP1
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -411,6 +411,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER2,
.ChannelID = PWM_CHANNEL3,

20
edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -312,6 +312,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER2,
.ChannelID = PWM_CHANNEL3,

8
edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
View File

@@ -87,6 +87,14 @@
#
gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -322,6 +322,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER0,
.ChannelID = PWM_CHANNEL1,

9
edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/NanoPC-CM3588-NAS.dsc
View File

@@ -103,6 +103,15 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -316,6 +316,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

9
edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
View File

@@ -99,6 +99,15 @@
#
gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -300,6 +300,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

7
edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/NanoPi-M6.dsc
View File

@@ -94,6 +94,13 @@
gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -300,6 +300,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

7
edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc
View File

@@ -93,6 +93,13 @@
gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -287,6 +287,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

7
edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc
View File

@@ -92,6 +92,13 @@
gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

8
edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
View File

@@ -96,6 +96,14 @@
# SD card detect signal is inverted
gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_DP0,
VOP_OUTPUT_IF_MIPI0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

8
edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -246,6 +246,14 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
}
VOID
EFIAPI
PwmFanIoSetup (

9
edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
View File

@@ -102,6 +102,15 @@
#
gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -345,6 +345,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

8
edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc
View File

@@ -100,6 +100,14 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -285,6 +285,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
STATIC
VOID
KhadasMcuRegistrationEventHandler (

30
edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -302,6 +302,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

10
edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
View File

@@ -104,6 +104,16 @@
gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0,
VOP_OUTPUT_IF_DP1
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -344,6 +344,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
VOID
EFIAPI
PwmFanIoSetup (

9
edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
View File

@@ -106,6 +106,15 @@
#
gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0,
VOP_OUTPUT_IF_DP1
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

9
edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc
View File

@@ -92,6 +92,15 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0,
VOP_OUTPUT_IF_DP1
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -294,6 +294,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER2,
.ChannelID = PWM_CHANNEL0,

20
edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -277,6 +277,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER3,
.ChannelID = PWM_CHANNEL2,

8
edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
View File

@@ -102,6 +102,14 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -319,6 +319,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC4, 5); // hdmim2_tx1_cec
GpioPinSetPull (3, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER0,
.ChannelID = PWM_CHANNEL3,

9
edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc
View File

@@ -102,6 +102,15 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -274,6 +274,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PD4, 3); // hdmim1_tx0_hpd
GpioPinSetPull (3, GPIO_PIN_PD4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER0,
.ChannelID = PWM_CHANNEL3,

8
edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc
View File

@@ -95,6 +95,14 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -309,6 +309,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec
GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER0,
.ChannelID = PWM_CHANNEL1,

9
edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc
View File

@@ -103,6 +103,15 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

30
edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -322,6 +322,36 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda
GpioPinSetPull (4, GPIO_PIN_PC0, GPIO_PIN_PULL_NONE);
break;
case 1:
GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec
GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER0,
.ChannelID = PWM_CHANNEL1,

9
edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc
View File

@@ -107,6 +107,15 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI0,
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.

20
edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -319,6 +319,26 @@ PciePeReset (
}
}
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
)
{
switch (Id) {
case 1:
GpioPinSetFunction (2, GPIO_PIN_PC4, 4); // hdmim0_tx1_cec
GpioPinSetPull (2, GPIO_PIN_PC4, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (1, GPIO_PIN_PA6, 5); // hdmim0_tx1_hpd
GpioPinSetPull (1, GPIO_PIN_PA6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC6, 5); // hdmim1_tx1_scl
GpioPinSetPull (3, GPIO_PIN_PC6, GPIO_PIN_PULL_NONE);
GpioPinSetFunction (3, GPIO_PIN_PC5, 5); // hdmim1_tx1_sda
GpioPinSetPull (3, GPIO_PIN_PC5, GPIO_PIN_PULL_NONE);
break;
}
}
PWM_DATA pwm_data = {
.ControllerID = PWM_CONTROLLER0,
.ChannelID = PWM_CHANNEL1,

12
edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc
View File

@@ -75,11 +75,6 @@
gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
#
# HDMI1 Display
#
gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
#
# PCIe/SATA/USB Combo PIPE PHY support flags and default values
#
@@ -110,6 +105,13 @@
#
gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{CODE({
VOP_OUTPUT_IF_HDMI1,
VOP_OUTPUT_IF_DP0
})}
################################################################################
#

4
edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.c
View File

@@ -1357,7 +1357,7 @@ Vop2IfConfig (
}
}
if (OutputIf & VOP_OUTPUT_IF_eDP0) {
if (OutputIf & VOP_OUTPUT_IF_EDP0) {
Vop2MaskWrite (
Vop2->BaseAddress,
RK3568_DSP_IF_EN,
@@ -1400,7 +1400,7 @@ Vop2IfConfig (
);
}
if (OutputIf & VOP_OUTPUT_IF_eDP1) {
if (OutputIf & VOP_OUTPUT_IF_EDP1) {
Vop2MaskWrite (
Vop2->BaseAddress,
RK3568_DSP_IF_EN,

31
edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.h
View File

@@ -11,6 +11,7 @@
#define __VOP2_H__
#include <Library/Vop2Regs.h>
#include <Library/RockchipDisplayLib.h>
/*
* major: IP major vertion, used for IP structure
@@ -23,36 +24,6 @@
#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
/*
* display output interface supported by rockchip lcdc
*/
#define ROCKCHIP_OUT_MODE_P888 0
#define ROCKCHIP_OUT_MODE_BT1120 0
#define ROCKCHIP_OUT_MODE_P666 1
#define ROCKCHIP_OUT_MODE_P565 2
#define ROCKCHIP_OUT_MODE_BT656 5
#define ROCKCHIP_OUT_MODE_S888 8
#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
#define ROCKCHIP_OUT_MODE_YUV420 14
/* for use special outface */
#define ROCKCHIP_OUT_MODE_AAAA 15
#define VOP_OUTPUT_IF_RGB BIT(0)
#define VOP_OUTPUT_IF_BT1120 BIT(1)
#define VOP_OUTPUT_IF_BT656 BIT(2)
#define VOP_OUTPUT_IF_LVDS0 BIT(3)
#define VOP_OUTPUT_IF_LVDS1 BIT(4)
#define VOP_OUTPUT_IF_MIPI0 BIT(5)
#define VOP_OUTPUT_IF_MIPI1 BIT(6)
#define VOP_OUTPUT_IF_eDP0 BIT(7)
#define VOP_OUTPUT_IF_eDP1 BIT(8)
#define VOP_OUTPUT_IF_DP0 BIT(9)
#define VOP_OUTPUT_IF_DP1 BIT(10)
#define VOP_OUTPUT_IF_HDMI0 BIT(11)
#define VOP_OUTPUT_IF_HDMI1 BIT(12)
#define VOP_OUTPUT_IF_NUMS 13
#define VOP2_LAYER_MAX 8
#define VOP_FEATURE_OUTPUT_10BIT BIT(0)

4
edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc
View File

@@ -118,7 +118,9 @@
# Display Support
#
INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
# INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
!if $(RK_ANALOGIX_DP_ENABLE) == TRUE
INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
!endif
!if $(RK_DW_HDMI_QP_ENABLE) == TRUE
INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
!endif

38
edk2-rockchip/Silicon/Rockchip/Include/Library/AnalogixDpLib.h
View File

@@ -24,9 +24,6 @@
#define EINVAL 22 /* Invalid argument */
#define ETIMEDOUT 110 /* Connection timed out */
#define ANALOGIX_DP0_REG_BASE 0xFDEC0000
#define ANALOGIX_DP1_REG_BASE 0xFDED0000
#define ANALOGIX_DP_TX_SW_RESET 0x14
#define ANALOGIX_DP_FUNC_EN_1 0x18
#define ANALOGIX_DP_FUNC_EN_2 0x1C
@@ -704,18 +701,6 @@ struct LinkTrain {
enum LinkTrainingState LtState;
};
struct AnalogixDpDevice {
UINT32 Id;
BOOLEAN ForceHpd;
struct VideoInfo VideoInfo;
struct LinkTrain LinkTrain;
struct DrmDisplayMode *MODE;
unsigned char EDID[EDID_BLOCK_LENGTH * 2];
UINT8 Dpcd[DP_RECEIVER_CAP_SIZE];
UINT8 Edid[EDID_BLOCK_LENGTH * 2];
UINT32 LaneMap[4];
};
/* Rockchip Htx Phy */
struct RockchipHdptxPhy {
@@ -723,6 +708,29 @@ struct RockchipHdptxPhy {
UINT32 LANE_POLARITY_INVERT[4];
};
struct AnalogixDpDevice {
UINT32 Signature;
ROCKCHIP_CONNECTOR_PROTOCOL Connector;
UINT32 Id;
UINTN Base;
UINT32 OutputInterface;
BOOLEAN ForceHpd;
struct VideoInfo VideoInfo;
struct LinkTrain LinkTrain;
struct DrmDisplayMode *MODE;
unsigned char EDID[EDID_BLOCK_LENGTH * 2];
UINT8 Dpcd[DP_RECEIVER_CAP_SIZE];
UINT8 Edid[EDID_BLOCK_LENGTH * 2];
UINT32 LaneMap[4];
struct RockchipHdptxPhy HdptxPhy;
};
#define ANALOGIX_DP_SIGNATURE SIGNATURE_32 ('A', 'n', 'D', 'P')
#define ANALOGIX_DP_FROM_CONNECTOR_PROTOCOL(a) \
CR (a, struct AnalogixDpDevice, Connector, ANALOGIX_DP_SIGNATURE)
struct PhyConfigureOptsDp {
UINTN LINKRATE;
UINTN LANES;

41
edk2-rockchip/Silicon/Rockchip/Include/Library/DwHdmiQpLib.h
View File

@@ -898,9 +898,6 @@
#define SCDC_MANUFACTURER_SPECIFIC 0xde
#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
#define HDMI0_BASE 0xFDE80000
#define HDMI1_BASE 0xFDEA0000
#define HDMI0TX_PHY_BASE 0xFED60000
#define HDMI1TX_PHY_BASE 0xFED70000
@@ -910,10 +907,15 @@
#define PMU1CRU_SOFTRST_CON03 0xA0C
#define PMU1CRU_SOFTRST_CON04 0xA10
/* Rockchip Htx Phy */
struct RockchipHdptxPhyHdmi {
UINT32 Id;
};
struct DwHdmiQpI2c {
BOOLEAN Cmp;
UINT32 Stat;
UINT32 PinMux;
UINT8 SlaveReg;
BOOLEAN IsSegment;
@@ -921,16 +923,27 @@ struct DwHdmiQpI2c {
};
struct DwHdmiQpDevice {
UINT32 Id;
BOOLEAN ForceHpd;
struct DwHdmiQpI2c I2c;
UINT32 ScdcIntr;
UINT32 FltIntr;
UINT32 EarcIntr;
UINT32 Signature;
ROCKCHIP_CONNECTOR_PROTOCOL Connector;
UINT32 Id;
UINTN Base;
UINT32 OutputInterface;
BOOLEAN ForceHpd;
struct DwHdmiQpI2c I2c;
UINT32 ScdcIntr;
UINT32 FltIntr;
UINT32 EarcIntr;
BOOLEAN FltCmp;
BOOLEAN FltCmp;
struct RockchipHdptxPhyHdmi HdptxPhy;
};
#define DW_HDMI_QP_SIGNATURE SIGNATURE_32 ('D', 'W', 'h', 'D')
#define DW_HDMI_QP_FROM_CONNECTOR_PROTOCOL(a) \
CR (a, struct DwHdmiQpDevice, Connector, DW_HDMI_QP_SIGNATURE)
struct i2c_msg {
UINT16 addr;
UINT16 flags;
@@ -947,12 +960,6 @@ struct i2c_msg {
UINT8 *buf;
};
/* Rockchip Htx Phy */
struct RockchipHdptxPhyHdmi {
UINT32 Id;
};
EFI_STATUS
DwHdmiQpConnectorPreInit (
OUT ROCKCHIP_CONNECTOR_PROTOCOL *This,

19
edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipDisplayLib.h
View File

@@ -6,12 +6,13 @@
**/
#ifndef __ROCKCHIP_DISPLAY_H__
#define __ROCKCHIP_DISPLAY_H__
#ifndef __ROCKCHIP_DISPLAY_LIB_H__
#define __ROCKCHIP_DISPLAY_LIB_H__
#include <Uefi/UefiBaseType.h>
#include <Library/uboot-env.h>
#include <Library/drm_dsc.h>
#include <RockchipDisplay.h>
#define LIST_FOR_EACH_ENTRY(Pos, Head, Member) \
for (Pos = BASE_CR((Head)->ForwardLink, typeof(*Pos), Member); \
@@ -62,20 +63,6 @@ typedef enum {
/* for use special outface */
#define ROCKCHIP_OUT_MODE_AAAA 15
#define VOP_OUTPUT_IF_RGB BIT(0)
#define VOP_OUTPUT_IF_BT1120 BIT(1)
#define VOP_OUTPUT_IF_BT656 BIT(2)
#define VOP_OUTPUT_IF_LVDS0 BIT(3)
#define VOP_OUTPUT_IF_LVDS1 BIT(4)
#define VOP_OUTPUT_IF_MIPI0 BIT(5)
#define VOP_OUTPUT_IF_MIPI1 BIT(6)
#define VOP_OUTPUT_IF_eDP0 BIT(7)
#define VOP_OUTPUT_IF_eDP1 BIT(8)
#define VOP_OUTPUT_IF_DP0 BIT(9)
#define VOP_OUTPUT_IF_DP1 BIT(10)
#define VOP_OUTPUT_IF_HDMI0 BIT(11)
#define VOP_OUTPUT_IF_HDMI1 BIT(12)
typedef struct {
UINT32 Mode;
UINT32 Offset;

19
edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h
View File

@@ -1,7 +1,7 @@
/** @file
*
* Copyright (c) 2021, Rockchip Limited. All rights reserved.
* Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
* Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -26,14 +26,9 @@ SdhciEmmcIoMux (
VOID
EFIAPI
EnableBacklight (
IN BOOLEAN en
);
VOID
EFIAPI
EnablePWM (
IN BOOLEAN en
EdpEnableBacklight (
IN UINT32 Id,
IN BOOLEAN Enable
);
VOID
@@ -117,6 +112,12 @@ PciePeReset (
BOOLEAN Enable
);
VOID
EFIAPI
HdmiTxIomux (
IN UINT32 Id
);
VOID
EFIAPI
PwmFanIoSetup (

27
edk2-rockchip/Silicon/Rockchip/Include/RockchipDisplay.h Normal file
View File

@@ -0,0 +1,27 @@
/** @file
*
* Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __ROCKCHIP_DISPLAY_H__
#define __ROCKCHIP_DISPLAY_H__
#define VOP_OUTPUT_IF_RGB 0x00000001
#define VOP_OUTPUT_IF_BT1120 0x00000002
#define VOP_OUTPUT_IF_BT656 0x00000004
#define VOP_OUTPUT_IF_LVDS0 0x00000008
#define VOP_OUTPUT_IF_LVDS1 0x00000010
#define VOP_OUTPUT_IF_MIPI0 0x00000020
#define VOP_OUTPUT_IF_MIPI1 0x00000040
#define VOP_OUTPUT_IF_EDP0 0x00000080
#define VOP_OUTPUT_IF_EDP1 0x00000100
#define VOP_OUTPUT_IF_DP0 0x00000200
#define VOP_OUTPUT_IF_DP1 0x00000400
#define VOP_OUTPUT_IF_HDMI0 0x00000800
#define VOP_OUTPUT_IF_HDMI1 0x00001000
#define VOP_OUTPUT_IF_NUMS 13
#endif

92
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.c
View File

@@ -14,18 +14,13 @@
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/AnalogixDpLib.h>
#include <Library/PWMLib.h>
#include <Library/DrmModes.h>
#include <Library/RockchipPlatformLib.h>
#include <Library/MediaBusFormat.h>
#include <Library/DrmModes.h>
#include <Library/uboot-env.h>
#include <Protocol/RockchipConnectorProtocol.h>
#include <Uefi/UefiBaseType.h>
#include <Library/uboot-env.h>
#define DP_MAX_LINK_RATE 0x001
#define DP_MAX_LANE_COUNT 0x002
@@ -407,9 +402,9 @@ AnalogixDpSetLinkBandwidth (
UINTN i;
UINT32 Reg;
OUT struct PhyConfigureOptsDp OPTS_DP;
OUT struct RockchipHdptxPhy Hdptx;
OUT struct RockchipHdptxPhy *Hdptx;
Dp->Id = Hdptx.Id = PcdGet32 (PcdEdpId);
Hdptx = &Dp->HdptxPhy;
OPTS_DP.LANES = Dp->LinkTrain.LaneCount;
OPTS_DP.LINKRATE = DrmDpBwCodeToLinkRate (Dp->LinkTrain.LinkRate) / 100;
@@ -418,7 +413,7 @@ AnalogixDpSetLinkBandwidth (
OPTS_DP.SETRATE = TRUE;
OPTS_DP.SETVOLTAGES = FALSE;
RockchipHdptxPhyConfigure (&Hdptx, &OPTS_DP);
RockchipHdptxPhyConfigure (Hdptx, &OPTS_DP);
AnalogixDpRegWrite (Dp, ANALOGIX_DP_LINK_BW_SET, BwType);
Reg = AnalogixDpGetPllLockStatus (Dp);
@@ -441,9 +436,9 @@ AnalogixDpSetLaneCount (
{
UINTN Reg;
OUT struct PhyConfigureOptsDp OPTS_DP;
OUT struct RockchipHdptxPhy Hdptx;
OUT struct RockchipHdptxPhy *Hdptx;
Dp->Id = Hdptx.Id = PcdGet32 (PcdEdpId);
Hdptx = &Dp->HdptxPhy;
Reg = Count;
AnalogixDpRegWrite (Dp, ANALOGIX_DP_LANE_COUNT_SET, Reg);
@@ -454,7 +449,7 @@ AnalogixDpSetLaneCount (
OPTS_DP.SETLANES = TRUE;
OPTS_DP.SETRATE = FALSE;
OPTS_DP.SETVOLTAGES = FALSE;
RockchipHdptxPhyConfigure (&Hdptx, &OPTS_DP);
RockchipHdptxPhyConfigure (Hdptx, &OPTS_DP);
return 0;
}
@@ -660,9 +655,9 @@ AnalogixDpSetLaneLinkTraining (
{
UINT8 Lane;
OUT struct PhyConfigureOptsDp OPTS_DP;
OUT struct RockchipHdptxPhy Hdptx;
OUT struct RockchipHdptxPhy *Hdptx;
Dp->Id = Hdptx.Id = PcdGet32 (PcdEdpId);
Hdptx = &Dp->HdptxPhy;
for (Lane = 0; Lane < Dp->LinkTrain.LaneCount; Lane++) {
UINT8 TrainingLane = Dp->LinkTrain.TrainingLane[Lane];
@@ -687,7 +682,7 @@ AnalogixDpSetLaneLinkTraining (
OPTS_DP.SETLANES = FALSE;
OPTS_DP.SETRATE = FALSE;
OPTS_DP.SETVOLTAGES = TRUE;
RockchipHdptxPhyConfigure (&Hdptx, &OPTS_DP);
RockchipHdptxPhyConfigure (Hdptx, &OPTS_DP);
}
STATIC
@@ -1229,31 +1224,24 @@ AnalogixDpConnectorPreInit (
)
{
CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState;
struct RockchipHdptxPhy Hdptx;
struct RockchipHdptxPhy *Hdptx;
struct AnalogixDpDevice *Dp;
Dp = AllocateZeroPool (sizeof (*Dp));
Dp = ANALOGIX_DP_FROM_CONNECTOR_PROTOCOL (This);
Hdptx = &Dp->HdptxPhy;
ConnectorState->Type = DRM_MODE_CONNECTOR_eDP;
ConnectorState->OutputInterface = VOP_OUTPUT_IF_eDP1;
Dp->Id = Hdptx.Id = PcdGet32 (PcdEdpId);
ConnectorState->OutputInterface = Dp->OutputInterface;
if (Dp->Id) {
ConnectorState->OutputInterface = VOP_OUTPUT_IF_eDP1;
} else {
ConnectorState->OutputInterface = VOP_OUTPUT_IF_eDP0;
}
if (ConnectorState->OutputInterface == VOP_OUTPUT_IF_eDP0) {
if (ConnectorState->OutputInterface == VOP_OUTPUT_IF_EDP0) {
MmioWrite32 (0xFD5A8000, 0xFFFF0001);
} else {
MmioWrite32 (0xFD5A8004, 0xFFFF0001);
}
RockchipHdptxPhyInit (&Hdptx);
RockchipHdptxPhyInit (Hdptx);
MicroSecondDelay (10);
EnableBacklight (TRUE);
EnablePWM (TRUE);
EdpEnableBacklight (Dp->Id, TRUE);
AnalogixDpReset (Dp);
AnalogixDpSwreset (Dp);
AnalogixDpInitAnalogParam (Dp);
@@ -1331,7 +1319,7 @@ AnalogixDpConnectorEnable (
CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState;
struct AnalogixDpDevice *Dp;
Dp = AllocatePool (sizeof (*Dp));
Dp = ANALOGIX_DP_FROM_CONNECTOR_PROTOCOL (This);
struct VideoInfo *Video = &Dp->VideoInfo;
UINTN Ret;
@@ -1356,7 +1344,6 @@ AnalogixDpConnectorEnable (
Dp->VideoInfo.MaxLinkRate = DP_LINK_BW_5_4;
Dp->VideoInfo.MaxLaneCount = LANE_COUNT4;
Dp->LinkTrain.SSC = TRUE;
Dp->Id = PcdGet32 (PcdEdpId);
Ret = AnalogixDpReadBytesFromDpcd (
Dp,
@@ -1421,7 +1408,7 @@ AnalogixDpConnectorDetect (
return 0;
}
ROCKCHIP_CONNECTOR_PROTOCOL mDp = {
ROCKCHIP_CONNECTOR_PROTOCOL mDpConnectorOps = {
NULL,
AnalogixDpConnectorPreInit,
AnalogixDpConnectorInit,
@@ -1435,6 +1422,19 @@ ROCKCHIP_CONNECTOR_PROTOCOL mDp = {
NULL
};
STATIC struct AnalogixDpDevice mRk3588AnalogixDpDevices[] = {
{
.Id = 0,
.Base = 0xFDEC0000,
.OutputInterface = VOP_OUTPUT_IF_EDP0,
},
{
.Id = 1,
.Base = 0xFDED0000,
.OutputInterface = VOP_OUTPUT_IF_EDP1,
},
};
EFI_STATUS
EFIAPI
AnalogixDpInitDp (
@@ -1443,17 +1443,29 @@ AnalogixDpInitDp (
)
{
EFI_STATUS Status;
UINT32 Index;
EFI_HANDLE Handle;
Handle = NULL;
for (Index = 0; Index < ARRAY_SIZE (mRk3588AnalogixDpDevices); Index++) {
struct AnalogixDpDevice *Dp = &mRk3588AnalogixDpDevices[Index];
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gRockchipConnectorProtocolGuid,
&mDp,
NULL
);
ASSERT_EFI_ERROR (Status);
if (!(PcdGet32 (PcdDisplayConnectorsMask) & Dp->OutputInterface)) {
continue;
}
Dp->Signature = ANALOGIX_DP_SIGNATURE;
Dp->HdptxPhy.Id = Dp->Id;
CopyMem (&Dp->Connector, &mDpConnectorOps, sizeof (ROCKCHIP_CONNECTOR_PROTOCOL));
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gRockchipConnectorProtocolGuid,
&Dp->Connector,
NULL
);
ASSERT_EFI_ERROR (Status);
}
return EFI_SUCCESS;
}

11
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
View File

@@ -35,7 +35,6 @@
BaseMemoryLib
RockchipDisplayLib
MemoryAllocationLib
PWMLib
RockchipPlatformLib
UefiLib
UefiDriverEntryPoint
@@ -47,17 +46,11 @@
Silicon/Rockchip/RockchipPkg.dec
Silicon/Rockchip/RK3588/RK3588.dec
[BuildOptions]
[Pcd]
gRockchipTokenSpaceGuid.PcdLcdPixelFormat
gRockchipTokenSpaceGuid.PcdEdpId
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask
[Protocols]
gRockchipConnectorProtocolGuid
[Depex]
TRUE
gRockchipPlatformConfigAppliedProtocolGuid

28
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpReg.c
View File

@@ -28,15 +28,7 @@ AnalogixDpRegWrite (
IN UINT32 Value
)
{
UINT32 BASE;
if (!Dp->Id) {
BASE = ANALOGIX_DP0_REG_BASE;
} else {
BASE = ANALOGIX_DP1_REG_BASE;
}
MmioWrite32 (BASE + Offset, Value);
MmioWrite32 (Dp->Base + Offset, Value);
}
UINT32
@@ -45,17 +37,7 @@ AnalogixDpRegRead (
IN UINT32 Offset
)
{
UINT32 Reg;
UINT32 BASE;
if (!Dp->Id) {
BASE = ANALOGIX_DP0_REG_BASE;
} else {
BASE = ANALOGIX_DP1_REG_BASE;
}
Reg = MmioRead32 (BASE + Offset);
return Reg;
return MmioRead32 (Dp->Base + Offset);
}
VOID
@@ -1326,11 +1308,7 @@ DumpDpRegisters (
UINT32 Ret;
UINT32 Shift;
if (!Dp->Id) {
Shift = ANALOGIX_DP0_REG_BASE;
} else {
Shift = ANALOGIX_DP1_REG_BASE;
}
Shift = Dp->Base;
DEBUG ((DEBUG_WARN, "\n%.8x ", Shift));
for (i = 0; i < 800; i++) {

7
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.c
View File

@@ -232,6 +232,7 @@ struct dw_dp_sdp {
struct dw_dp {
UINT32 Signature;
ROCKCHIP_CONNECTOR_PROTOCOL connector;
UINT32 output_if;
UINTN regmap;
DP_PHY_PROTOCOL *phy;
struct reset_ctl reset;
@@ -1408,7 +1409,7 @@ static int dw_dp_connector_init(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE
struct dw_dp *dp = DW_DP_FROM_CONNECTOR_PROTOCOL (conn);
int ret = 0;
conn_state->OutputInterface |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0;
conn_state->OutputInterface |= dp->output_if;
conn_state->OutputMode = ROCKCHIP_OUT_MODE_AAAA;
conn_state->ColorSpace = V4L2_COLORSPACE_DEFAULT;
@@ -1623,11 +1624,13 @@ static struct dw_dp mRk3588Dp[] = {
.regmap = 0xfde50000,
.reset = { 0xAE0, 8 },
.id = 0,
.output_if = VOP_OUTPUT_IF_DP0,
},
{
.regmap = 0xfde60000,
.reset = { 0xAE0, 9 },
.id = 1,
.output_if = VOP_OUTPUT_IF_DP1,
},
};
@@ -1667,7 +1670,7 @@ DpPhyRegistrationEventHandler (
for (Index = 0; Index < ARRAY_SIZE (mRk3588Dp); Index++) {
DwDp = &mRk3588Dp[Index];
if (DwDp->id == DpPhy->Id) {
if (DwDp->id == DpPhy->Id && (PcdGet32 (PcdDisplayConnectorsMask) & DwDp->output_if)) {
DwDp->Signature = DW_DP_SIGNATURE;
DwDp->phy = DpPhy;
DwDp->force_output = TRUE;

3
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf
View File

@@ -41,6 +41,7 @@
[BuildOptions]
[Pcd]
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask
[Protocols]
gRockchipConnectorProtocolGuid ## PRODUCES
@@ -50,4 +51,4 @@
GCC:*_*_AARCH64_CC_FLAGS = -Wno-error=unused-function -Wno-error=unused-variable
[Depex]
TRUE
gRockchipPlatformConfigAppliedProtocolGuid

167
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.c
View File

@@ -14,19 +14,13 @@
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DwHdmiQpLib.h>
#include <Library/PWMLib.h>
#include <Library/DrmModes.h>
#include <Library/RockchipPlatformLib.h>
#include <Library/MediaBusFormat.h>
#include <Library/DrmModes.h>
#include <Library/GpioLib.h>
#include <Library/uboot-env.h>
#include <Protocol/RockchipConnectorProtocol.h>
#include <Uefi/UefiBaseType.h>
#include <Library/uboot-env.h>
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
#define RK3588_GRF_SOC_CON2 0x0308
@@ -100,15 +94,7 @@ DwHdmiQpRegWrite (
IN UINT32 Offset
)
{
UINT32 BASE;
if (!Hdmi->Id) {
BASE = HDMI0_BASE;
} else {
BASE = HDMI1_BASE;
}
MmioWrite32 (BASE + Offset, Value);
MmioWrite32 (Hdmi->Base + Offset, Value);
}
UINT32
@@ -117,17 +103,7 @@ DwHdmiQpRegRead (
IN UINT32 Offset
)
{
UINT32 Value;
UINT32 BASE;
if (!Hdmi->Id) {
BASE = HDMI0_BASE;
} else {
BASE = HDMI1_BASE;
}
Value = MmioRead32 (BASE + Offset);
return Value;
return MmioRead32 (Hdmi->Base + Offset);
}
VOID
@@ -139,19 +115,12 @@ DwHdmiQpRegMod (
)
{
UINT32 Val;
UINT32 BASE;
if (!Hdmi->Id) {
BASE = HDMI0_BASE;
} else {
BASE = HDMI1_BASE;
}
Val = MmioRead32 (BASE + Offset);
Val = MmioRead32 (Hdmi->Base + Offset);
Val &= ~Mask;
Val |= Value;
MmioWrite32 (BASE + Offset, Val);
MmioWrite32 (Hdmi->Base + Offset, Val);
}
VOID
@@ -539,14 +508,6 @@ DwHdmiI2cInit (
OUT struct DwHdmiQpDevice *Hdmi
)
{
UINT32 BaseAddr;
if (Hdmi->Id) {
BaseAddr = HDMI1_BASE;
} else {
BaseAddr = HDMI0_BASE;
}
/* Software reset */
DwHdmiQpRegWrite (Hdmi, 0x01, I2CM_CONTROL0);
@@ -595,48 +556,6 @@ DumpEdid (
}
}
VOID
DwHdmiQpI2cSetIomux (
OUT struct DwHdmiQpDevice *Hdmi
)
{
if (!Hdmi->Id) {
switch (Hdmi->I2c.PinMux) {
case 0:
GpioPinSetFunction (4, GPIO_PIN_PB7, 0x5);
GpioPinSetFunction (4, GPIO_PIN_PC0, 0x5);
break;
case 1:
GpioPinSetFunction (0, GPIO_PIN_PD5, 0xb);
GpioPinSetFunction (0, GPIO_PIN_PD4, 0xb);
break;
case 2:
GpioPinSetFunction (3, GPIO_PIN_PC7, 0x5);
GpioPinSetFunction (3, GPIO_PIN_PD0, 0x5);
break;
default:
break;
}
} else {
switch (Hdmi->I2c.PinMux) {
case 0:
GpioPinSetFunction (2, GPIO_PIN_PB4, 0x4);
GpioPinSetFunction (2, GPIO_PIN_PB5, 0x4);
break;
case 1:
GpioPinSetFunction (3, GPIO_PIN_PC5, 0x5);
GpioPinSetFunction (3, GPIO_PIN_PC6, 0x5);
break;
case 2:
GpioPinSetFunction (1, GPIO_PIN_PA3, 0x5);
GpioPinSetFunction (1, GPIO_PIN_PA4, 0x5);
break;
default:
break;
}
}
}
EFI_STATUS
DwHdmiQpConnectorPreInit (
OUT ROCKCHIP_CONNECTOR_PROTOCOL *This,
@@ -644,27 +563,22 @@ DwHdmiQpConnectorPreInit (
)
{
CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState;
struct RockchipHdptxPhyHdmi Hdptx;
struct RockchipHdptxPhyHdmi *Hdptx;
struct DwHdmiQpDevice *Hdmi;
Hdmi = AllocateZeroPool (sizeof (*Hdmi));
Hdmi = DW_HDMI_QP_FROM_CONNECTOR_PROTOCOL (This);
Hdptx = &Hdmi->HdptxPhy;
DEBUG ((DEBUG_INIT, "DwHdmiQpConnectorPreInit"));
ConnectorState->Type = DRM_MODE_CONNECTOR_HDMIA;
Hdmi->Id = Hdptx.Id = PcdGet32 (PcdHdmiId);
Hdmi->I2c.PinMux = PcdGet32 (PcdHdmiDDCI2CPinMux);
ConnectorState->Type = DRM_MODE_CONNECTOR_HDMIA;
ConnectorState->OutputInterface = Hdmi->OutputInterface;
if (Hdmi->Id) {
ConnectorState->OutputInterface = VOP_OUTPUT_IF_HDMI1;
} else {
ConnectorState->OutputInterface = VOP_OUTPUT_IF_HDMI0;
}
HdmiTxIomux (Hdmi->Id);
DwHdmiQpSetIomux (Hdmi);
DwHdmiQpI2cSetIomux (Hdmi);
DwHdmiI2cInit (Hdmi);
HdptxRopllCmnConfig (&Hdptx);
HdptxRopllCmnConfig (Hdptx);
DEBUG ((DEBUG_INFO, "%a hdmi pre init success\n", __func__));
return 0;
}
@@ -756,15 +670,15 @@ DwHdmiQpSetup (
OUT DISPLAY_STATE *DisplayState
)
{
struct RockchipHdptxPhyHdmi Hdptx;
struct RockchipHdptxPhyHdmi *Hdptx;
CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState;
UINT32 Val = 0;
ConnectorState->Type = DRM_MODE_CONNECTOR_HDMIA;
Hdptx.Id = PcdGet32 (PcdHdmiId);
Hdptx = &Hdmi->HdptxPhy;
Val = DwHdmiQpRegRead (Hdmi, 0xb0);
DEBUG ((DEBUG_INIT, "%a Hdptx.Id :%d\n", __func__, Hdptx.Id));
DEBUG ((DEBUG_INIT, "%a Hdptx->Id :%d\n", __func__, Hdptx->Id));
DEBUG ((DEBUG_INIT, "%a 0xb0:%d\n", __func__, Val));
Rk3588SetColorFormat (Hdmi, MEDIA_BUS_FMT_RGB888_1X24, 8);
HdmiConfigAvi (Hdmi);
@@ -777,7 +691,7 @@ DwHdmiQpSetup (
DumpEdid (Hdmi);
// enable phy output
HdptxRopllTmdsModeConfig (&Hdptx);
HdptxRopllTmdsModeConfig (Hdptx);
MicroSecondDelay (50);
DwHdmiQpRegWrite (Hdmi, 2, PKTSCHED_PKT_CONTROL0);
DwHdmiQpRegMod (Hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN);
@@ -791,9 +705,8 @@ DwHdmiQpConnectorEnable (
{
struct DwHdmiQpDevice *Hdmi;
Hdmi = AllocatePool (sizeof (*Hdmi));
Hdmi = DW_HDMI_QP_FROM_CONNECTOR_PROTOCOL (This);
DEBUG ((DEBUG_INIT, "DwHdmiQpConnectorEnable\n"));
Hdmi->Id = PcdGet32 (PcdHdmiId);
DwHdmiQpSetup (Hdmi, DisplayState);
@@ -820,7 +733,7 @@ DwHdmiQpConnectorDetect (
return 0;
}
ROCKCHIP_CONNECTOR_PROTOCOL mHdmi = {
ROCKCHIP_CONNECTOR_PROTOCOL mHdmiConnectorOps = {
NULL,
DwHdmiQpConnectorPreInit,
DwHdmiQpConnectorInit,
@@ -834,6 +747,19 @@ ROCKCHIP_CONNECTOR_PROTOCOL mHdmi = {
NULL
};
STATIC struct DwHdmiQpDevice mRk3588DwHdmiQpDevices[] = {
{
.Id = 0,
.Base = 0xFDE80000,
.OutputInterface = VOP_OUTPUT_IF_HDMI0,
},
{
.Id = 1,
.Base = 0xFDEA0000,
.OutputInterface = VOP_OUTPUT_IF_HDMI1,
},
};
EFI_STATUS
EFIAPI
DwHdmiQpInitHdmi (
@@ -842,18 +768,29 @@ DwHdmiQpInitHdmi (
)
{
EFI_STATUS Status;
UINT32 Index;
EFI_HANDLE Handle;
DEBUG ((DEBUG_INIT, "hdmi init start\n"));
Handle = NULL;
for (Index = 0; Index < ARRAY_SIZE (mRk3588DwHdmiQpDevices); Index++) {
struct DwHdmiQpDevice *Hdmi = &mRk3588DwHdmiQpDevices[Index];
if (!(PcdGet32 (PcdDisplayConnectorsMask) & Hdmi->OutputInterface)) {
continue;
}
Hdmi->Signature = DW_HDMI_QP_SIGNATURE;
Hdmi->HdptxPhy.Id = Hdmi->Id;
CopyMem (&Hdmi->Connector, &mHdmiConnectorOps, sizeof (ROCKCHIP_CONNECTOR_PROTOCOL));
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gRockchipConnectorProtocolGuid,
&Hdmi->Connector,
NULL
);
ASSERT_EFI_ERROR (Status);
}
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gRockchipConnectorProtocolGuid,
&mHdmi,
NULL
);
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INIT, "hdmi init success\n"));
return EFI_SUCCESS;
}

11
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
View File

@@ -46,18 +46,11 @@
Silicon/Rockchip/RockchipPkg.dec
Silicon/Rockchip/RK3588/RK3588.dec
[BuildOptions]
[Pcd]
gRockchipTokenSpaceGuid.PcdLcdPixelFormat
gRockchipTokenSpaceGuid.PcdHdmiId
gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask
[Protocols]
gRockchipConnectorProtocolGuid
[Depex]
TRUE
gRockchipPlatformConfigAppliedProtocolGuid

8
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.c
View File

@@ -288,6 +288,7 @@ struct mipi_dphy_configure {
struct dw_mipi_dsi2 {
UINT32 Signature;
ROCKCHIP_CONNECTOR_PROTOCOL connector;
UINT32 output_if;
UINTN base;
UINTN grf;
int id;
@@ -984,8 +985,7 @@ static int dw_mipi_dsi2_connector_init(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLA
conn_state->OutputMode = ROCKCHIP_OUT_MODE_P888;
conn_state->ColorSpace = V4L2_COLORSPACE_DEFAULT;
conn_state->OutputInterface |=
dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
conn_state->OutputInterface |= dsi2->output_if;
if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) {
conn_state->OutputFlags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE;
@@ -1538,12 +1538,14 @@ struct dw_mipi_dsi2 mRk3588MipiDsi[] = {
.base = 0xfde20000,
.grf = RK3588_VOP_GRF_BASE,
.id = 0,
.output_if = VOP_OUTPUT_IF_MIPI0,
.pdata = &rk3588_mipi_dsi2_plat_data,
},
{
.base = 0xfde30000,
.grf = RK3588_VOP_GRF_BASE,
.id = 1,
.output_if = VOP_OUTPUT_IF_MIPI1,
.pdata = &rk3588_mipi_dsi2_plat_data,
},
};
@@ -1584,7 +1586,7 @@ DsiPanelRegistrationEventHandler (
for (Index = 0; Index < ARRAY_SIZE (mRk3588MipiDsi); Index++) {
dsi2 = &mRk3588MipiDsi[Index];
if (dsi2->id == DsiPanel->DsiId) {
if (dsi2->id == DsiPanel->DsiId && (PcdGet32 (PcdDisplayConnectorsMask) & dsi2->output_if)) {
dsi2->Signature = DW_MIPI_DSI2_SIGNATURE;
dsi2->dcphy.phy = rockchip_phy_by_id(dsi2->id);
dsi2->RockchipDsiPanel = DsiPanel;

3
edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf
View File

@@ -42,6 +42,7 @@
Silicon/Rockchip/RK3588/RK3588.dec
[Pcd]
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask
[Protocols]
gRockchipConnectorProtocolGuid ## PRODUCES
@@ -51,4 +52,4 @@
GCC:*_*_AARCH64_CC_FLAGS = -Wno-error=unused-function -Wno-error=unused-variable
[Depex]
TRUE
gRockchipPlatformConfigAppliedProtocolGuid

81
edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/Display.c Normal file
View File

@@ -0,0 +1,81 @@
/** @file
*
* Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include "Display.h"
STATIC
EFI_STATUS
InitializeDisplayVariables (
VOID
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 *Connectors;
UINTN ConnectorsCount;
UINT32 ConnectorsMask;
Connectors = PcdGetPtr (PcdDisplayConnectors);
ConnectorsCount = PcdGetSize (PcdDisplayConnectors) / sizeof (*Connectors);
ASSERT (ConnectorsCount <= VOP_OUTPUT_IF_NUMS);
ConnectorsMask = 0;
for (Index = 0; Index < ConnectorsCount; Index++ ) {
ConnectorsMask |= Connectors[Index];
}
if ((ConnectorsMask & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_EDP0)) ==
(VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_EDP0))
{
DEBUG ((DEBUG_ERROR, "%a: Cannot support both HDMI0 and EDP0 simultaneously!\n", __func__));
ASSERT (FALSE);
ConnectorsMask &= ~(VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_EDP0);
}
if ((ConnectorsMask & (VOP_OUTPUT_IF_HDMI1 | VOP_OUTPUT_IF_EDP1)) ==
(VOP_OUTPUT_IF_HDMI1 | VOP_OUTPUT_IF_EDP1))
{
DEBUG ((DEBUG_ERROR, "%a: Cannot support both HDMI1 and EDP1 simultaneously!\n", __func__));
ASSERT (FALSE);
ConnectorsMask &= ~(VOP_OUTPUT_IF_HDMI1 | VOP_OUTPUT_IF_EDP1);
}
Status = PcdSet32S (PcdDisplayConnectorsMask, ConnectorsMask);
ASSERT_EFI_ERROR (Status);
if (ConnectorsMask == 0) {
return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
}
VOID
EFIAPI
ApplyDisplayVariables (
VOID
)
{
}
VOID
EFIAPI
SetupDisplayVariables (
VOID
)
{
EFI_STATUS Status;
Status = InitializeDisplayVariables ();
if (EFI_ERROR (Status)) {
return;
}
}

32
edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/Display.h Normal file
View File

@@ -0,0 +1,32 @@
/** @file
*
* Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __RK3588DXE_DISPLAY_H__
#define __RK3588DXE_DISPLAY_H__
#include <RockchipDisplay.h>
//
// Don't declare these in the VFR file.
//
#ifndef VFR_FILE_INCLUDE
VOID
EFIAPI
ApplyDisplayVariables (
VOID
);
VOID
EFIAPI
SetupDisplayVariables (
VOID
);
#endif // VFR_FILE_INCLUDE
#endif // __RK3588DXE_DISPLAY_H__

3
edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c
View File

@@ -39,6 +39,7 @@
#include "FanControl.h"
#include "UsbDpPhy.h"
#include "DebugSerialPort.h"
#include "Display.h"
extern UINT8 RK3588DxeHiiBin[];
extern UINT8 RK3588DxeStrings[];
@@ -197,6 +198,7 @@ SetupVariables (
SetupCoolingFanVariables ();
SetupUsbDpPhyVariables ();
SetupDebugSerialPortVariables ();
SetupDisplayVariables ();
return EFI_SUCCESS;
}
@@ -244,6 +246,7 @@ ApplyVariables (
ApplyCoolingFanVariables ();
ApplyUsbDpPhyVariables ();
ApplyDebugSerialPortVariables ();
ApplyDisplayVariables ();
InstallConfigAppliedProtocol ();

4
edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf
View File

@@ -25,6 +25,7 @@
FanControl.c
UsbDpPhy.c
DebugSerialPort.c
Display.c
[Packages]
ArmPkg/ArmPkg.dec
@@ -119,6 +120,9 @@
gRK3588TokenSpaceGuid.PcdI2S0Supported
gRK3588TokenSpaceGuid.PcdI2S1Supported
gRK3588TokenSpaceGuid.PcdDisplayConnectors
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask
[Guids]
gRK3588DxeFormSetGuid

9
edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec
View File

@@ -69,6 +69,13 @@
gRK3588TokenSpaceGuid.PcdI2S0Supported|FALSE|BOOLEAN|0x00010701
gRK3588TokenSpaceGuid.PcdI2S1Supported|FALSE|BOOLEAN|0x00010702
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{ 0x0 }|UINT32[]|0x00010801 {
<Packages>
Silicon/Rockchip/RockchipPkg.dec
<HeaderFiles>
RockchipDisplay.h
}
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|0|UINT32|0x00000001
gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|0|UINT32|0x00000002
@@ -102,5 +109,7 @@
gRK3588TokenSpaceGuid.PcdUsbDpPhy0Usb3State|0|UINT32|0x00000501
gRK3588TokenSpaceGuid.PcdUsbDpPhy1Usb3State|0|UINT32|0x00000502
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask|0|UINT32|0x00000801
[PcdsDynamicEx]
gRK3588TokenSpaceGuid.PcdPcieEcamCompliantSegmentsMask|0|UINT32|0x20000001

18
edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc
View File

@@ -89,6 +89,9 @@
!ifndef RK_AHCI_ENABLE
DEFINE RK_AHCI_ENABLE = TRUE
!endif
!ifndef RK_ANALOGIX_DP_ENABLE
DEFINE RK_ANALOGIX_DP_ENABLE = FALSE
!endif
!ifndef RK_DW_HDMI_QP_ENABLE
DEFINE RK_DW_HDMI_QP_ENABLE = TRUE
!endif
@@ -245,11 +248,6 @@
# Display
#
gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
#gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
#gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux|0x00000000 #hdmitx_i2c_m0
#
# CPU Performance default values
@@ -290,6 +288,11 @@
gRK3588TokenSpaceGuid.PcdFdtForceGopDefault|FALSE
gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault|FALSE
#
# Display support flags and default values
#
gRK3588TokenSpaceGuid.PcdDisplayConnectors|{ 0x0 }
[PcdsPatchableInModule]
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
@@ -355,6 +358,11 @@
gRK3588TokenSpaceGuid.PcdUsbDpPhy0Usb3State|L"UsbDpPhy0Usb3State"|gRK3588DxeFormSetGuid|0x0|$(USBDP_PHY_USB3_STATE_ENABLED)
gRK3588TokenSpaceGuid.PcdUsbDpPhy1Usb3State|L"UsbDpPhy1Usb3State"|gRK3588DxeFormSetGuid|0x0|$(USBDP_PHY_USB3_STATE_ENABLED)
#
# Display
#
gRK3588TokenSpaceGuid.PcdDisplayConnectorsMask|L"DisplayConnectorsMask"|gRK3588DxeFormSetGuid|0x0|0|BS
################################################################################
#
# Components Section - list of all common EDK II Modules needed by RK3588 platforms.

4
edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc
View File

@@ -628,7 +628,9 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
# Display Support
#
Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
# Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
!if $(RK_ANALOGIX_DP_ENABLE) == TRUE
Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
!endif
!if $(RK_DW_HDMI_QP_ENABLE) == TRUE
Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
!endif

3
edk2-rockchip/Silicon/Rockchip/RockchipPkg.dec
View File

@@ -91,9 +91,6 @@
gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash|FALSE|BOOLEAN|0x21200009
gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0|UINT32|0x32000001
gRockchipTokenSpaceGuid.PcdEdpId|0|UINT32|0x32000003
gRockchipTokenSpaceGuid.PcdHdmiId|0|UINT32|0x32000004
gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux|0|UINT32|0x32000005
gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase|0x0010f000|UINT64|0x00001000
gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize|0x100|UINT32|0x00001001