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Clean-up some of the unused code

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Rockchip EVB platforms and RK356x silicon bits have also been deleted.

1) EVB platform was outdated, unbuildable and I don't have the hardware to test. Feel free to add it back if you do :-)

2) RK356x support was almost non-existent outside of some basic HAL SDK ported code.
There's no interest to support it in this repo either - unless, of course, it's done properly with code reusability in mind (but then might as well aim for upstream).
This commit is contained in:
Mario Bălănică
2023-07-26 02:49:26 +03:00
parent 8358d31f3a
commit 98aec4c33c
146 changed files with 4 additions and 30419 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.github/workflows/build.yml vendored
View File

@@ -37,7 +37,6 @@ jobs:
- nanopc-t6
- blade3
- h88k
# - rk3588-evb is currently failing
CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }}
steps:
- name: Checkout

3
configs/rk3588-evb.conf
View File

@@ -1,3 +0,0 @@
DSC_FILE=edk2-rockchip/Platform/Rockchip/RK3588/RK3588.dsc
PLATFORM_NAME=RK3588
SOC=RK3588

12
edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf
View File

@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf
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@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

12
edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf
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@@ -47,7 +47,6 @@
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
@@ -57,15 +56,4 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase

1
edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -17,7 +17,6 @@
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec

BIN
edk2-rockchip/Platform/Rockchip/DeviceTree/rk3588.dtb
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Binary file not shown.

20
edk2-rockchip/Platform/Rockchip/RK3568/Include/ArmPlatform.h
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@@ -1,20 +0,0 @@
/** @file
*
* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __PLATFORM_H__
#define __PLATFORM_H__
//
// We don't care about this value, but the PL031 driver depends on the macro
// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()
// function, which just returns EFI_UNSUPPORTED.
//
//
#define SYS_CFG_RTC 0
#endif /* __PLATFORM_H__ */

111
edk2-rockchip/Platform/Rockchip/RK3568/Library/RK3568Lib/RK3568.c
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@@ -1,111 +0,0 @@
/** @file
*
* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Soc.h>
ARM_CORE_INFO mRK3568InfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 1
0x0, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 2
0x0, 0x2,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 3
0x0, 0x3,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
};
/**
Return the current Boot Mode
This function returns the boot reason on the platform
@return Return the current Boot Mode of the platform
**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
)
{
return BOOT_WITH_FULL_CONFIGURATION;
}
/**
Initialize controllers that must setup in the normal world
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
in the PEI phase.
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
return RETURN_SUCCESS;
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
// Only support one cluster
*CoreCount = sizeof(mRK3568InfoTable) / sizeof(ARM_CORE_INFO);
*ArmCoreTable = mRK3568InfoTable;
return EFI_SUCCESS;
}
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&mArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
}
};
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = sizeof(gPlatformPpiTable);
*PpiList = gPlatformPpiTable;
}

43
edk2-rockchip/Platform/Rockchip/RK3568/Library/RK3568Lib/RK3568Helper.S
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@@ -1,43 +0,0 @@
#
# Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#include <AsmMacroIoLibV8.h>
#include <Library/ArmLib.h>
ASM_FUNC(ArmPlatformPeiBootAction)
ret
//UINTN
//ArmPlatformGetCorePosition (
// IN UINTN MpId
// );
// With this function: CorePos = (ClusterId * 4) + CoreId
ASM_FUNC(ArmPlatformGetCorePosition)
and x1, x0, #ARM_CORE_MASK
and x0, x0, #ARM_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
//UINTN
//ArmPlatformGetPrimaryCoreMpId (
// VOID
// );
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
ret
//UINTN
//ArmPlatformIsPrimaryCore (
// IN UINTN MpId
// );
ASM_FUNC(ArmPlatformIsPrimaryCore)
MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
and x0, x0, x1
MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
cmp w0, w1
cset x0, eq
ret

42
edk2-rockchip/Platform/Rockchip/RK3568/Library/RK3568Lib/RK3568Lib.inf
View File

@@ -1,42 +0,0 @@
#
# Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RK3568Lib
FILE_GUID = 0453643a-3177-11ec-95b4-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3568/RK3568.dec
Silicon/Rockchip/RK3568/RK3568.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
[Sources.common]
RK3568.c
RK3568Mem.c
[Sources.AARCH64]
RK3568Helper.S
[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize

194
edk2-rockchip/Platform/Rockchip/RK3568/Library/RK3568Lib/RK3568Mem.c
View File

@@ -1,194 +0,0 @@
/** @file
*
* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Soc.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
#define RK3568_EXTRA_SYSTEM_MEMORY_BASE 0x40000000
#define RK3568_EXTRA_SYSTEM_MEMORY_SIZE 0x40000000
STATIC struct RK3568ReservedMemory {
EFI_PHYSICAL_ADDRESS Offset;
EFI_PHYSICAL_ADDRESS Size;
} RK3568ReservedMemoryBuffer [] = {
{ 0x00000000, 0x00A00000 }, // ATF
// { 0x05F01000, 0x00001000 }, // ADB REBOOT "REASON"
// { 0x06DFF000, 0x00001000 }, // MAILBOX
// { 0x0740F000, 0x00001000 }, // MAILBOX
// { 0x21F00000, 0x00100000 }, // PSTORE/RAMOOPS
// { 0x3E000000, 0x02000000 } // TEE OS
};
STATIC
UINT64
EFIAPI
RK3568InitMemorySize (
IN VOID
)
{
//UINT32 Data;
UINT64 MemorySize;
//Data = MmioRead32 (MDDRC_AXI_BASE + AXI_REGION_MAP);
MemorySize = SIZE_2GB;//RK3568_REGION_SIZE(Data);
return MemorySize;
}
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
UINTN Index = 0, Count, ReservedTop;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
EFI_PEI_HOB_POINTERS NextHob;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
UINT64 ResourceLength;
EFI_PHYSICAL_ADDRESS ResourceTop;
UINT64 MemorySize, AdditionalMemorySize;
MemorySize = RK3568InitMemorySize ();
if (MemorySize == 0) {
MemorySize = PcdGet64 (PcdSystemMemorySize);
}
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED
);
// Create initial Base Hob for system memory.
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
PcdGet64 (PcdSystemMemoryBase),
PcdGet64 (PcdSystemMemorySize)
);
NextHob.Raw = GetHobList ();
Count = sizeof (RK3568ReservedMemoryBuffer) / sizeof (struct RK3568ReservedMemory);
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
if (Index >= Count) {
break;
}
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
(RK3568ReservedMemoryBuffer[Index].Offset >= NextHob.ResourceDescriptor->PhysicalStart) &&
((RK3568ReservedMemoryBuffer[Index].Offset + RK3568ReservedMemoryBuffer[Index].Size) <=
NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength)) {
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
ReservedTop = RK3568ReservedMemoryBuffer[Index].Offset + RK3568ReservedMemoryBuffer[Index].Size;
// Create the System Memory HOB for the reserved buffer
BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
EFI_RESOURCE_ATTRIBUTE_PRESENT,
RK3568ReservedMemoryBuffer[Index].Offset,
RK3568ReservedMemoryBuffer[Index].Size);
// Update the HOB
NextHob.ResourceDescriptor->ResourceLength = RK3568ReservedMemoryBuffer[Index].Offset - NextHob.ResourceDescriptor->PhysicalStart;
// If there is some memory available on the top of the reserved memory then create a HOB
if (ReservedTop < ResourceTop) {
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
ReservedTop,
ResourceTop - ReservedTop);
}
Index++;
}
NextHob.Raw = GET_NEXT_HOB (NextHob);
}
AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
if (AdditionalMemorySize >= SIZE_1GB) {
// Declared the additional memory
ResourceAttributes =
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED;
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
RK3568_EXTRA_SYSTEM_MEMORY_BASE,
RK3568_EXTRA_SYSTEM_MEMORY_SIZE);
}
ASSERT (VirtualMemoryMap != NULL);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
CacheAttributes = DDR_ATTRIBUTES_CACHED;
Index = 0;
// RK3568 SOC peripherals
VirtualMemoryTable[Index].PhysicalBase = RK3568_PERIPH_BASE;
VirtualMemoryTable[Index].VirtualBase = RK3568_PERIPH_BASE;
VirtualMemoryTable[Index].Length = RK3568_PERIPH_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// DDR - predefined 1GB size
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// If DDR capacity is 2GB size, append a new entry to fill the gap.
if (AdditionalMemorySize >= SIZE_1GB) {
VirtualMemoryTable[++Index].PhysicalBase = RK3568_EXTRA_SYSTEM_MEMORY_BASE;
VirtualMemoryTable[Index].VirtualBase = RK3568_EXTRA_SYSTEM_MEMORY_BASE;
VirtualMemoryTable[Index].Length = RK3568_EXTRA_SYSTEM_MEMORY_SIZE;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
*VirtualMemoryMap = VirtualMemoryTable;
}

34
edk2-rockchip/Platform/Rockchip/RK3568/Library/RockchipPlatformLib/CruLib.inf
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@@ -1,34 +0,0 @@
#
# Copyright (c) 2021, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RockchipPlatformLib
FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RockchipPlatformLib
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3568/RK3568.dec
Silicon/Rockchip/RK3568/RK3568.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
[Sources.common]
RK3568CruLib.c
[Sources.AARCH64]
[FixedPcd]

1300
edk2-rockchip/Platform/Rockchip/RK3568/Library/RockchipPlatformLib/RK3568CruLib.c
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File diff suppressed because it is too large Load Diff

46
edk2-rockchip/Platform/Rockchip/RK3568/Library/RockchipPlatformLib/RockchipPlatformLib.c
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@@ -1,46 +0,0 @@
/** @file
*
* Copyright (c) 2021, Rockchip Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/DebugLib.h>
#include <Soc.h>
void DebugPrintHex(void *buf, UINT32 width, UINT32 len)
{
UINT32 i,j;
UINT8 *p8 = (UINT8 *) buf;
UINT16 *p16 = (UINT16 *) buf;
UINT32 *p32 =(UINT32 *) buf;
j = 0;
for (i = 0; i < len; i++) {
if (j == 0)
DebugPrint(DEBUG_ERROR, "%p + 0x%x:",buf, i * width);
if (width == 4)
DebugPrint(DEBUG_ERROR, "0x%08x,", p32[i]);
else if (width == 2)
DebugPrint(DEBUG_ERROR, "0x%04x,", p16[i]);
else
DebugPrint(DEBUG_ERROR, "0x%02x,", p8[i]);
if (++j >= (16/width)) {
j = 0;
DebugPrint(DEBUG_ERROR, "\n","");
}
}
DebugPrint(DEBUG_ERROR, "\n","");
}
void DwEmmcDxeIoMux(void)
{
/* sdmmc0 iomux */
GRF->GPIO1D_IOMUX_H = (0x7770UL << 16) | (0x111 << 4);
GRF->GPIO2A_IOMUX_L = (0x777UL << 16) | (0x111 << 0);
GRF->GPIO0A_IOMUX_H = (0x77 << 16) | (0x11 << 0);
GRF->SDMMC_DET_COUNTER = 2;
}

39
edk2-rockchip/Platform/Rockchip/RK3568/Library/RockchipPlatformLib/RockchipPlatformLib.inf
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@@ -1,39 +0,0 @@
#
# Copyright (c) 2021, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RockchipPlatformLib
FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RockchipPlatformLib
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3568/RK3568.dec
Silicon/Rockchip/RK3568/RK3568.dec
Silicon/Rockchip/RockchipPkg.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
CruLib
[Sources.common]
RockchipPlatformLib.c
RK3568CruLib.c
RockchipSdhci.c
[Sources.AARCH64]
[Pcd]
gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress

96
edk2-rockchip/Platform/Rockchip/RK3568/Library/RockchipPlatformLib/RockchipSdhci.c
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@@ -1,96 +0,0 @@
/** @file
*
* Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "RockchipSdhci.h"
#include <Library/PcdLib.h>
#define GRF_BASE 0xFDC60000
#define NS_CRU_BASE 0xFDD20000
#define CRU_CLKSEL_CON28 0x0170
#define EMMC_CLOCK_BASE (NS_CRU_BASE + CRU_CLKSEL_CON28)
#define EMMC_CLOCK_SEL(a) (((7 << 12) << 16) | (a << 12))
#define EMMCPHY_BASE PcdGet32 (PcdSdhciDxeBaseAddress)
#define DWCMSHC_HOST_CTRL3 (EMMC_BASE + 0x508)
#define EMMC_DLL_CTRL (EMMC_BASE + 0x800)
#define EMMC_DLL_RXCLK (EMMC_BASE + 0x804)
#define EMMC_DLL_TXCLK (EMMC_BASE + 0x808)
#define EMMC_DLL_STRBIN (EMMC_BASE + 0x80C)
#define EMMC_DLL_STATUS0 (EMMC_BASE + 0x840)
#define EMMC_DLL_STATUS1 (EMMC_BASE + 0x844)
EFI_STATUS SdhciSetPHY(
IN UINTN Clock
)
{
UINT32 Tmp;
/* Disable cmd conflict check */
Tmp = MmioRead32(DWCMSHC_HOST_CTRL3);
Tmp &= ~BIT0;
MmioWrite32(EMMCPHY_BASE + DWCMSHC_HOST_CTRL3, Tmp);
if (Clock < 100000000) {
MmioWrite32(EMMC_DLL_CTRL, 0);
MmioWrite32(EMMC_DLL_RXCLK, 1<<29); /* PIO mode need set bit 29*/
MmioWrite32(EMMC_DLL_TXCLK, 0);
MmioWrite32(EMMC_DLL_STRBIN, 0);
return EFI_SUCCESS;
}
else {
return RETURN_UNSUPPORTED;
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
SdhciGetClockRate(
IN UINTN TargetFreq,
OUT UINTN *BaseFreq
)
{
UINT32 CClkEmmcSel;
if (TargetFreq == 0 || BaseFreq == NULL)
return -1;
if (TargetFreq >= 200000000) {
CClkEmmcSel = 1;
} else if (TargetFreq >= 150000000) {
CClkEmmcSel = 2;
} else if (TargetFreq >= 100000000) {
CClkEmmcSel = 3;
} else if (TargetFreq >= 50000000) {
CClkEmmcSel = 4;
} else if (TargetFreq >= 24000000) {
CClkEmmcSel = 0;
} else {
CClkEmmcSel = 5; /* 375KHZ */
}
SdhciSetPHY(TargetFreq);
*BaseFreq= TargetFreq;
DEBUG ((DEBUG_BLKIO, "MMCHost: Clock: %d\n", TargetFreq));
MmioWrite32(EMMC_CLOCK_BASE, EMMC_CLOCK_SEL(CClkEmmcSel));
DEBUG ((DEBUG_BLKIO, "EMMC_CLOCK 0x%x: 0x%x:\n", EMMC_CLOCK_BASE, MmioRead32(EMMC_CLOCK_BASE)));
//DEBUG ((DEBUG_BLKIO, "GPIO1B_IOMUX_H: 0x%x:\n", MmioRead32(GRF_BASE+0x0C)));
//DEBUG ((DEBUG_BLKIO, "GPIO1C_IOMUX_L: 0x%x:\n", MmioRead32(GRF_BASE+0x10)));
//DEBUG ((DEBUG_BLKIO, "GPIO1C_IOMUX_H: 0x%x:\n", MmioRead32(GRF_BASE+0x14)));
//DEBUG ((DEBUG_BLKIO, "EMMC_DLL_CTRL: 0x%x:\n", MmioRead32(EMMC_DLL_CTRL)));
//DEBUG ((DEBUG_BLKIO, "EMMC_DLL_RXCLK: 0x%x:\n", MmioRead32(EMMC_DLL_RXCLK)));
//DEBUG ((DEBUG_BLKIO, "EMMC_DLL_TXCLK: 0x%x:\n", MmioRead32(EMMC_DLL_TXCLK)));
return EFI_SUCCESS;
}

33
edk2-rockchip/Platform/Rockchip/RK3568/Library/RockchipPlatformLib/RockchipSdhci.h
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@@ -1,33 +0,0 @@
/** @file
*
* Copyright (c) Rockchip Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef _ROCKCHIP_SDHCI_H_
#define _ROCKCHIP_SDHCI_H_
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
#define EMMC_BASE 0xFE310000
EFI_STATUS
SdhciGetClockRate (
IN UINTN TargetFreq,
OUT UINTN *BaseFreq
);
#endif

32
edk2-rockchip/Platform/Rockchip/RK3568/RK3568.dec
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@@ -1,32 +0,0 @@
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
DEC_SPECIFICATION = 0x0001001a
PACKAGE_NAME = RK3568
PACKAGE_GUID = 83dbcb08-3176-11ec-95b4-f42a7dcb925d
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[Guids.common]
gRK3568TokenSpaceGuid = { 0xc620b83a, 0x3175, 0x11ec, { 0x95, 0xb4, 0xf4, 0x2a, 0x7d, 0xcb, 0x92, 0x5d } }
[PcdsFixedAtBuild.common]
gRK3568TokenSpaceGuid.PcdAndroidBootDevicePath|L""|VOID*|0x00000001
gRK3568TokenSpaceGuid.PcdAndroidBootFile|{ 0x36, 0x8b, 0x73, 0x3a, 0xc5, 0xb9, 0x63, 0x47, 0xab, 0xbd, 0x6c, 0xbd, 0x4b, 0x25, 0xf9, 0xff }|VOID*|0x00000002
gRK3568TokenSpaceGuid.PcdAndroidFastbootFile|{ 0x2a, 0x50, 0x88, 0x95, 0x70, 0x53, 0xe3, 0x11, 0x86, 0x31, 0xd7, 0xc5, 0x95, 0x13, 0x64, 0xc8 }|VOID*|0x00000003
gRK3568TokenSpaceGuid.PcdSdBootDevicePath|L""|VOID*|0x00000004

319
edk2-rockchip/Platform/Rockchip/RK3568/RK3568.dsc
View File

@@ -1,319 +0,0 @@
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = RK3568
PLATFORM_GUID = 83dbcb08-3176-11ec-95b4-f42a7dcb925d
PLATFORM_VERSION = 0.2
DSC_SPECIFICATION = 0x00010019
OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
SUPPORTED_ARCHITECTURES = AARCH64
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Platform/Rockchip/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
DEFINE CONFIG_NO_DEBUGLIB = TRUE
#
# Network definition
#
DEFINE NETWORK_SNP_ENABLE = FALSE
DEFINE NETWORK_IP6_ENABLE = FALSE
DEFINE NETWORK_TLS_ENABLE = FALSE
DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
DEFINE NETWORK_ISCSI_ENABLE = FALSE
DEFINE NETWORK_VLAN_ENABLE = FALSE
!include Silicon/Rockchip/Rockchip.dsc.inc
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmPlatformLib|Platform/Rockchip/RK3568/Library/RK3568Lib/RK3568Lib.inf
RockchipPlatformLib|Platform/Rockchip/RK3568/Library/RockchipPlatformLib/RockchipPlatformLib.inf
CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
# UiApp dependencies
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
#SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
#RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
# USB Requirements
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
# VariableRuntimeDxe Requirements
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
[LibraryClasses.common.SEC]
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
[BuildOptions]
GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3568/Include -I$(WORKSPACE)/Platform/Rockchip/RK3568/Include
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFeatureFlag.common]
# If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
[PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
# System Memory (1GB)
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
# RK3568 CPU profile
gArmPlatformTokenSpaceGuid.PcdCoreCount|4
gArmPlatformTokenSpaceGuid.PcdClusterCount|1
#
# ARM PrimeCell
#
## UART2 - Serial Terminal
DEFINE SERIAL_BASE = 0xFE660000 # UART2
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
## PL031 RealTimeClock
#gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
#
# ARM General Interrupt Controller
#
gArmTokenSpaceGuid.PcdGicDistributorBase|0xfd400000
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfd400000
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfd460000
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
# GUID of the UI app
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
#
# DW SD card controller
#
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2b0000
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
#
# SDHCI controller
#
gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
#
#
# Fastboot
#
gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
#
# Android Loader
#
gRK3568TokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00D023F70000000000)/eMMC(0x0)/Ctrl(0x0)/HD(6,GPT,5C0F213C-17E1-4149-88C8-8B50FB4EC70E,0x7000,0x20000)/\\EFI\\BOOT\\GRUBAA64.EFI"
gRK3568TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(7,GPT,7A3F0000-0000-446A-8000-702F00006273,0xC800,0x14000)"
#
# Make VariableRuntimeDxe work at emulated non-volatile variable mode.
#
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
#
# PEI Phase modules
#
ArmPlatformPkg/PrePi/PeiUniCore.inf
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf
#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
}
#
# Architectural Protocols
#
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
#EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
}
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
#
# GPIO
#
Platform/Rockchip/RK3568/RK3568GpioDxe/RK3568GpioDxe.inf
#ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
#
# Virtual Keyboard
#
EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
Platform/Rockchip/RK3568/RK3568Dxe/RK3568Dxe.inf
#
# MMC/SD
#
#EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
#Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
#
# USB Host Support
#
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
#
# USB Mass Storage Support
#
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# USB Peripheral Support
#
EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
#
# Fastboot
#
EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
#
# Android Boot applications
#
EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
#
# UEFI Network Stack
#
!include NetworkPkg/Network.dsc.inc
#
# AX88772 Ethernet Driver
#
Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
#
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf
#
# Bds
#
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
MdeModulePkg/Application/UiApp/UiApp.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
#NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
}
!ifdef $(INCLUDE_TFTP_COMMAND)
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)

226
edk2-rockchip/Platform/Rockchip/RK3568/RK3568.fdf
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@@ -1,226 +0,0 @@
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.BL33_AP_UEFI]
BaseAddress = 0x00A00000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
# This one is tricky, it must be: BlockSize * NumBlocks = Size
BlockSize = 0x00001000
NumBlocks = 0xF0
################################################################################
#
# Following are lists of FD Region layout which correspond to the locations of different
# images within the flash device.
#
# Regions must be defined in ascending order and may not overlap.
#
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
# the pipe "|" character, followed by the size of the region, also in hex with the leading
# "0x" characters. Like:
# Offset|Size
# PcdOffsetCName|PcdSizeCName
# RegionType <FV, DATA, or FILE>
#
################################################################################
0x00000000|0x000F0000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FvMain]
BlockSize = 0x40
NumBlocks = 0 # This FV gets compressed so make it just big enough
FvAlignment = 8 # FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
APRIORI DXE {
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
}
INF MdeModulePkg/Core/Dxe/DxeMain.inf
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
#
# Multiple Console IO support
#
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
#
# GPIO
#
INF Platform/Rockchip/RK3568/RK3568GpioDxe/RK3568GpioDxe.inf
#INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
#
# Virtual Keyboard
#
INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
INF Platform/Rockchip/RK3568/RK3568Dxe/RK3568Dxe.inf
#
# Multimedia Card Interface
#
#INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
#INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
#
# USB Host Support
#
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
#
# USB Mass Storage Support
#
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# USB Peripheral Support
#
INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
#
# Fastboot
#
INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
#
# Android Boot applications
#
INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
#
# UEFI Network Stack
#
!include NetworkPkg/Network.fdf.inc
#
# AX88772 Ethernet Driver for Apple Ethernet Adapter
#
INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
#
# FAT filesystem + GPT/MBR partitioning
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
#
# UEFI applications
#
INF ShellPkg/Application/Shell/Shell.inf
!ifdef $(INCLUDE_TFTP_COMMAND)
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)
#
# Bds
#
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF ArmPlatformPkg/PrePi/PeiUniCore.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
!include Silicon/Rockchip/Rockchip.fdf.inc

381
edk2-rockchip/Platform/Rockchip/RK3568/RK3568Dxe/RK3568Dxe.c
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@@ -1,381 +0,0 @@
/** @file
*
* Copyright (c) 2018, Linaro Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/CacheMaintenanceLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootManagerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Protocol/DevicePath.h>
#include <Protocol/DevicePathFromText.h>
#include <Protocol/EmbeddedGpio.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/PlatformBootManager.h>
#include <Protocol/PlatformVirtualKeyboard.h>
#include <Protocol/AndroidBootImg.h>
#include <Soc.h>
#include <RK3568RegsPeri.h>
#include "RK3568Dxe.h"
STATIC
VOID
UartInit (
IN VOID
)
{
//UINT32 Val;
/* make UART1 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1);
/* make UART2 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2);
/* make UART3 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3);
/* make UART4 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4);
//MmioWrite32 (CRU_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4);
/* make DW_MMC2 out of reset */
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2);
/* enable clock for BT/WIFI */
//Val = MmioRead32 (PMUSSI_ONOFF8_REG) | PMUSSI_ONOFF8_EN_32KB;
//MmioWrite32 (PMUSSI_ONOFF8_REG, Val);
}
STATIC EMBEDDED_GPIO *mGpio;
STATIC
VOID
MtcmosInit (
IN VOID
)
{
//UINT32 Data;
/* enable MTCMOS for GPU */
//MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D);
//do {
// Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0);
//} while ((Data & PW_EN0_G3D) == 0);
}
EFI_STATUS
RK3568InitPeripherals (
IN VOID
)
{
//UINT32 Data, Bits;
/* make I2C0/I2C1/I2C2/SPI0 out of reset */
//Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | PERIPH_RST3_SSP;
//MmioWrite32 (CRU_BASE + SC_PERIPH_RSTDIS3, Bits);
//do {
// Data = MmioRead32 (CRU_BASE + SC_PERIPH_RSTSTAT3);
//} while (Data & Bits);
UartInit ();
/* MTCMOS -- Multi-threshold CMOS */
MtcmosInit ();
/* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */
//MmioWrite32 (IOCG_084_REG, 0); /* configure GPIO24 as nopull */
//MmioWrite32 (IOMG_080_REG, 0); /* configure GPIO24 as GPIO */
return EFI_SUCCESS;
}
STATIC
EFI_STATUS
CreatePlatformBootOptionFromPath (
IN CHAR16 *PathStr,
IN CHAR16 *Description,
IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *BootOption
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH *DevicePath;
DevicePath = (EFI_DEVICE_PATH *)ConvertTextToDevicePath (PathStr);
ASSERT (DevicePath != NULL);
Status = EfiBootManagerInitializeLoadOption (
BootOption,
LoadOptionNumberUnassigned,
LoadOptionTypeBoot,
LOAD_OPTION_ACTIVE,
Description,
DevicePath,
NULL,
0
);
FreePool (DevicePath);
return Status;
}
STATIC
EFI_STATUS
CreatePlatformBootOptionFromGuid (
IN EFI_GUID *FileGuid,
IN CHAR16 *Description,
IN OUT EFI_BOOT_MANAGER_LOAD_OPTION *BootOption
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH *DevicePath;
EFI_DEVICE_PATH *TempDevicePath;
EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
Status = gBS->HandleProtocol (
gImageHandle,
&gEfiLoadedImageProtocolGuid,
(VOID **) &LoadedImage
);
ASSERT_EFI_ERROR (Status);
EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
TempDevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle);
ASSERT (TempDevicePath != NULL);
DevicePath = AppendDevicePathNode (
TempDevicePath,
(EFI_DEVICE_PATH_PROTOCOL *) &FileNode
);
ASSERT (DevicePath != NULL);
Status = EfiBootManagerInitializeLoadOption (
BootOption,
LoadOptionNumberUnassigned,
LoadOptionTypeBoot,
LOAD_OPTION_ACTIVE,
Description,
DevicePath,
NULL,
0
);
FreePool (DevicePath);
return Status;
}
STATIC
EFI_STATUS
GetPlatformBootOptionsAndKeys (
OUT UINTN *BootCount,
OUT EFI_BOOT_MANAGER_LOAD_OPTION **BootOptions,
OUT EFI_INPUT_KEY **BootKeys
)
{
EFI_GUID *FileGuid;
CHAR16 *PathStr;
EFI_STATUS Status;
UINTN Size;
Size = sizeof (EFI_BOOT_MANAGER_LOAD_OPTION) * HIKEY_BOOT_OPTION_NUM;
*BootOptions = (EFI_BOOT_MANAGER_LOAD_OPTION *)AllocateZeroPool (Size);
if (*BootOptions == NULL) {
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootOptions\n"));
return EFI_OUT_OF_RESOURCES;
}
Size = sizeof (EFI_INPUT_KEY) * HIKEY_BOOT_OPTION_NUM;
*BootKeys = (EFI_INPUT_KEY *)AllocateZeroPool (Size);
if (*BootKeys == NULL) {
DEBUG ((DEBUG_ERROR, "Failed to allocate memory for BootKeys\n"));
Status = EFI_OUT_OF_RESOURCES;
goto Error;
}
PathStr = (CHAR16 *)PcdGetPtr (PcdSdBootDevicePath);
ASSERT (PathStr != NULL);
Status = CreatePlatformBootOptionFromPath (
PathStr,
L"Boot from SD",
&(*BootOptions)[0]
);
ASSERT_EFI_ERROR (Status);
PathStr = (CHAR16 *)PcdGetPtr (PcdAndroidBootDevicePath);
ASSERT (PathStr != NULL);
Status = CreatePlatformBootOptionFromPath (
PathStr,
L"Grub",
&(*BootOptions)[1]
);
ASSERT_EFI_ERROR (Status);
FileGuid = PcdGetPtr (PcdAndroidBootFile);
ASSERT (FileGuid != NULL);
Status = CreatePlatformBootOptionFromGuid (
FileGuid,
L"Android Boot",
&(*BootOptions)[2]
);
ASSERT_EFI_ERROR (Status);
FileGuid = PcdGetPtr (PcdAndroidFastbootFile);
ASSERT (FileGuid != NULL);
Status = CreatePlatformBootOptionFromGuid (
FileGuid,
L"Android Fastboot",
&(*BootOptions)[3]
);
ASSERT_EFI_ERROR (Status);
(*BootKeys)[3].ScanCode = SCAN_NULL;
(*BootKeys)[3].UnicodeChar = 'f';
*BootCount = 4;
return EFI_SUCCESS;
Error:
FreePool (*BootOptions);
return Status;
}
PLATFORM_BOOT_MANAGER_PROTOCOL mPlatformBootManager = {
GetPlatformBootOptionsAndKeys
};
EFI_STATUS
EFIAPI
VirtualKeyboardRegister (
IN VOID
)
{
EFI_STATUS Status;
Status = gBS->LocateProtocol (
&gEmbeddedGpioProtocolGuid,
NULL,
(VOID **) &mGpio
);
if (EFI_ERROR (Status)) {
return Status;
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
VirtualKeyboardReset (
IN VOID
)
{
EFI_STATUS Status;
if (mGpio == NULL) {
return EFI_INVALID_PARAMETER;
}
Status = mGpio->Set (mGpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT);
return Status;
}
BOOLEAN
EFIAPI
VirtualKeyboardQuery (
IN VIRTUAL_KBD_KEY *VirtualKey
)
{
EFI_STATUS Status;
UINTN Value = 0;
if ((VirtualKey == NULL) || (mGpio == NULL)) {
return FALSE;
}
if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
goto Done;
} else {
Status = mGpio->Get (mGpio, DETECT_J15_FASTBOOT, &Value);
if (EFI_ERROR (Status) || (Value != 0)) {
return FALSE;
}
}
Done:
VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE;
VirtualKey->Key.ScanCode = SCAN_NULL;
VirtualKey->Key.UnicodeChar = L'f';
return TRUE;
}
EFI_STATUS
EFIAPI
VirtualKeyboardClear (
IN VIRTUAL_KBD_KEY *VirtualKey
)
{
if (VirtualKey == NULL) {
return EFI_INVALID_PARAMETER;
}
if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) {
MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE);
WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4);
}
return EFI_SUCCESS;
}
PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = {
VirtualKeyboardRegister,
VirtualKeyboardReset,
VirtualKeyboardQuery,
VirtualKeyboardClear
};
ANDROID_BOOTIMG_PROTOCOL mAndroidBootImageManager = {
NULL,
NULL
};
EFI_STATUS
EFIAPI
RK3568EntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
Status = RK3568InitPeripherals ();
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->InstallProtocolInterface (
&ImageHandle,
&gPlatformVirtualKeyboardProtocolGuid,
EFI_NATIVE_INTERFACE,
&mVirtualKeyboard
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->InstallProtocolInterface (
&ImageHandle,
&gPlatformBootManagerProtocolGuid,
EFI_NATIVE_INTERFACE,
&mPlatformBootManager
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->InstallProtocolInterface (
&ImageHandle,
&gAndroidBootImgProtocolGuid,
EFI_NATIVE_INTERFACE,
&mAndroidBootImageManager
);
return Status;
}

20
edk2-rockchip/Platform/Rockchip/RK3568/RK3568Dxe/RK3568Dxe.h
View File

@@ -1,20 +0,0 @@
/** @file
*
* Copyright (c) 2018, Linaro Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __HIKEYDXE_H__
#define __HIKEYDXE_H__
#define DETECT_J15_FASTBOOT 24 // GPIO3_0
#define ADB_REBOOT_ADDRESS 0x05F01000
#define ADB_REBOOT_BOOTLOADER 0x77665500
#define ADB_REBOOT_NONE 0x77665501
#define HIKEY_BOOT_OPTION_NUM 4
#endif /* __HIKEYDXE_H__ */

51
edk2-rockchip/Platform/Rockchip/RK3568/RK3568Dxe/RK3568Dxe.inf
View File

@@ -1,51 +0,0 @@
#
# Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.
# Copyright (c) 2018, Linaro Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x0001001a
BASE_NAME = RK3568Dxe
FILE_GUID = 101d1748-3177-11ec-95b4-f42a7dcb925d
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = RK3568EntryPoint
[Sources.common]
RK3568Dxe.c
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Platform/Rockchip/RK3568/RK3568.dec
[LibraryClasses]
CacheMaintenanceLib
DebugLib
IoLib
UefiBootManagerLib
UefiLib
UefiDriverEntryPoint
[Protocols]
gEfiDevicePathFromTextProtocolGuid
gEfiLoadedImageProtocolGuid
gEmbeddedGpioProtocolGuid
gPlatformBootManagerProtocolGuid
gPlatformVirtualKeyboardProtocolGuid
gAndroidBootImgProtocolGuid
[Pcd]
gRK3568TokenSpaceGuid.PcdAndroidBootDevicePath
gRK3568TokenSpaceGuid.PcdAndroidBootFile
gRK3568TokenSpaceGuid.PcdAndroidFastbootFile
gRK3568TokenSpaceGuid.PcdSdBootDevicePath
[Guids]
gEfiEndOfDxeEventGroupGuid
[Depex]
TRUE

53
edk2-rockchip/Platform/Rockchip/RK3568/RK3568GpioDxe/RK3568GpioDxe.c
View File

@@ -1,53 +0,0 @@
/** @file
*
* Copyright (c) 2018, Linaro. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedGpio.h>
GPIO_CONTROLLER gGpioDevice[] = {
//
// { base address, gpio index, gpio count }
//
{ 0xFDD60000, 0, 32 }, // GPIO0
{ 0xFE740000, 32, 32 }, // GPIO1
{ 0xFE750000, 64, 32 }, // GPIO2
{ 0xFE760000, 96, 32 }, // GPIO3
{ 0xFE770000, 128, 32 }, // GPIO3
};
PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = {
//
// { global gpio count, gpio controller counter, GPIO_CONTROLLER }
//
160, 20, gGpioDevice
};
EFI_STATUS
EFIAPI
RK3568GpioEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
// Install the Embedded Platform GPIO Protocol onto a new handle
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces(
&Handle,
&gPlatformGpioProtocolGuid, &gPlatformGpioDevice,
NULL
);
if (EFI_ERROR(Status)) {
Status = EFI_OUT_OF_RESOURCES;
}
return Status;
}

30
edk2-rockchip/Platform/Rockchip/RK3568/RK3568GpioDxe/RK3568GpioDxe.inf
View File

@@ -1,30 +0,0 @@
#
# Copyright (c) 2018, Linaro. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x0001001a
BASE_NAME = RK3568Gpio
FILE_GUID = 16bca67c-3177-11ec-95b4-f42a7dcb925d
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = RK3568GpioEntryPoint
[Sources.common]
RK3568GpioDxe.c
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
DebugLib
UefiDriverEntryPoint
[Protocols]
gPlatformGpioProtocolGuid
[Depex]
TRUE

41
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/AcpiTables.h
View File

@@ -1,41 +0,0 @@
/** @file
*
* RPi defines for constructing ACPI tables
*
* Copyright (c) 2020, Pete Batard <pete@akeo.ie>
* Copyright (c) 2019, ARM Ltd. All rights reserved.
* Copyright (c) 2018, Andrei Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __ACPITABLES_H__
#define __ACPITABLES_H__
#include <IndustryStandard/Acpi.h>
#define EFI_ACPI_OEM_ID {'R','K','C','P',' ',' '}
#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64 ('R','K','3','5','8','8',' ',' ')
#define EFI_ACPI_OEM_REVISION 0x00000000
#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('E','D','K','2')
#define EFI_ACPI_CREATOR_REVISION 0x00000000
#define EFI_ACPI_VENDOR_ID SIGNATURE_32 ('R','K','C','P')
// A macro to initialise the common header part of EFI ACPI tables as defined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
#define ACPI_HEADER(Signature, Type, Revision) { \
Signature, /* UINT32 Signature */ \
sizeof (Type), /* UINT32 Length */ \
Revision, /* UINT8 Revision */ \
0, /* UINT8 Checksum */ \
EFI_ACPI_OEM_ID, /* UINT8 OemId[6] */ \
EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
}
#endif // __ACPITABLES_H__

65
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/AcpiTables.inf
View File

@@ -1,65 +0,0 @@
#/** @file
#
# ACPI table data and ASL sources required to boot the platform.
#
# Copyright (c) 2019-2021, ARM Limited. All rights reserved.
# Copyright (c) Microsoft Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = AcpiTables
FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
MODULE_TYPE = USER_DEFINED
VERSION_STRING = 1.0
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = AARCH64
#
[Sources]
AcpiTables.h
Madt.aslc
Fadt.aslc
Gtdt.aslc
Dsdt.asl
Spcr.aslc
Mcfg.aslc
RK3588PcieIort.aslc
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64
#[BuildOptions]
#GCC:*_*_*_ASL_FLAGS = -vw3133 -vw3150

78
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Dsdt.asl
View File

@@ -1,78 +0,0 @@
/** @file
*
* Differentiated System Definition Table (DSDT)
*
* Copyright (c) 2020, Pete Batard <pete@akeo.ie>
* Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
{
Scope (\_SB_)
{
Device (CPU0)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x0)
Method (_STA)
{
Return (0xf)
}
}
Device (CPU1)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x1)
Method (_STA)
{
Return (0xf)
}
}
Device (CPU2)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x2)
Method (_STA)
{
Return (0xf)
}
}
Device (CPU3)
{
Name (_HID, "ACPI0007")
Name (_UID, 0x3)
Method (_STA)
{
Return (0xf)
}
}
Device(DEM0) {
Name (_HID, "RKCP0000")
Name (_UID, 0)
Method (_STA, 0, NotSerialized)
{
Return(0x0F)
}
}
include ("Pcie.aslc")
include ("Sata.asl")
include ("Emmc.asl")
include ("Gmac.asl")
include ("Gpio.asl")
include ("I2c.asl")
include ("Uart.asl")
include ("Spi.asl")
include ("Usb2.asl")
}
}

76
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Emmc.asl
View File

@@ -1,76 +0,0 @@
/** @file
*
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
Device (SDC3) {
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfe2e0000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 237 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk3588-dwcmshc" },
Package () { "max-frequency", 200000000 },
Package () { "bus-width", 8 },
Package () { "no-sd", 0x1 },
Package () { "no-sdio", 0x1 },
Package () { "mmc-hs400-1_8v", 0x1 },
Package () { "mmc-hs400-enhanced-strobe", 0x1 },
Package () { "non-removable", 0x1 },
}
})
OperationRegion(EMMC, SystemMemory, 0xFD7C0434, 0x4)
Field(EMMC, DWordAcc, Lock, WriteAsZeros) {
PLLE, 32,
}
Method(SCLK, 1, Serialized) {
If (Arg0 <= 400000)
{
Store (0xFF00BF00, PLLE)
}
ElseIF (Arg0 <= 50000000)
{
Store (0xFF008000, PLLE)
}
Else
{
Store (0xFF000600, PLLE)
}
}
Method(_PS3) {
}
Method(_PS2) {
Store (0xFF00BF00, PLLE)
}
Method(_PS1) {
Store (0xFF008000, PLLE)
}
Method(_PS0) {
Store (0xFF000600, PLLE)
}
Method(_PSC) {
Return(0x01)
}
}

96
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Fadt.aslc
View File

@@ -1,96 +0,0 @@
/** @file
*
* Fixed ACPI Description Table (FADT)
*
* Copyright (c) 2019, Pete Batard <pete@akeo.ie>
* Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/PcdLib.h>
#include "AcpiTables.h"
/*
* Windows 10 on the Raspberry Pi 3 requires a specific OEM Id for FADT.
* We replace the one that was defined in "AcpiTables.h", so that it is
* picked by the ACPI_HEADER () macro.
*/
#if (RPI_MODEL == 3)
#undef EFI_ACPI_OEM_ID
#define EFI_ACPI_OEM_ID {'R','O','C','K',' ',' '}
#endif
EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
ACPI_HEADER (
EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE,
EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
),
0, // UINT32 FirmwareCtrl
0, // UINT32 Dsdt
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC, // UINT8 PreferredPmProfile
0, // UINT16 SciInt
0, // UINT32 SmiCmd
0, // UINT8 AcpiEnable
0, // UINT8 AcpiDisable
0, // UINT8 S4BiosReq
0, // UINT8 PstateCnt
0, // UINT32 Pm1aEvtBlk
0, // UINT32 Pm1bEvtBlk
0, // UINT32 Pm1aCntBlk
0, // UINT32 Pm1bCntBlk
0, // UINT32 Pm2CntBlk
0, // UINT32 PmTmrBlk
0, // UINT32 Gpe0Blk
0, // UINT32 Gpe1Blk
0, // UINT8 Pm1EvtLen
0, // UINT8 Pm1CntLen
0, // UINT8 Pm2CntLen
0, // UINT8 PmTmrLen
0, // UINT8 Gpe0BlkLen
0, // UINT8 Gpe1BlkLen
0, // UINT8 Gpe1Base
0, // UINT8 CstCnt
0, // UINT16 PLvl2Lat
0, // UINT16 PLvl3Lat
0, // UINT16 FlushSize
0, // UINT16 FlushStride
0, // UINT8 DutyOffset
0, // UINT8 DutyWidth
0, // UINT8 DayAlrm
0, // UINT8 MonAlrm
0, // UINT8 Century
EFI_ACPI_RESERVED_WORD, // UINT16 IaPcBootArch (Reserved on ARM)
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1
EFI_ACPI_6_3_WBINVD | EFI_ACPI_6_3_SLP_BUTTON | // UINT32 Flags
EFI_ACPI_6_3_HW_REDUCED_ACPI,
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg
0, // UINT8 ResetValue
EFI_ACPI_6_3_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
0, // UINT64 XFirmwareCtrl
0, // UINT64 XDsdt
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg
NULL_GAS // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
};
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Fadt;

214
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Gmac.asl
View File

@@ -1,214 +0,0 @@
/** @file
*
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
Device (MAC0) {
Name (_HID, "PRP0001")
Name (_UID, 0)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfe1b0000, 0x10000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 259, 258 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "interrupt-names", Package () { "macirq", "eth_wake_irq" }, },
Package (2) { "tx_delay", 67 },
Package (2) { "compatible", package () { "rockchip,rk3588-gmac", "snps,dwmac-4.20a" }, },
Package (2) { "phy-mode", "rgmii-rxid" },
Package (2) { "clock_in_out", "output" },
Package (2) { "csr-freq", 150000000 },
Package (2) { "snps,reset-delays-us", package () { 0, 20000, 100000 } },
Package (2) { "phy-handle", \_SB.MAC0.MDIO.PHY0 },
Package (2) { "snps,axi-config", \_SB.MAC0.AST0 },
Package (2) { "snps,mtl-rx-config", \_SB.MAC0.MRX0 },
Package (2) { "snps,mtl-tx-config", \_SB.MAC0.MTX0 },
Package () { "snps,mixed-burst", " " },
Package () { "snps,tso", " " },
Package () { "snps,reset-active-low", " " },
}
})
Method(PRST, 0, Serialized) {
OperationRegion(CTRL, SystemMemory, 0xfec50000, 0x10)
Field(CTRL, DWordAcc,Lock, Preserve) {
DRL, 32,
DRH, 32,
DDRL, 32,
DDRH, 32,
}
Store(0x08000800, DDRL)
sleep(20)
Store(0x08000000, DRL)
sleep(200)
Store(0x08000800, DRL)
sleep(1000)
}
Method(RGMI, 2, Serialized) {
OperationRegion(PGRF, SystemMemory, 0xfd5b0008, 0x70)
Field(PGRF, DWordAcc,Lock, Preserve) {
CON0, 32,
Offset(0x68),
CLK1, 32,
}
OperationRegion(SGRF, SystemMemory, 0xfd58c31c, 0x8)
Field(SGRF, DWordAcc,Lock, Preserve) {
CON7, 32,
CON8, 32,
}
Store(0x00380008, CON0)
Store(0x00010000, CLK1)
if (LGreater(ToInteger(Arg0), 0)) {
Store(0x00040004, CON7)
local0 = Arg0 & 0xff
local0 = local0 | 0x00ff0000
Store(local0, CON8)
}
if (LGreater(ToInteger(Arg1), 0)) {
Store(0x00080008, CON7)
local1 = Arg1 & 0x00
local1 = local1 << 8
local1 = local1 | 0xff000000
Store(local1, CON8)
}
}
Method(RMII, 0, Serialized) {
OperationRegion(PGRF, SystemMemory, 0xfd5b0008, 0x70)
Field(PGRF, DWordAcc,Lock, Preserve) {
CON0, 32,
Offset(0x68),
CLK1, 32,
}
Store(0x00380020, CON0)
Store(0x00010001, CLK1)
}
Method(SPED, 1, Serialized) {
OperationRegion(PGRF, SystemMemory, 0xfd5b0070, 0x4)
Field(PGRF, DWordAcc,Lock, Preserve) {
CLK1, 32,
}
if (LEqual(Arg0, 1000)) {
Store(0x000c0000, CLK1)
}
if (LEqual(Arg0, 100)) {
Store(0x000c000c, CLK1)
}
if (LEqual(Arg0, 10)) {
Store(0x000c0008, CLK1)
}
}
Method(CLKS, 2, Serialized) {
OperationRegion(PGRF, SystemMemory, 0xfd5b0070, 0x4)
Field(PGRF, DWordAcc,Lock, Preserve) {
CLK1, 32,
}
if (LEqual(Arg0, 0)) {
Store(0x00100010, CLK1)
}
if (LEqual(Arg1, 1)) {
Store(0x00020000, CLK1)
}
}
Device (AST0)
{
Name (_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "snps,wr_osr_lmt", 4 },
Package () { "snps,rd_osr_lmt", 8 },
Package () { "snps,blen", package () { 0, 0, 0, 0, 16, 8, 4 }, },
}
})
}
Device (MRX0)
{
Name (_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "snps,rx-queues-to-use", 2 },
}
})
Device (rxq0) {
Name (_ADR, 0)
}
Device (rxq1) {
Name (_ADR, 1)
}
}
Device (MTX0)
{
Name (_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "snps,tx-queues-to-use", 2 },
}
})
Device (txq0) {
Name (_ADR, 0)
}
Device (txq1) {
Name (_ADR, 1)
}
}
Device (MDIO)
{
Name (_HID, "PRP0001")
Name (_UID, 0)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "snps,dwmac-mdio" },
Package () { "#address-cells", 1},
}
})
Device (PHY0)
{
Name (_HID, "PRP0001")
Name (_UID, 0)
Name (_ADR, 1)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "ethernet-phy-ieee802.3-c22" },
Package () { "reg", 1},
}
})
}
}
}

161
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Gpio.asl
View File

@@ -1,161 +0,0 @@
/** @file
*
* Copyright (c) 2022, Rockchip Electronics Co. Ltd.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
//
// Description: GPIO
//
Device (GPI0)
{
Name (_HID, "PRP0001")
Name (_UID, 0x0)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "rockchip,gpio-bank" },
}
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xFD8A0000, 0x100)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {309}
})
Return(RBUF)
}
Method (_STA)
{
Return(0xf)
}
}//GPIO0
Device (GPI1)
{
Name (_HID, "PRP0001")
Name (_UID, 0x1)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "rockchip,gpio-bank" },
}
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xFEC20000, 0x100)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {310}
})
Return(RBUF)
}
Method (_STA)
{
Return(0xf)
}
}//GPIO1
Device (GPI2)
{
Name (_HID, "PRP0001")
Name (_UID, 0x2)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "rockchip,gpio-bank" },
}
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xFEC30000, 0x100)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {311}
})
Return(RBUF)
}
Method (_STA)
{
Return(0xf)
}
}//GPIO2
Device (GPI3)
{
Name (_HID, "PRP0001")
Name (_UID, 0x3)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "rockchip,gpio-bank" },
}
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xFEC40000, 0x100)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {312}
})
Return(RBUF)
}
Method (_STA)
{
Return(0xf)
}
}//GPIO3
Device (GPI4)
{
Name (_HID, "PRP0001")
Name (_UID, 0x4)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "rockchip,gpio-bank" },
}
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xFEC50000, 0x100)
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {313}
})
Return(RBUF)
}
Method (_STA)
{
Return(0xf)
}
}//GPIO4
Device (PINC)
{
Name (_HID, "PRP0001")
Name (_UID, 0x4)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "rockchip,rk3588-pinctrl" },
}
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xFD5F0000, 0x10000)
})
Return(RBUF)
}
Method (_STA)
{
Return(0xf)
}
}

88
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Gtdt.aslc
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@@ -1,88 +0,0 @@
/** @file
* Generic Timer Description Table (GTDT)
*
* Copyright (c) 2018, Linaro Limited. All rights reserved.
* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "ArmPlatform.h"
#include <Library/AcpiLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>
#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
#define GTDT_GLOBAL_FLAGS_LEVEL 0
// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
#ifdef SYSTEM_TIMER_BASE_ADDRESS
#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
#else
#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
#endif
#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
#define GTDT_TIMER_LEVEL_TRIGGERED 0
#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
#define GTDT_TIMER_ACTIVE_HIGH 0
#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long
#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long
#define EFI_ACPI_ARM_OEM_REVISION 0x20140727
#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
Signature, /* UINT32 Signature */ \
sizeof (Type), /* UINT32 Length */ \
Revision, /* UINT8 Revision */ \
0, /* UINT8 Checksum */ \
{ EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
}
#pragma pack (1)
typedef struct {
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
} GENERIC_TIMER_DESCRIPTION_TABLE;
#pragma pack ()
GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
{
ARM_ACPI_HEADER(
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
GENERIC_TIMER_DESCRIPTION_TABLE,
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
),
SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
0, // UINT32 Reserved
FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
0, // UINT32 PlatformTimerCount
},
};
//
// Reference the table being generated to prevent the optimizer
// from removing the data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Gtdt;

55
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/I2c.asl
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@@ -1,55 +0,0 @@
/** @file
*
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
Device (I2C2) {
Name (_HID, "PRP0001")
Name (_UID, 2)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfeaa0000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 351 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "i2c,clk-rate", 198000000 },
Package (2) { "compatible", "rockchip,rk3399-i2c" },
Package (2) { "#address-cells", 1 },
Package (2) { "#size-cells", 0 },
}
})
OperationRegion(I2PC, SystemMemory, 0xFD7C0828, 0x4)
Field(I2PC, DWordAcc, Lock, WriteAsZeros) {
CG10, 32,
}
OperationRegion(I2SC, SystemMemory, 0xFD7C082c, 0x4)
Field(I2SC, DWordAcc, Lock, WriteAsZeros) {
CG11, 32,
}
Method(_PS3) {
Store (0x02000200, CG10)
Store (0x00020002, CG11)
}
Method(_PS0) {
Store (0x02000000, CG10)
Store (0x00020000, CG11)
}
Method(_PSC) {
Return(0x01)
}
}

108
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Madt.aslc
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@@ -1,108 +0,0 @@
/** @file
* Multiple APIC Description Table (MADT)
*
* Copyright (c) 2016 Linaro Ltd. All rights reserved.
* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include "AcpiTables.h"
//
// Multiple APIC Description Table
//
#pragma pack (1)
#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) { \
EFI_ACPI_6_0_GIC_ITS, \
sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), \
0, \
Id, \
PhysAddress, \
0 \
}
typedef struct {
EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
EFI_ACPI_6_3_GIC_STRUCTURE GicInterfaces[8];
EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
EFI_ACPI_6_3_GICR_STRUCTURE GicRedistributor;
EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts[2];
} RK_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
RK_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ACPI_HEADER (
EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
RK_MULTIPLE_APIC_DESCRIPTION_TABLE,
EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
0, // LocalApicAddress
0, // Flags
},
{
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
0, 0, GET_MPID(0, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
//
// Use 1 for GICR Base Address below, since Windows 10 on Raspberry Pi 3 does not
// boot otherwise, and this is the value that Microsoft had in their IoT blobs.
// Kept to 1 for GICv2-based Pi 4, since this field only matters for GICv3.
//
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
1, 1, GET_MPID(1, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
2, 2, GET_MPID(2, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
3, 3, GET_MPID(3, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
4, 4, GET_MPID(4, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
5, 5, GET_MPID(5, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
6, 6, GET_MPID(6, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
EFI_ACPI_6_3_GICC_STRUCTURE_INIT (
7, 7, GET_MPID(7, 0), EFI_ACPI_6_3_GIC_ENABLED, 23,
FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase),
FixedPcdGet64 (PcdGicInterruptInterfaceBase), 25, FixedPcdGet64 (PcdGicRedistributorsBase), 1, 0),
},
EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase), 0, 3),
{
EFI_ACPI_6_3_GICR,
sizeof (EFI_ACPI_6_3_GICR_STRUCTURE),
EFI_ACPI_RESERVED_WORD,
FixedPcdGet32 (PcdGicRedistributorsBase),
0x100000
},
{
EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0x0, 0xfe640000),
EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0x1, 0xfe660000)
},
};
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Madt;

41
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Mcfg.aslc
View File

@@ -1,41 +0,0 @@
/** @file
* PCI Express Memory-mapped Configuration Space base address description table (MCFG)
*
* Copyright (c) 2022, Rockchip Inc.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include "AcpiTables.h"
#pragma pack(push, 1)
typedef struct {
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Entry;
} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {
{
ACPI_HEADER (
EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE,
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
),
}, {
FixedPcdGet64 (PcdPcieRootPort3x4CfgBaseAddress), //pcie3x4, + 0x8000?
0, // PciSegmentNumber
0x0, // PciBusMin
0xf, // PciBusMax
0 // Reserved
}
};
#pragma pack(pop)
VOID* CONST ReferenceAcpiTable = &Mcfg;

131
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Pcie.aslc
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@@ -1,131 +0,0 @@
/** @file
* PCIe Controller devices.
*
* Copyright (c) 2022, Rockchip Inc.
* SPDX-License-Identifier: BSD-2-Clause-Patent
**/
//#include <IndustryStandard/Acpi64.h>
#include "AcpiTables.h"
// PCIe 3x4
Device (PCI0) {
Name (_HID, "PNP0A08") // PCI Express Root Bridge
Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
Name (_CCA, Zero)
Name (_SEG, Zero) // Segment of this Root complex
Name (_BBN, Zero) // Base Bus Number
Name (_PRT, Package() { //legacy的支持需要route到不同的SPI，目前无法使用。。。
Package (4) { 0x0FFFF, 0, Zero, 292 },
Package (4) { 0x0FFFF, 1, Zero, 292 },
Package (4) { 0x0FFFF, 2, Zero, 292 },
Package (4) { 0x0FFFF, 3, Zero, 292 }
})
Method (_CRS, 0, Serialized) { // Root complex resources
Name (RBUF, ResourceTemplate () {
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, // Bus numbers assigned to this root
0, // Granularity
0, // AddressMinimum - Minimum Bus Number
0xf, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
16, // RangeLength - Number of Busses
)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, // 32-bit BAR Windows
0x00000000, // Granularity
FixedPcdGet32 (PcdPcieRootPort3x4MemBaseAddress), // Range Minimum
0xF0FFFFFF, // Range Maximum
0x00000000, // Translation Offset
FixedPcdGet32 (PcdPcieRootPort3x4MemSize), // Length
)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, // 64-bit BAR Windows
0x0000000000000000, // Granularity
FixedPcdGet64 (PcdPcieRootPort3x4MemBaseAddress64), // Range Minimum
0x000000093fffffff, // Range Maximum
0x0000000000000000, // Translation Offset
FixedPcdGet64 (PcdPcieRootPort3x4MemSize64), // Length
)
QWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, // IO BAR Windows
0, // Granularity
0x0000, // Range Minimum
0xFFFF, // Range Maximum
FixedPcdGet32 (PcdPcieRootPort3x4IoBaseAddress), // Translation Offset
FixedPcdGet32 (PcdPcieRootPort3x4IoSize), // Length
)
})
return (RBUF)
}
Method (_CBA, 0, NotSerialized) {
return (0x900000000) //指定外设ECAM空间,acpi_pci_root_get_mcfg_addr拿到的是这个，且不能和Mcfg里面的地址一样
}
Device (RES0) {
Name (_HID, "RKCP0001") // PCIe RC config base address
Name (_CID, "PNP0C02") // Motherboard reserved resource
Name (_UID, 0x0) // Unique ID
Name (_CRS, ResourceTemplate (){
Memory32Fixed (ReadWrite, 0xf5000000 , 0x400000) //DBI for accessing RC config base address
QWordMemory ( // 64-bit PCIe ECAM window
ResourceProducer,
PosDecode,
MinFixed,
MaxFixed,
NonCacheable,
ReadWrite,
0x0000000000000000, // Granularity
0x900000000, // Range Minimum
0x900ffffff, // Range Maximum
0x0000000000000000, // Translation Offset
0x1000000, // Length
,
,
,
AddressRangeMemory,
TypeStatic
)
})
}
// OS Control Handoff
Name(SUPP, Zero) // PCI _OSC Support Field value
Name(CTRL, Zero) // PCI _OSC Control Field value
// See [1] 6.2.10, [2] 4.5
Method(_OSC,4) {
// Note, This code is very similar to the code in the PCIe firmware
// specification which can be used as a reference
// Check for proper UUID
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
// Create DWord-adressable fields from the Capabilities Buffer
CreateDWordField(Arg3,0,CDW1)
CreateDWordField(Arg3,4,CDW2)
CreateDWordField(Arg3,8,CDW3)
// Save Capabilities DWord2 & 3
Store(CDW2,SUPP)
Store(CDW3,CTRL)
// Mask out Native HotPlug
And(CTRL,0x1E,CTRL)
// Always allow native PME, AER (no dependencies)
// Never allow SHPC (no SHPC controller in this system)
And(CTRL,0x1D,CTRL)
If(LNotEqual(Arg1,One)) { // Unknown revision
Or(CDW1,0x08,CDW1)
}
If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
Or(CDW1,0x10,CDW1)
}
// Update DWORD3 in the buffer
Store(CTRL,CDW3)
Return(Arg3)
} Else {
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
} // End _OSC
} // PCI0

139
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/RK3588PcieIort.aslc
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@@ -1,139 +0,0 @@
/** @file
* I/O Remapping Table (Iort)
*
* Copyright (c) 2018, ARM Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/Acpi62.h>
#include <IndustryStandard/IoRemappingTable.h>
#include "AcpiTables.h"
#pragma pack(1)
#define EFI_ACPI_ARM_OEM_ID 'A','R','M','L','T','D' // OEMID 6 bytes long
#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('A','R','M','-','J','U','N','O') // OEM table id 8 bytes long
#define EFI_ACPI_ARM_OEM_REVISION 0x20140727
#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
Signature, /* UINT32 Signature */ \
sizeof (Type), /* UINT32 Length */ \
Revision, /* UINT8 Revision */ \
0, /* UINT8 Checksum */ \
{ EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
}
typedef struct
{
EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode;
UINT32 ItsIdentifiers;
} ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
typedef struct
{
EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode;
EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap;
} ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
typedef struct
{
EFI_ACPI_6_0_IO_REMAPPING_TABLE Header;
ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Its0Node;
ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Its1Node;
ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Rc3x4Node;
} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE;
#pragma pack (1)
ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
{
// EFI_ACPI_6_0_IO_REMAPPING_TABLE
{
ARM_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER
(
EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE,
ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE,
EFI_ACPI_IO_REMAPPING_TABLE_REVISION
),
3, // NumNodes
sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
0, // Reserved
},
// ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE
{
// EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE
{
// EFI_ACPI_6_0_IO_REMAPPING_NODE
{
EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type
sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length
0, // Revision
0, // Reserved
0, // NumIdMappings
0, // IdReference
},
1, // ITS count
},
0, // GIC ITS Identifiers
},
// ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE
{
// EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE
{
// EFI_ACPI_6_0_IO_REMAPPING_NODE
{
EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type
sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length
0, // Revision
0, // Reserved
0, // NumIdMappings
0, // IdReference
},
1, // ITS count
},
1, // GIC ITS Identifiers
},
// ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE
{
// EFI_ACPI_6_0_IO_REMAPPING_RC_NODE
{
// EFI_ACPI_6_0_IO_REMAPPING_NODE
{
EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length
0, // Revision
0, // Reserved
1, // NumIdMappings
OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap) // IdReference
},
1, // CacheCoherent
0, // AllocationHints
0, // Reserved
0, // MemoryAccessFlags
EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED, // AtsAttribute
0x0, // PciSegmentNumber
},
// EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE
{
0x0000, // InputBase
0xffff, // NumIds
0x0000, // OutputBase
OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, Its1Node), // OutputReference
0, // Flags
}
}
};
VOID* CONST ReferenceAcpiTable = &Iort;

68
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Sata.asl
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@@ -1,68 +0,0 @@
/** @file
*
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
Device (ATA0) {
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfe210000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 305 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk-ahci" },
}
})
}
Device (ATA1) {
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfe220000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 306 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk-ahci" },
}
})
}
Device (ATA2) {
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfe230000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 307 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk-ahci" },
}
})
}

80
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Spcr.aslc
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@@ -1,80 +0,0 @@
/** @file
* SPCR Table
*
* Copyright (c) 2019 Pete Batard <pete@akeo.ie>
* Copyright (c) 2014-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
#include <Library/AcpiLib.h>
#include <Library/PcdLib.h>
#include "AcpiTables.h"
#define RPI_UART_FLOW_CONTROL_NONE 0
#define RPI_UART_INTERFACE_TYPE EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550
#define RPI_UART_BASE_ADDRESS 0xfeb50000
#define RPI_UART_INTERRUPT 365
STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
ACPI_HEADER (
EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
),
// UINT8 InterfaceType;
RPI_UART_INTERFACE_TYPE,
// UINT8 Reserved1[3];
{
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE
},
// EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddress;
ARM_GAS32 (RPI_UART_BASE_ADDRESS),
// UINT8 InterruptType;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
// UINT8 Irq;
0, // Not used on ARM
// UINT32 GlobalSystemInterrupt;
RPI_UART_INTERRUPT,
// UINT8 BaudRate;
0,
// UINT8 Parity;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
// UINT8 StopBits;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
// UINT8 FlowControl;
RPI_UART_FLOW_CONTROL_NONE,
// UINT8 TerminalType;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8,
// UINT8 Reserved2;
EFI_ACPI_RESERVED_BYTE,
// UINT16 PciDeviceId;
0xFFFF,
// UINT16 PciVendorId;
0xFFFF,
// UINT8 PciBusNumber;
0x00,
// UINT8 PciDeviceNumber;
0x00,
// UINT8 PciFunctionNumber;
0x00,
// UINT32 PciFlags;
0x00000000,
// UINT8 PciSegment;
0x00,
// UINT32 Reserved3;
EFI_ACPI_RESERVED_DWORD
};
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Spcr;

145
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Spi.asl
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@@ -1,145 +0,0 @@
/** @file
*
* Copyright (c) 2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
Device (SPI0)
{
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfeb00000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 358 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk3036-spi" },
Package () { "clock-frequency", 200000000 },
Package () { "num-cs", 2 },
}
})
}
Device (SPI1)
{
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfeb10000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 359 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk3036-spi" },
Package () { "clock-frequency", 200000000 },
Package () { "num-cs", 2 },
}
})
}
Device (SPI2)
{
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfeb20000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 360 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk3036-spi" },
Package () { "clock-frequency", 200000000 },
Package () { "num-cs", 2 },
}
})
}
Device (SPI3)
{
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfeb30000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 361 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk3036-spi" },
Package () { "clock-frequency", 200000000 },
Package () { "num-cs", 2 },
}
})
}
Device (SPI4)
{
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfecb0000, 0x1000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 362 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,rk3036-spi" },
Package () { "clock-frequency", 200000000 },
Package () { "num-cs", 2 },
}
})
}
Device (SFC0)
{
Name (_HID, "PRP0001")
Name (_UID, 3)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfe2b0000, 0x4000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 238 }
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package (2) { "compatible", "rockchip,sfc" },
Package () { "clock-frequency", 100000000 },
}
})
}

40
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Uart.asl
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@@ -1,40 +0,0 @@
/** @file
*
* [DSDT] Serial devices (UART).
*
* Copyright (c) 2021, ARM Limited. All rights reserved.
* Copyright (c) 2020, Pete Batard <pete@akeo.ie>
* Copyright (c) 2018, Andrey Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "AcpiTables.h"
Device(UAR2) {
Name (_HID, "HISI0031")
Name (_UID, 2)
Name (_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfeb50000, 0x100)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 365 }
})
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "reg-shift", 2 },
Package () { "reg-io-width", 4 },
Package () { "clock-frequency", 24000000 },
}
})
Method (_STA, 0, NotSerialized) {
Return(0x0F)
}
}

197
edk2-rockchip/Platform/Rockchip/RK3588/AcpiTables/Usb2.asl
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@@ -1,197 +0,0 @@
/** @file
* USB2 devices.
*
* Copyright (c) 2022, Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "AcpiTables.h"
// USB OHCI Host Controller
Device (OHC0) {
Name (_HID, "PRP0001")
Name (_CLS, Package() { 0x0c, 0x03, 0x10 })
Name (_UID, Zero)
Name (_CCA, Zero)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "generic-ohci" },
}
})
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xFC840000, 0x40000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 248 }
})
Return (RBUF)
}
// Name (_STA, FixedPcdGet8(PcdOhc0Status))
Device (RHUB) {
Name (_ADR, 0)
Device (PRT1) {
Name (_ADR, 1)
Name (_UPC, Package() {
0xFF, // Port is connectable
0x00, // Connector type - Type 'A'
0x00000000, // Reserved, must be zero
0x00000000 // Reserved, must be zero
})
Name (_PLD, Package (0x01) {
ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_UserVisible = 0x1,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "HORIZONTALRECTANGLE",
PLD_Ejectable = 0x1,
PLD_EjectRequired = 0x1,
)
})
} // PRT1
} // RHUB
} // OHC0
// USB EHCI Host Controller
Device (EHC0) {
Name (_HID, "PNP0D20")
Name (_UID, Zero)
Name (_CCA, Zero)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xFC800000, 0x40000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 247 }
})
Return (RBUF)
}
// Name (_STA, FixedPcdGet8(PcdEhc0Status))
Device (RHUB) {
Name (_ADR, 0)
Device (PRT1) {
Name (_ADR, 1)
Name (_UPC, Package() {
0xFF, // Port is connectable
0x00, // Connector type - Type 'A'
0x00000000, // Reserved, must be zero
0x00000000 // Reserved, must be zero
})
Name (_PLD, Package (0x01) {
ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_UserVisible = 0x1,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "HORIZONTALRECTANGLE",
PLD_Ejectable = 0x1,
PLD_EjectRequired = 0x1,
)
})
} // PRT1
} // RHUB
} // EHC0
// USB OHCI Host Controller
Device (OHC1) {
Name (_HID, "PRP0001")
Name (_CLS, Package() { 0x0c, 0x03, 0x10 })
Name (_UID, One)
Name (_CCA, Zero)
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "generic-ohci" },
}
})
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xFC8C0000, 0x40000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 251 }
})
Return (RBUF)
}
// Name (_STA, FixedPcdGet8(PcdOhc1Status))
Device (RHUB) {
Name (_ADR, 0)
Device (PRT1) {
Name (_ADR, 1)
Name (_UPC, Package() {
0xFF, // Port is connectable
0x00, // Connector type - Type 'A'
0x00000000, // Reserved, must be zero
0x00000000 // Reserved, must be zero
})
Name (_PLD, Package (0x01) {
ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_UserVisible = 0x1,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "LOWER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "HORIZONTALRECTANGLE",
PLD_Ejectable = 0x1,
PLD_EjectRequired = 0x1,
)
})
} // PRT1
} // RHUB
} // OHC1
// USB EHCI Host Controller
Device (EHC1) {
Name (_HID, "PNP0D20")
Name (_UID, One)
Name (_CCA, Zero)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xFC880000, 0x40000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 250 }
})
Return (RBUF)
}
// Name (_STA, FixedPcdGet8(PcdEhc1Status))
Device (RHUB) {
Name (_ADR, 0)
Device (PRT1) {
Name (_ADR, 1)
Name (_UPC, Package() {
0xFF, // Port is connectable
0x00, // Connector type - Type 'A'
0x00000000, // Reserved, must be zero
0x00000000 // Reserved, must be zero
})
Name (_PLD, Package (0x01) {
ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_UserVisible = 0x1,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "LOWER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "HORIZONTALRECTANGLE",
PLD_Ejectable = 0x1,
PLD_EjectRequired = 0x1,
)
})
} // PRT1
} // RHUB
} // EHC1

604
edk2-rockchip/Platform/Rockchip/RK3588/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.c
View File

@@ -1,604 +0,0 @@
/** @file
This module install ACPI Boot Graphics Resource Table (BGRT).
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016, Microsoft Corporation<BR>
Copyright (c) 2022 Rockchip Electronics Co. Ltd.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <IndustryStandard/Acpi.h>
#include <Protocol/AcpiTable.h>
#include <Protocol/GraphicsOutput.h>
#include <Protocol/BootLogo.h>
#include <Protocol/BootLogo2.h>
#include <Guid/EventGroup.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/SafeIntLib.h>
#include <Library/BmpSupportLib.h>
/**
Update information of logo image drawn on screen.
@param[in] This The pointer to the Boot Logo protocol 2 instance.
@param[in] BltBuffer The BLT buffer for logo drawn on screen. If BltBuffer
is set to NULL, it indicates that logo image is no
longer on the screen.
@param[in] DestinationX X coordinate of destination for the BltBuffer.
@param[in] DestinationY Y coordinate of destination for the BltBuffer.
@param[in] Width Width of rectangle in BltBuffer in pixels.
@param[in] Height Hight of rectangle in BltBuffer in pixels.
@retval EFI_SUCCESS The boot logo information was updated.
@retval EFI_INVALID_PARAMETER One of the parameters has an invalid value.
@retval EFI_OUT_OF_RESOURCES The logo information was not updated due to
insufficient memory resources.
**/
EFI_STATUS
EFIAPI
SetBootLogo (
IN EFI_BOOT_LOGO_PROTOCOL *This,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer OPTIONAL,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height
);
/**
Update information of logo image drawn on screen.
@param[in] This The pointer to the Boot Logo protocol 2 instance.
@param[in] BltBuffer The BLT buffer for logo drawn on screen. If BltBuffer
is set to NULL, it indicates that logo image is no
longer on the screen.
@param[in] DestinationX X coordinate of destination for the BltBuffer.
@param[in] DestinationY Y coordinate of destination for the BltBuffer.
@param[in] Width Width of rectangle in BltBuffer in pixels.
@param[in] Height Hight of rectangle in BltBuffer in pixels.
@retval EFI_SUCCESS The boot logo information was updated.
@retval EFI_INVALID_PARAMETER One of the parameters has an invalid value.
@retval EFI_OUT_OF_RESOURCES The logo information was not updated due to
insufficient memory resources.
**/
EFI_STATUS
EFIAPI
SetBootLogo2 (
IN EDKII_BOOT_LOGO2_PROTOCOL *This,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer OPTIONAL,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height
);
/**
Get the location of the boot logo on the screen.
@param[in] This The pointer to the Boot Logo Protocol 2 instance
@param[out] BltBuffer Returns pointer to the GOP BLT buffer that was
previously registered with SetBootLogo2(). The
buffer returned must not be modified or freed.
@param[out] DestinationX Returns the X start position of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@param[out] DestinationY Returns the Y start position of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@param[out] Width Returns the width of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@param[out] Height Returns the height of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@retval EFI_SUCCESS The location of the boot logo was returned.
@retval EFI_NOT_READY The boot logo has not been set.
@retval EFI_INVALID_PARAMETER BltBuffer is NULL.
@retval EFI_INVALID_PARAMETER DestinationX is NULL.
@retval EFI_INVALID_PARAMETER DestinationY is NULL.
@retval EFI_INVALID_PARAMETER Width is NULL.
@retval EFI_INVALID_PARAMETER Height is NULL.
**/
EFI_STATUS
EFIAPI
GetBootLogo2 (
IN EDKII_BOOT_LOGO2_PROTOCOL *This,
OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL **BltBuffer,
OUT UINTN *DestinationX,
OUT UINTN *DestinationY,
OUT UINTN *Width,
OUT UINTN *Height
);
//
// Boot Logo Protocol Handle
//
EFI_HANDLE mBootLogoHandle = NULL;
//
// Boot Logo Protocol Instance
//
EFI_BOOT_LOGO_PROTOCOL mBootLogoProtocolTemplate = {
SetBootLogo
};
///
/// Boot Logo 2 Protocol instance
///
EDKII_BOOT_LOGO2_PROTOCOL mBootLogo2ProtocolTemplate = {
SetBootLogo2,
GetBootLogo2
};
EFI_EVENT mBootGraphicsReadyToBootEvent;
UINTN mBootGraphicsResourceTableKey = 0;
BOOLEAN mIsLogoValid = FALSE;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL *mLogoBltBuffer = NULL;
UINTN mLogoDestX = 0;
UINTN mLogoDestY = 0;
UINTN mLogoWidth = 0;
UINTN mLogoHeight = 0;
BOOLEAN mAcpiBgrtInstalled = FALSE;
BOOLEAN mAcpiBgrtStatusChanged = FALSE;
BOOLEAN mAcpiBgrtBufferChanged = FALSE;
//
// ACPI Boot Graphics Resource Table template
//
EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE mBootGraphicsResourceTableTemplate = {
{
EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE,
sizeof (EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE),
EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION, // Revision
0x00, // Checksum will be updated at runtime
//
// It is expected that these values will be updated at EntryPoint.
//
{0x00}, // OEM ID is a 6 bytes long field
0x00, // OEM Table ID(8 bytes long)
0x00, // OEM Revision
0x00, // Creator ID
0x00, // Creator Revision
},
EFI_ACPI_5_0_BGRT_VERSION, // Version
EFI_ACPI_5_0_BGRT_STATUS_VALID, // Status
EFI_ACPI_5_0_BGRT_IMAGE_TYPE_BMP, // Image Type
0, // Image Address
0, // Image Offset X
0 // Image Offset Y
};
/**
Update information of logo image drawn on screen.
@param This The pointer to the Boot Logo protocol instance.
@param BltBuffer The BLT buffer for logo drawn on screen. If BltBuffer
is set to NULL, it indicates that logo image is no
longer on the screen.
@param DestinationX X coordinate of destination for the BltBuffer.
@param DestinationY Y coordinate of destination for the BltBuffer.
@param Width Width of rectangle in BltBuffer in pixels.
@param Height Hight of rectangle in BltBuffer in pixels.
@retval EFI_SUCCESS The boot logo information was updated.
@retval EFI_INVALID_PARAMETER One of the parameters has an invalid value.
@retval EFI_OUT_OF_RESOURCES The logo information was not updated due to
insufficient memory resources.
**/
EFI_STATUS
EFIAPI
SetBootLogo (
IN EFI_BOOT_LOGO_PROTOCOL *This,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer OPTIONAL,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height
)
{
//
// Call same service in Boot Logo 2 Protocol
//
return SetBootLogo2 (
&mBootLogo2ProtocolTemplate,
BltBuffer,
DestinationX,
DestinationY,
Width,
Height
);
}
/**
Update information of logo image drawn on screen.
@param[in] This The pointer to the Boot Logo protocol 2 instance.
@param[in] BltBuffer The BLT buffer for logo drawn on screen. If BltBuffer
is set to NULL, it indicates that logo image is no
longer on the screen.
@param[in] DestinationX X coordinate of destination for the BltBuffer.
@param[in] DestinationY Y coordinate of destination for the BltBuffer.
@param[in] Width Width of rectangle in BltBuffer in pixels.
@param[in] Height Hight of rectangle in BltBuffer in pixels.
@retval EFI_SUCCESS The boot logo information was updated.
@retval EFI_INVALID_PARAMETER One of the parameters has an invalid value.
@retval EFI_OUT_OF_RESOURCES The logo information was not updated due to
insufficient memory resources.
**/
EFI_STATUS
EFIAPI
SetBootLogo2 (
IN EDKII_BOOT_LOGO2_PROTOCOL *This,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer OPTIONAL,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height
)
{
EFI_STATUS Status;
UINTN BufferSize;
UINT32 Result32;
if (BltBuffer == NULL) {
mIsLogoValid = FALSE;
mAcpiBgrtStatusChanged = TRUE;
return EFI_SUCCESS;
}
//
// Width and height are not allowed to be zero.
//
if (Width == 0 || Height == 0) {
return EFI_INVALID_PARAMETER;
}
//
// Verify destination, width, and height do not overflow 32-bit values.
// The Boot Graphics Resource Table only has 32-bit fields for these values.
//
Status = SafeUintnToUint32 (DestinationX, &Result32);
if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;
}
Status = SafeUintnToUint32 (DestinationY, &Result32);
if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;
}
Status = SafeUintnToUint32 (Width, &Result32);
if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;
}
Status = SafeUintnToUint32 (Height, &Result32);
if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;
}
//
// Ensure the Height * Width * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) does
// not overflow UINTN
//
Status = SafeUintnMult (
Width,
Height,
&BufferSize
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
Status = SafeUintnMult (
BufferSize,
sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL),
&BufferSize
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
//
// Update state
//
mAcpiBgrtBufferChanged = TRUE;
//
// Free old logo buffer
//
if (mLogoBltBuffer != NULL) {
FreePool (mLogoBltBuffer);
mLogoBltBuffer = NULL;
}
//
// Allocate new logo buffer
//
mLogoBltBuffer = AllocateCopyPool (BufferSize, BltBuffer);
if (mLogoBltBuffer == NULL) {
return EFI_OUT_OF_RESOURCES;
}
mLogoDestX = DestinationX;
mLogoDestY = DestinationY;
mLogoWidth = Width;
mLogoHeight = Height;
mIsLogoValid = TRUE;
return EFI_SUCCESS;
}
/**
Get the location of the boot logo on the screen.
@param[in] This The pointer to the Boot Logo Protocol 2 instance
@param[out] BltBuffer Returns pointer to the GOP BLT buffer that was
previously registered with SetBootLogo2(). The
buffer returned must not be modified or freed.
@param[out] DestinationX Returns the X start position of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@param[out] DestinationY Returns the Y start position of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@param[out] Width Returns the width of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@param[out] Height Returns the height of the GOP BLT buffer
that was previously registered with SetBootLogo2().
@retval EFI_SUCCESS The location of the boot logo was returned.
@retval EFI_NOT_READY The boot logo has not been set.
@retval EFI_INVALID_PARAMETER BltBuffer is NULL.
@retval EFI_INVALID_PARAMETER DestinationX is NULL.
@retval EFI_INVALID_PARAMETER DestinationY is NULL.
@retval EFI_INVALID_PARAMETER Width is NULL.
@retval EFI_INVALID_PARAMETER Height is NULL.
**/
EFI_STATUS
EFIAPI
GetBootLogo2 (
IN EDKII_BOOT_LOGO2_PROTOCOL *This,
OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL **BltBuffer,
OUT UINTN *DestinationX,
OUT UINTN *DestinationY,
OUT UINTN *Width,
OUT UINTN *Height
)
{
//
// If the boot logo has not been set with SetBootLogo() or SetBootLogo() was
// called with a NULL BltBuffer then the boot logo is not valid and
// EFI_NOT_READY is returned.
//
if (mLogoBltBuffer == NULL) {
DEBUG ((DEBUG_ERROR, "Request to get boot logo location before boot logo has been set.\n"));
return EFI_NOT_READY;
}
//
// Make sure none of the boot logo location parameters are NULL.
//
if (BltBuffer == NULL || DestinationX == NULL || DestinationY == NULL ||
Width == NULL || Height == NULL) {
return EFI_INVALID_PARAMETER;
}
//
// Boot logo is valid. Return values from module globals.
//
*BltBuffer = mLogoBltBuffer;
*DestinationX = mLogoDestX;
*DestinationY = mLogoDestY;
*Width = mLogoWidth;
*Height = mLogoHeight;
return EFI_SUCCESS;
}
/**
Notify function for event group EFI_EVENT_GROUP_READY_TO_BOOT. This is used to
install the Boot Graphics Resource Table.
@param[in] Event The Event that is being processed.
@param[in] Context The Event Context.
**/
VOID
EFIAPI
BgrtReadyToBootEventNotify (
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_STATUS Status;
EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol;
VOID *ImageBuffer;
UINT32 BmpSize;
//
// Get ACPI Table protocol.
//
Status = gBS->LocateProtocol (
&gEfiAcpiTableProtocolGuid,
NULL,
(VOID **) &AcpiTableProtocol
);
if (EFI_ERROR (Status)) {
return;
}
//
// Check whether Boot Graphics Resource Table is already installed.
//
if (mAcpiBgrtInstalled) {
if (!mAcpiBgrtStatusChanged && !mAcpiBgrtBufferChanged) {
//
// Nothing has changed
//
return;
} else {
//
// If BGRT data change happens, then uninstall orignal AcpiTable first
//
Status = AcpiTableProtocol->UninstallAcpiTable (
AcpiTableProtocol,
mBootGraphicsResourceTableKey
);
if (EFI_ERROR (Status)) {
return;
}
}
} else {
//
// Check whether Logo exists
//
if (mLogoBltBuffer == NULL) {
return;
}
}
if (mAcpiBgrtBufferChanged) {
//
// Free the old BMP image buffer
//
ImageBuffer = (UINT8 *)(UINTN)mBootGraphicsResourceTableTemplate.ImageAddress;
if (ImageBuffer != NULL) {
FreePool (ImageBuffer);
}
//
// Convert GOP Blt buffer to BMP image. Pass in ImageBuffer set to NULL
// so the BMP image is allocated by TranslateGopBltToBmp().
//
ImageBuffer = NULL;
Status = TranslateGopBltToBmp (
mLogoBltBuffer,
(UINT32)mLogoHeight,
(UINT32)mLogoWidth,
&ImageBuffer,
&BmpSize
);
if (EFI_ERROR (Status)) {
return;
}
//
// Free the logo buffer
//
FreePool (mLogoBltBuffer);
mLogoBltBuffer = NULL;
//
// Update BMP image fields of the Boot Graphics Resource Table
//
mBootGraphicsResourceTableTemplate.ImageAddress = (UINT64)(UINTN)ImageBuffer;
mBootGraphicsResourceTableTemplate.ImageOffsetX = (UINT32)mLogoDestX;
mBootGraphicsResourceTableTemplate.ImageOffsetY = (UINT32)mLogoDestY;
}
//
// Update Status field of Boot Graphics Resource Table
//
if (mIsLogoValid) {
mBootGraphicsResourceTableTemplate.Status = EFI_ACPI_5_0_BGRT_STATUS_VALID;
} else {
mBootGraphicsResourceTableTemplate.Status = EFI_ACPI_5_0_BGRT_STATUS_INVALID;
}
//
// Update Checksum of Boot Graphics Resource Table
//
mBootGraphicsResourceTableTemplate.Header.Checksum = 0;
mBootGraphicsResourceTableTemplate.Header.Checksum =
CalculateCheckSum8 (
(UINT8 *)&mBootGraphicsResourceTableTemplate,
sizeof (EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE)
);
//
// Publish Boot Graphics Resource Table.
//
Status = AcpiTableProtocol->InstallAcpiTable (
AcpiTableProtocol,
&mBootGraphicsResourceTableTemplate,
sizeof (EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE),
&mBootGraphicsResourceTableKey
);
if (EFI_ERROR (Status)) {
return;
}
mAcpiBgrtInstalled = TRUE;
mAcpiBgrtStatusChanged = FALSE;
mAcpiBgrtBufferChanged = FALSE;
}
/**
The module Entry Point of the Boot Graphics Resource Table DXE driver.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval Other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
BootGraphicsDxeEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_ACPI_DESCRIPTION_HEADER *Header;
//
// Update Header fields of Boot Graphics Resource Table from PCDs
//
Header = &mBootGraphicsResourceTableTemplate.Header;
ZeroMem (Header->OemId, sizeof (Header->OemId));
CopyMem (
Header->OemId,
PcdGetPtr (PcdAcpiDefaultOemId),
MIN (PcdGetSize (PcdAcpiDefaultOemId), sizeof (Header->OemId))
);
WriteUnaligned64 (&Header->OemTableId, PcdGet64 (PcdAcpiDefaultOemTableId));
Header->OemRevision = PcdGet32 (PcdAcpiDefaultOemRevision);
Header->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId);
Header->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision);
//
// Install Boot Logo and Boot Logo 2 Protocols.
//
Status = gBS->InstallMultipleProtocolInterfaces (
&mBootLogoHandle,
&gEfiBootLogoProtocolGuid,
&mBootLogoProtocolTemplate,
&gEdkiiBootLogo2ProtocolGuid,
&mBootLogo2ProtocolTemplate,
NULL
);
ASSERT_EFI_ERROR (Status);
//
// Register notify function to install BGRT on ReadyToBoot Event.
//
Status = gBS->CreateEventEx (
EVT_NOTIFY_SIGNAL,
TPL_CALLBACK,
BgrtReadyToBootEventNotify,
NULL,
&gEfiEventReadyToBootGuid,
&mBootGraphicsReadyToBootEvent
);
ASSERT_EFI_ERROR (Status);
return Status;
}

62
edk2-rockchip/Platform/Rockchip/RK3588/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
View File

@@ -1,62 +0,0 @@
## @file
# This module install ACPI Boot Graphics Resource Table (BGRT).
#
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2016, Microsoft Corporation<BR>
# Copyright (c) 2022 Rockchip Electronics Co. Ltd.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BootGraphicsResourceTableDxe
MODULE_UNI_FILE = BootGraphicsResourceTableDxe.uni
FILE_GUID = df89e2ae-8e33-11ec-bd4b-f42a7dcb925d
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = BootGraphicsDxeEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
BootGraphicsResourceTableDxe.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
[LibraryClasses]
UefiDriverEntryPoint
BaseLib
BaseMemoryLib
MemoryAllocationLib
UefiLib
UefiBootServicesTableLib
DebugLib
PcdLib
SafeIntLib
BmpSupportLib
[Protocols]
gEfiAcpiTableProtocolGuid ## CONSUMES
gEfiBootLogoProtocolGuid ## PRODUCES
gEdkiiBootLogo2ProtocolGuid ## PRODUCES
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision ## CONSUMES
[Guids]
gEfiEventReadyToBootGuid ## CONSUMES ## Event
[UserExtensions.TianoCore."ExtraFiles"]
BootGraphicsResourceTableDxeExtra.uni

20
edk2-rockchip/Platform/Rockchip/RK3588/Include/ArmPlatform.h
View File

@@ -1,20 +0,0 @@
/** @file
*
* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef __PLATFORM_H__
#define __PLATFORM_H__
//
// We don't care about this value, but the PL031 driver depends on the macro
// to exist: it will pass it on to our ArmPlatformSysConfigLib:ConfigGet()
// function, which just returns EFI_UNSUPPORTED.
//
//
#define SYS_CFG_RTC 0
#endif /* __PLATFORM_H__ */

111
edk2-rockchip/Platform/Rockchip/RK3588/Library/RK3588Lib/RK3588.c
View File

@@ -1,111 +0,0 @@
/** @file
*
* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Ppi/ArmMpCoreInfo.h>
#include <Soc.h>
ARM_CORE_INFO mRK3588InfoTable[] = {
{
// Cluster 0, Core 0
0x0, 0x0,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 1
0x0, 0x1,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 2
0x0, 0x2,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
{
// Cluster 0, Core 3
0x0, 0x3,
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(UINT64)0xFFFFFFFF
},
};
/**
Return the current Boot Mode
This function returns the boot reason on the platform
@return Return the current Boot Mode of the platform
**/
EFI_BOOT_MODE
ArmPlatformGetBootMode (
VOID
)
{
return BOOT_WITH_FULL_CONFIGURATION;
}
/**
Initialize controllers that must setup in the normal world
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
in the PEI phase.
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
return RETURN_SUCCESS;
}
EFI_STATUS
PrePeiCoreGetMpCoreInfo (
OUT UINTN *CoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
)
{
// Only support one cluster
*CoreCount = sizeof(mRK3588InfoTable) / sizeof(ARM_CORE_INFO);
*ArmCoreTable = mRK3588InfoTable;
return EFI_SUCCESS;
}
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&mArmMpCoreInfoPpiGuid,
&mMpCoreInfoPpi
}
};
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
*PpiListSize = sizeof(gPlatformPpiTable);
*PpiList = gPlatformPpiTable;
}

43
edk2-rockchip/Platform/Rockchip/RK3588/Library/RK3588Lib/RK3588Helper.S
View File

@@ -1,43 +0,0 @@
#
# Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
#include <AsmMacroIoLibV8.h>
#include <Library/ArmLib.h>
ASM_FUNC(ArmPlatformPeiBootAction)
ret
//UINTN
//ArmPlatformGetCorePosition (
// IN UINTN MpId
// );
// With this function: CorePos = (ClusterId * 4) + CoreId
ASM_FUNC(ArmPlatformGetCorePosition)
and x1, x0, #ARM_CORE_MASK
and x0, x0, #ARM_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
//UINTN
//ArmPlatformGetPrimaryCoreMpId (
// VOID
// );
ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
MOV32 (w0, FixedPcdGet32(PcdArmPrimaryCore))
ret
//UINTN
//ArmPlatformIsPrimaryCore (
// IN UINTN MpId
// );
ASM_FUNC(ArmPlatformIsPrimaryCore)
MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCoreMask))
and x0, x0, x1
MOV32 (w1, FixedPcdGet32(PcdArmPrimaryCore))
cmp w0, w1
cset x0, eq
ret

44
edk2-rockchip/Platform/Rockchip/RK3588/Library/RK3588Lib/RK3588Lib.inf
View File

@@ -1,44 +0,0 @@
#
# Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RK3588Lib
FILE_GUID = e3984c9a-45eb-11ec-9726-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformLib
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
[Sources.common]
RK3588.c
RK3588Mem.c
[Sources.AARCH64]
RK3588Helper.S
[FixedPcd]
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
gRK3588TokenSpaceGuid.PcdTotalMemorySize

277
edk2-rockchip/Platform/Rockchip/RK3588/Library/RK3588Lib/RK3588Mem.c
View File

@@ -1,277 +0,0 @@
/** @file
*
* Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Soc.h>
// The total number of descriptors, including the final "end-of-table" descriptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
#define RK3588_EXTRA_SYSTEM_MEMORY_BASE (FixedPcdGet64(PcdLcdDdrFrameBufferBase) + FixedPcdGet64(PcdLcdDdrFrameBufferSize))
#define RK3588_EXTRA_SYSTEM_MEMORY_SIZE 0xA0000000
#define RK3588_DISPLAY_FB_BASE (FixedPcdGet64(PcdLcdDdrFrameBufferBase))
#define RK3588_DISPLAY_FB_SIZE (FixedPcdGet64(PcdLcdDdrFrameBufferSize))
STATIC struct RK3588ReservedMemory {
EFI_PHYSICAL_ADDRESS Offset;
EFI_PHYSICAL_ADDRESS Size;
} RK3588ReservedMemoryBuffer [] = {
{ 0x00000000, 0x00200000 }, // ATF
{ 0x08400000, 0x01000000 }, // TEE OS
{ 0xF0000000, 0x10000000 }, // REG
{ 0x180000000, 0x00001000 }, // for grub test
};
STATIC
UINT64
EFIAPI
RK3588InitMemorySize (
IN VOID
)
{
return SIZE_4GB;
}
/*++
Routine Description:
Remove the reserved region from a System Memory Hob that covers it.
Arguments:
FileHandle - Handle of the file being invoked.
PeiServices - Describes the list of possible PEI Services.
--*/
STATIC
VOID
ReserveMemoryRegion (
IN EFI_PHYSICAL_ADDRESS ReservedRegionBase,
IN UINT32 ReservedRegionSize
)
{
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
EFI_PHYSICAL_ADDRESS ReservedRegionTop;
EFI_PHYSICAL_ADDRESS ResourceTop;
EFI_PEI_HOB_POINTERS NextHob;
UINT64 ResourceLength;
ReservedRegionTop = ReservedRegionBase + ReservedRegionSize;
//
// Search for System Memory Hob that covers the reserved region,
// and punch a hole in it
//
for (NextHob.Raw = GetHobList ();
NextHob.Raw != NULL;
NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
NextHob.Raw)) {
if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
(ReservedRegionBase >= NextHob.ResourceDescriptor->PhysicalStart) &&
(ReservedRegionTop <= NextHob.ResourceDescriptor->PhysicalStart +
NextHob.ResourceDescriptor->ResourceLength))
{
ResourceAttributes = NextHob.ResourceDescriptor->ResourceAttribute;
ResourceLength = NextHob.ResourceDescriptor->ResourceLength;
ResourceTop = NextHob.ResourceDescriptor->PhysicalStart + ResourceLength;
if (ReservedRegionBase == NextHob.ResourceDescriptor->PhysicalStart) {
//
// This region starts right at the start of the reserved region, so we
// can simply move its start pointer and reduce its length by the same
// value
//
NextHob.ResourceDescriptor->PhysicalStart += ReservedRegionSize;
NextHob.ResourceDescriptor->ResourceLength -= ReservedRegionSize;
} else if ((NextHob.ResourceDescriptor->PhysicalStart +
NextHob.ResourceDescriptor->ResourceLength) ==
ReservedRegionTop) {
//
// This region ends right at the end of the reserved region, so we
// can simply reduce its length by the size of the region.
//
NextHob.ResourceDescriptor->ResourceLength -= ReservedRegionSize;
} else {
//
// This region covers the reserved region. So split it into two regions,
// each one touching the reserved region at either end, but not covering
// it.
//
NextHob.ResourceDescriptor->ResourceLength =
ReservedRegionBase - NextHob.ResourceDescriptor->PhysicalStart;
// Create the System Memory HOB for the remaining region (top of the FD)
BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
ReservedRegionTop,
ResourceTop - ReservedRegionTop);
}
//
// Reserve the memory space.
//
BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED,
0,
ReservedRegionBase,
ReservedRegionSize);
break;
}
NextHob.Raw = GET_NEXT_HOB (NextHob);
}
}
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
Virtual Memory mapping. This array must be ended by a zero-filled
entry
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
UINTN Index = 0, Count;
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
UINT64 MemorySize, AdditionalMemorySize;
MemorySize = PcdGet64 (PcdTotalMemorySize);
if (MemorySize == 0)
MemorySize = RK3588InitMemorySize ();
ResourceAttributes = (
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED
);
// Create initial Base Hob for system memory.
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
PcdGet64 (PcdSystemMemoryBase),
PcdGet64 (PcdSystemMemorySize)
);
if (MemorySize >= PcdGet64 (PcdSystemMemorySize)) {
ResourceAttributes =
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED;
AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
if (MemorySize > RK3588_PERIPH_BASE)
AdditionalMemorySize = RK3588_PERIPH_BASE - PcdGet64 (PcdSystemMemorySize);
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
PcdGet64 (PcdSystemMemorySize),
AdditionalMemorySize);
if (MemorySize > SIZE_4GB) {
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
SIZE_4GB,
MemorySize - SIZE_4GB);
}
}
Count = sizeof (RK3588ReservedMemoryBuffer) / sizeof (struct RK3588ReservedMemory);
for (Index = 0; Index < Count; Index++)
ReserveMemoryRegion(RK3588ReservedMemoryBuffer[Index].Offset, RK3588ReservedMemoryBuffer[Index].Size);
ASSERT (VirtualMemoryMap != NULL);
VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
if (VirtualMemoryTable == NULL) {
return;
}
CacheAttributes = DDR_ATTRIBUTES_CACHED;
Index = 0;
// RK3588 SOC peripherals
VirtualMemoryTable[Index].PhysicalBase = RK3588_PERIPH_BASE;
VirtualMemoryTable[Index].VirtualBase = RK3588_PERIPH_BASE;
VirtualMemoryTable[Index].Length = RK3588_PERIPH_SZ;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE;
//PCIe 64 BAR space
VirtualMemoryTable[++Index].PhysicalBase = 0x940000000;
VirtualMemoryTable[Index].VirtualBase = 0x940000000;
VirtualMemoryTable[Index].Length = 0x100000000 + 0x1400000;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE;
// DDR - predefined 1GB size
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// If DDR capacity is 2GB size, append a new entry to fill the gap.
if (MemorySize >= PcdGet64 (PcdSystemMemorySize)) {
AdditionalMemorySize = MemorySize - PcdGet64 (PcdSystemMemorySize);
if (MemorySize > RK3588_PERIPH_BASE)
AdditionalMemorySize = RK3588_PERIPH_BASE - PcdGet64 (PcdSystemMemorySize);
if (AdditionalMemorySize >= SIZE_1GB) {
VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Length = AdditionalMemorySize;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
}
if (MemorySize > SIZE_4GB) {
VirtualMemoryTable[++Index].PhysicalBase = SIZE_4GB;
VirtualMemoryTable[Index].VirtualBase = SIZE_4GB;
VirtualMemoryTable[Index].Length = MemorySize - SIZE_4GB;
VirtualMemoryTable[Index].Attributes = CacheAttributes;
}
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
VirtualMemoryTable[Index].Length = 0;
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
*VirtualMemoryMap = VirtualMemoryTable;
}

34
edk2-rockchip/Platform/Rockchip/RK3588/Library/RockchipPlatformLib/CruLib.inf
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@@ -1,34 +0,0 @@
#
# Copyright (c) 2021, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RockchipPlatformLib
FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RockchipPlatformLib
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
[Sources.common]
RK3568CruLib.c
[Sources.AARCH64]
[FixedPcd]

395
edk2-rockchip/Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RK3588CruLib.c
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@@ -1,395 +0,0 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include "Include/Library/CruLib.h"
#include <Library/DebugLib.h>
/** @addtogroup RK_HAL_Driver
* @{
*/
/** @addtogroup CRU
* @{
*/
/** @defgroup CRU_Private_Definition Private Definition
* @{
*/
/********************* Private MACRO Definition ******************************/
/********************* Private Structure Definition **************************/
static struct PLL_CONFIG PLL_TABLE[] = {
/* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */
RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
{ /* sentinel */ },
};
static struct PLL_SETUP LPLL = {
.conOffset0 = &(DSUCRU->LPLL_CON[0]),
.conOffset1 = &(DSUCRU->LPLL_CON[1]),
.conOffset2 = &(DSUCRU->LPLL_CON[2]),
.conOffset3 = &(DSUCRU->LPLL_CON[3]),
.conOffset6 = &(DSUCRU->LPLL_CON[6]),
.modeOffset = &(DSUCRU->MODE_CON00),
.modeShift = 0,
.lockShift = 15,
.modeMask = 0x3,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP B0PLL = {
.conOffset0 = &(BIGCORE0CRU->B0PLL_CON[0]),
.conOffset1 = &(BIGCORE0CRU->B0PLL_CON[1]),
.conOffset2 = &(BIGCORE0CRU->B0PLL_CON[2]),
.conOffset3 = &(BIGCORE0CRU->B0PLL_CON[3]),
.conOffset6 = &(BIGCORE0CRU->B0PLL_CON[6]),
.modeOffset = &(BIGCORE0CRU->MODE_CON00),
.modeShift = 0,
.lockShift = 15,
.modeMask = 0x3,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP B1PLL = {
.conOffset0 = &(BIGCORE1CRU->B1PLL_CON[0]),
.conOffset1 = &(BIGCORE1CRU->B1PLL_CON[1]),
.conOffset2 = &(BIGCORE1CRU->B1PLL_CON[2]),
.conOffset3 = &(BIGCORE1CRU->B1PLL_CON[3]),
.conOffset6 = &(BIGCORE1CRU->B1PLL_CON[6]),
.modeOffset = &(BIGCORE1CRU->MODE_CON00),
.modeShift = 0,
.lockShift = 15,
.modeMask = 0x3,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP CPLL = {
.conOffset0 = &(CRU->CPLL_CON[0]),
.conOffset1 = &(CRU->CPLL_CON[1]),
.conOffset2 = &(CRU->CPLL_CON[2]),
.conOffset3 = &(CRU->CPLL_CON[3]),
.conOffset6 = &(CRU->CPLL_CON[6]),
.modeOffset = &(CRU->MODE_CON00),
.modeShift = 8,
.lockShift = 15,
.modeMask = 0x3 << 8,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP GPLL = {
.conOffset0 = &(CRU->GPLL_CON[0]),
.conOffset1 = &(CRU->GPLL_CON[1]),
.conOffset2 = &(CRU->GPLL_CON[2]),
.conOffset3 = &(CRU->GPLL_CON[3]),
.conOffset6 = &(CRU->GPLL_CON[6]),
.modeOffset = &(CRU->MODE_CON00),
.modeShift = 2,
.lockShift = 15,
.modeMask = 0x3 << 2,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP NPLL = {
.conOffset0 = &(CRU->NPLL_CON[0]),
.conOffset1 = &(CRU->NPLL_CON[1]),
.conOffset2 = &(CRU->NPLL_CON[2]),
.conOffset3 = &(CRU->NPLL_CON[3]),
.conOffset6 = &(CRU->NPLL_CON[6]),
.modeOffset = &(CRU->MODE_CON00),
.modeShift = 0,
.lockShift = 15,
.modeMask = 0x3 << 0,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP V0PLL = {
.conOffset0 = &(CRU->V0PLL_CON[0]),
.conOffset1 = &(CRU->V0PLL_CON[1]),
.conOffset2 = &(CRU->V0PLL_CON[2]),
.conOffset3 = &(CRU->V0PLL_CON[3]),
.conOffset6 = &(CRU->V0PLL_CON[6]),
.modeOffset = &(CRU->MODE_CON00),
.modeShift = 4,
.lockShift = 15,
.modeMask = 0x3 << 4,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP AUPLL = {
.conOffset0 = &(CRU->AUPLL_CON[0]),
.conOffset1 = &(CRU->AUPLL_CON[1]),
.conOffset2 = &(CRU->AUPLL_CON[2]),
.conOffset3 = &(CRU->AUPLL_CON[3]),
.conOffset6 = &(CRU->AUPLL_CON[6]),
.modeOffset = &(CRU->MODE_CON00),
.modeShift = 6,
.lockShift = 15,
.modeMask = 0x3 << 6,
.rateTable = PLL_TABLE,
};
static struct PLL_SETUP PPLL = {
.conOffset0 = &(PHPTOPCRU->PPLL_CON[0]),
.conOffset1 = &(PHPTOPCRU->PPLL_CON[1]),
.conOffset2 = &(PHPTOPCRU->PPLL_CON[2]),
.conOffset3 = &(PHPTOPCRU->PPLL_CON[3]),
.conOffset6 = &(PHPTOPCRU->PPLL_CON[6]),
.lockShift = 15,
.rateTable = PLL_TABLE,
};
/********************* Private Variable Definition ***************************/
static uint32_t s_lpllFreq;
static uint32_t s_cpllFreq = 1500 * 1000 * 1000;;
static uint32_t s_gpllFreq = 1188 * 1000 * 1000;
static uint32_t s_npllFreq;
static uint32_t s_v0pllFreq;
static uint32_t s_ppllFreq;
static uint32_t s_aupllFreq;
/********************* Private Function Definition ***************************/
/** @} */
/********************* Public Function Definition ****************************/
/**
* @brief Get clk freq.
* @param clockName: CLOCK_Name id.
* @return rate.
* @attention these APIs allow direct use in the HAL layer.
*/
uint32_t
EFIAPI
HAL_CRU_ClkGetFreq(eCLOCK_Name clockName)
{
uint32_t clkMux = CLK_GET_MUX(clockName);
uint32_t clkDiv = CLK_GET_DIV(clockName);
uint32_t pRate = 0, freq;
if (!s_cpllFreq) {
s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL);
}
switch (clockName) {
case PLL_LPLL:
freq = HAL_CRU_GetPllV1Freq(&LPLL);
s_lpllFreq = freq;
return freq;
case PLL_B0PLL:
freq = HAL_CRU_GetPllV1Freq(&B0PLL);
return freq;
case PLL_B1PLL:
freq = HAL_CRU_GetPllV1Freq(&B1PLL);
return freq;
case PLL_CPLL:
freq = HAL_CRU_GetPllV1Freq(&CPLL);
s_cpllFreq = freq;
return freq;
case PLL_NPLL:
freq = HAL_CRU_GetPllV1Freq(&NPLL);
s_npllFreq = freq;
return freq;
case PLL_V0PLL:
freq = HAL_CRU_GetPllV1Freq(&V0PLL);
s_v0pllFreq = freq;
return freq;
case PLL_AUPLL:
freq = HAL_CRU_GetPllV1Freq(&AUPLL);
s_aupllFreq = freq;
return freq;
case PLL_PPLL:
freq = HAL_CRU_GetPllV1Freq(&PPLL);
s_ppllFreq = freq;
return freq;
case PLL_GPLL:
freq = HAL_CRU_GetPllV1Freq(&GPLL);
s_gpllFreq = freq;
return s_gpllFreq;
case CCLK_EMMC:
case SCLK_SFC:
case CCLK_SRC_SDIO:
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
pRate = s_gpllFreq;
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
pRate = s_cpllFreq;
} else if (HAL_CRU_ClkGetMux(clkMux) == 2) {
pRate = PLL_INPUT_OSC_RATE;
}
return pRate / HAL_CRU_ClkGetDiv(clkDiv) ;
case BCLK_EMMC:
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
pRate = s_gpllFreq;
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
pRate = s_cpllFreq;
}
return pRate / HAL_CRU_ClkGetDiv(clkDiv) ;
case CLK_REF_PIPE_PHY0:
case CLK_REF_PIPE_PHY1:
case CLK_REF_PIPE_PHY2:
if (HAL_CRU_ClkGetMux(clkMux) == 0) {
return PLL_INPUT_OSC_RATE;
} else if (HAL_CRU_ClkGetMux(clkMux) == 1) {
return s_ppllFreq / HAL_CRU_ClkGetDiv(clkDiv) ;
}
default:
break;
}
if ((clkMux == 0) && (clkDiv == 0)) {
return 0;
}
if (clkDiv) {
freq = pRate / (HAL_CRU_ClkGetDiv(clkDiv));
} else {
freq = pRate;
}
return freq;
}
/**
* @brief Set clk freq.
* @param clockName: CLOCK_Name id.
* @param rate: clk rate.
* @return HAL_Status.
* @attention these APIs allow direct use in the HAL layer.
*/
HAL_Status
EFIAPI
HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate)
{
HAL_Status error = HAL_OK;
uint32_t clkMux = CLK_GET_MUX(clockName);
uint32_t clkDiv = CLK_GET_DIV(clockName);
uint32_t mux = 0, div = 0, pRate = 0;
if (!s_cpllFreq) {
s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL);
}
switch (clockName) {
case PLL_LPLL:
error = HAL_CRU_SetPllV1Freq(&LPLL, rate);
s_lpllFreq = HAL_CRU_GetPllV1Freq(&LPLL);
return error;
case PLL_B0PLL:
error = HAL_CRU_SetPllV1Freq(&B0PLL, rate);
return error;
case PLL_B1PLL:
error = HAL_CRU_SetPllV1Freq(&B1PLL, rate);
return error;
case PLL_CPLL:
error = HAL_CRU_SetPllV1Freq(&CPLL, rate);
s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL);
return error;
case PLL_PPLL:
error = HAL_CRU_SetPllV1Freq(&PPLL, rate);
s_ppllFreq = HAL_CRU_GetPllV1Freq(&PPLL);
return error;
case PLL_GPLL:
error = HAL_CRU_SetPllV1Freq(&GPLL, rate);
DEBUG ((DEBUG_INIT, "GPLL set rate: %d %x\n", rate, error));
s_gpllFreq = HAL_CRU_GetPllV1Freq(&GPLL);
return error;
case PLL_NPLL:
error = HAL_CRU_SetPllV1Freq(&NPLL, rate);
s_npllFreq = HAL_CRU_GetPllV1Freq(&NPLL);
return error;
case PLL_AUPLL:
error = HAL_CRU_SetPllV1Freq(&AUPLL, rate);
s_aupllFreq = HAL_CRU_GetPllV1Freq(&AUPLL);
return error;
case PLL_V0PLL:
error = HAL_CRU_SetPllV1Freq(&V0PLL, rate);
s_v0pllFreq = HAL_CRU_GetPllV1Freq(&V0PLL);
return error;
case CCLK_EMMC:
case SCLK_SFC:
case CCLK_SRC_SDIO:
if (PLL_INPUT_OSC_RATE % rate == 0) {
pRate = PLL_INPUT_OSC_RATE;
mux = 2;
} else if (s_cpllFreq % rate == 0){
pRate = s_cpllFreq;
mux = 1;
} else {
pRate = s_gpllFreq;
mux = 0;
}
break;
case BCLK_EMMC:
if (s_cpllFreq % rate == 0){
pRate = s_cpllFreq;
mux = 1;
} else {
pRate = s_gpllFreq;
mux = 0;
}
break;
case CLK_REF_PIPE_PHY0:
case CLK_REF_PIPE_PHY1:
case CLK_REF_PIPE_PHY2:
if (rate == PLL_INPUT_OSC_RATE) {
HAL_CRU_ClkSetMux(clkMux, 0);
HAL_CRU_ClkSetDiv(clkDiv, 0);
} else {
div = HAL_DIV_ROUND_UP(s_ppllFreq, rate);
HAL_CRU_ClkSetDiv(clkDiv, div);
HAL_CRU_ClkSetMux(clkMux, 1);
}
return HAL_OK;
default:
break;
}
if ((clkMux == 0) && (clkDiv == 0)) {
return HAL_INVAL;
}
div = HAL_DIV_ROUND_UP(pRate, rate);
if (clkMux) {
HAL_CRU_ClkSetMux(clkMux, mux);
}
if (clkDiv) {
HAL_CRU_ClkSetDiv(clkDiv, div);
}
return HAL_OK;
}
/** @} */
/** @} */
/** @} */

300
edk2-rockchip/Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RockchipPlatformLib.c
View File

@@ -1,300 +0,0 @@
/** @file
*
* Copyright (c) 2021, Rockchip Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/PWMLib.h>
#include <Soc.h>
void DebugPrintHex(void *buf, UINT32 width, UINT32 len)
{
UINT32 i,j;
UINT8 *p8 = (UINT8 *) buf;
UINT16 *p16 = (UINT16 *) buf;
UINT32 *p32 =(UINT32 *) buf;
j = 0;
for (i = 0; i < len; i++) {
if (j == 0) {
DebugPrint(DEBUG_ERROR, "%p + 0x%x:",buf, i * width);
}
if (width == 4) {
DebugPrint(DEBUG_ERROR, "0x%08x,", p32[i]);
} else if (width == 2) {
DebugPrint(DEBUG_ERROR, "0x%04x,", p16[i]);
} else {
DebugPrint(DEBUG_ERROR, "0x%02x,", p8[i]);
}
if (++j >= (16/width)) {
j = 0;
DebugPrint(DEBUG_ERROR, "\n","");
}
}
DebugPrint(DEBUG_ERROR, "\n","");
}
void
EFIAPI
DwEmmcDxeIoMux(void)
{
/* sdmmc0 iomux */
}
void
EFIAPI
EnableBacklight(IN BOOLEAN en) {
if (en) {
// rk3588s-evb1 pull high gpio1_a5
MmioWrite32(0xFEC20000, 0x00200020);
MmioWrite32(0xFEC20008, 0x00200020);
DEBUG ((EFI_D_WARN, "RK3588s evb1 Enable Display end \n"));
} else {
// rk3588s-evb1 pull low gpio1_a5
MmioWrite32(0xFEC20000, 0x00200000);
MmioWrite32(0xFEC20008, 0x00200020);
DEBUG ((EFI_D_WARN, "RK3588s evb1 Disabled Display end \n"));
}
}
void
EFIAPI
EnablePWM(IN BOOLEAN en) {
PWM_DATA PwmData = {
.ControllerID = PWM_CONTROLLER3,
.ChannelID = PWM_CHANNEL0,
.PeriodNs = 1000,
.DutyNs = 500,
.Polarity = 0
};
if (en) {
MmioWrite32(0xFD5F808C, 0x00F000B0);//PWM12 IOMUX
RkPwmSetConfig(&PwmData);
RkPwmEnable(&PwmData);
} else
RkPwmDisable(&PwmData);
}
void
EFIAPI
SdhciEmmcDxeIoMux(void)
{
/* sdmmc0 iomux */
BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
}
#define NS_CRU_BASE 0xFD7C0000
#define CRU_CLKSEL_CON59 0x03EC
#define CRU_CLKSEL_CON78 0x0438
void
EFIAPI
Rk806SpiIomux(void)
{
/* io mux */
//BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
//BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
}
void
EFIAPI
NorFspiIomux(void)
{
/* io mux */
MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
(((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
#define FSPI_M1
#if defined(FSPI_M0)
/*FSPI M0*/
BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
#elif defined(FSPI_M1)
/*FSPI M1*/
BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
#else
/*FSPI M2*/
BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
#endif
}
void
EFIAPI
GmacIomux (
UINT32 id
)
{
switch (id) {
case 0:
/* gmac0 iomux */
BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
BUS_IOC->GPIO2C_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
BUS_IOC->GPIO4C_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0100;
BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
break;
case 1:
/* gmac1 iomux */
break;
default:
break;
}
}
void
EFIAPI
NorFspiEnableClock (
UINT32 *CruBase
)
{
UINTN BaseAddr = (UINTN) CruBase;
MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
}
UINT32
EFIAPI
I2cGetBase (
UINT32 id
)
{
UINT32 Base = 0;
switch (id) {
case 0:
Base = 0xFD880000;
break;
case 1:
Base = 0xFEA90000;
/* io mux */
//BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
//PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
break;
case 2:
Base = 0xFEAA0000;
/* io mux */
BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
break;
case 3:
Base = 0xFEAB0000;
break;
case 4:
Base = 0xFEAC0000;
break;
case 5:
Base = 0xFEAD0000;
break;
default:
break;
}
return Base;
}
#define GPIO4_BASE 0xFEC50000
#define GPIO_SWPORT_DR_L 0x0000
#define GPIO_SWPORT_DR_H 0x0004
#define GPIO_SWPORT_DDR_L 0x0008
#define GPIO_SWPORT_DDR_H 0x000C
void
EFIAPI
UsbPortPowerEnable (void)
{
/* enable usb host vbus supply */
MmioWrite32(GPIO4_BASE + GPIO_SWPORT_DR_L, (0x0100UL << 16) | 0x0100);
MmioWrite32(GPIO4_BASE + GPIO_SWPORT_DDR_L, (0x0100UL << 16) | 0x0100);
/* enable usb otg0 vbus supply */
MmioWrite32(GPIO4_BASE + GPIO_SWPORT_DR_H, (0x0100UL << 16) | 0x0100);
MmioWrite32(GPIO4_BASE + GPIO_SWPORT_DDR_H, (0x0100UL << 16) | 0x0100);
}
void
EFIAPI
Usb2PhyResume (void)
{
MmioWrite32(0xfd5d4008, 0x20000000);
MmioWrite32(0xfd5d8008, 0x20000000);
MmioWrite32(0xfd5dc008, 0x20000000);
MmioWrite32(0xfd7f0a10, 0x07000700);
MmioWrite32(0xfd7f0a10, 0x07000000);
}
void
EFIAPI
UdPhyU3PortDisable (void)
{
/* disable U3 port */
MmioWrite32 (0xfd5ac01c, 0xf08d0089);
MmioWrite32 (0xfd5ac034, 0xf08d0089);
/* remove rx-termination */
MmioWrite32 (0xfd5c800c, 0x00030001);
MmioWrite32 (0xfd5cc00c, 0x00030001);
}
void
EFIAPI
Dwc3Force20ClkFor30Clk (UINT32 Address, BOOLEAN enable)
{
UINT32 Reg;
if (enable) {
Reg = MmioRead32(Address);
Reg |= (1 << 26);
MmioWrite32((Address), Reg);
} else {
Reg = MmioRead32(Address);
Reg &= ~(1 << 26);
MmioWrite32(Address, Reg);
}
}
void
EFIAPI
Pcie30IoInit(void)
{
/* Set reset and power IO to gpio output mode */
MmioWrite32(0xFD5F808C, 0xf << (8 + 16)); /* gpio4b6 to gpio mode -> reset */
MmioWrite32(0xFEC50008, 0x40004000); /* output */
MmioWrite32(0xFD5F8070, 0xf << (12 + 16)); /* gpio3c3 to gpio mode -> power */
MmioWrite32(0xFEC4000c, 0x80008); /* output */
}
void
EFIAPI
Pcie30PowerEn(void)
{
MmioWrite32(0xFEC40004, 0x80008); /* output high to enable power */
}
void
EFIAPI
Pcie30PeReset(BOOLEAN enable)
{
if(enable)
MmioWrite32(0xFEC50000, 0x40000000); /* output low */
else
MmioWrite32(0xFEC50000, 0x40004000); /* output high */
}

41
edk2-rockchip/Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RockchipPlatformLib.inf
View File

@@ -1,41 +0,0 @@
#
# Copyright (c) 2021, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x00010019
BASE_NAME = RockchipPlatformLib
FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = RockchipPlatformLib
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Platform/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RK3588/RK3588.dec
Silicon/Rockchip/RockchipPkg.dec
[LibraryClasses]
ArmLib
HobLib
IoLib
MemoryAllocationLib
SerialPortLib
CruLib
[Sources.common]
RockchipPlatformLib.c
RK3588CruLib.c
RockchipSdhci.c
[Sources.AARCH64]
[Pcd]
gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress
gRockchipTokenSpaceGuid.PcdI2cBusCount

163
edk2-rockchip/Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RockchipSdhci.c
View File

@@ -1,163 +0,0 @@
/** @file
*
* Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
* Copyright (c) Microsoft Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include "RockchipSdhci.h"
#include <Library/PcdLib.h>
#include <Library/TimerLib.h>
#define word32 *(volatile unsigned int *)(long)
#define word16 *(volatile unsigned short *)(long)
//#define GRF_BASE 0xFDC60000
#define NS_CRU_BASE 0xFD7C0000
#define CRU_CLKSEL_CON77 0x0434
#define CRU_GPLL_CON1 0x1C4
#define CRU_CPLL_CON1 0x1A4
#define EMMC_CLOCK_BASE (NS_CRU_BASE + CRU_CLKSEL_CON77)
#define EMMC_CLOCK_SEL(a) (((7 << 12) << 16) | (a << 12))
#define EMMC_BASE PcdGet32 (PcdSdhciDxeBaseAddress)
#define SDHCI_HOST_CTRL2 (EMMC_BASE + 0x3E)
#define SDHCI_HOST_CTRL3 (EMMC_BASE + 0x508)
#define SDHCI_EMMC_CTRL (EMMC_BASE + 0x52C)
#define DWCMSHC_CARD_IS_EMMC BIT0
#define EMMC_DLL_CTRL (EMMC_BASE + 0x800)
#define EMMC_DLL_RXCLK (EMMC_BASE + 0x804)
#define EMMC_DLL_TXCLK (EMMC_BASE + 0x808)
#define EMMC_DLL_STRBIN (EMMC_BASE + 0x80C)
#define EMMC_DLL_CMDOUT (EMMC_BASE + 0x810)
#define EMMC_DLL_STATUS0 (EMMC_BASE + 0x840)
#define EMMC_DLL_STATUS1 (EMMC_BASE + 0x844)
EFI_STATUS SdhciSetPHY(
IN UINTN Clock
)
{
UINT32 Ctrl2, Ctrl;
UINT32 status, timeout, tmp;
word32(SDHCI_EMMC_CTRL) |= (1 << 0); /* Host Controller is an eMMC card */
if (Clock < 100000000) {
word32(EMMC_DLL_CTRL) = 0;
word32(EMMC_DLL_RXCLK) = 0; /* PIO mode need set bit 29*/
word32(EMMC_DLL_TXCLK) = 0;
word32(EMMC_DLL_STRBIN) = (1 << 27) | (1 << 26) | (10 << 16);;
word32(EMMC_DLL_CMDOUT) = 0;
goto exit;
}
word32(EMMC_DLL_RXCLK) = 0;
/*Reset DLL*/
word32(EMMC_DLL_CTRL) = (0x1 << 1);
MicroSecondDelay(5);
word32(EMMC_DLL_CTRL) = 0;
/*Init DLL*/
word32(EMMC_DLL_CTRL) = (5 << 16) | (2 << 8) | 0x1;
/* Wait max 10 ms */
timeout = 10000;
while (1) {
status = word32(EMMC_DLL_STATUS0);
tmp = (status >> 8) & 0x3;
if (0x1 == tmp) /*check dll lock*/
break;
if (timeout-- > 0)
MicroSecondDelay(1);
else {
DEBUG ((DEBUG_ERROR, "%a timeout status:%x\n", __FUNCTION__, status));
return EFI_TIMEOUT;
}
}
Ctrl2 = word16(SDHCI_HOST_CTRL2) & 0x0007; /* Get Bus Speed Mode*/
if (Clock >= 200000000 && Ctrl2 == 0x7) { /*check is HS400 mode*/
word32(SDHCI_EMMC_CTRL) |= (1 << 8); /* CMD line is sampled using data strobe for HS400 mode */
word32(EMMC_DLL_RXCLK) = (1 << 27);
word32(EMMC_DLL_TXCLK) = (1 << 29) | (1 << 27) | (1 << 24) | 0x8;
word32(EMMC_DLL_STRBIN) = (1 << 27) | (1 << 24) | 0x4;
word32(EMMC_DLL_CMDOUT) = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 24) | 0x8;
/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
Ctrl = word32(SDHCI_EMMC_CTRL);
Ctrl |= DWCMSHC_CARD_IS_EMMC;
word32(SDHCI_EMMC_CTRL) = Ctrl;
}
else { /*config for HS200 mode*/
word32(EMMC_DLL_RXCLK) = (1 << 29) | (1 << 27);
word32(EMMC_DLL_TXCLK) = (1 << 27) | (1 << 24) | 0x1;
word32(EMMC_DLL_STRBIN) = 0; //max is 16
}
exit:
//DEBUG ((DEBUG_ERROR, "EMMC_DLL_CTRL :0x%x\n", word32(EMMC_DLL_CTRL)));
//DEBUG ((DEBUG_ERROR, "EMMC_DLL_RXCLK:0x%x\n", word32(EMMC_DLL_RXCLK)));
//DEBUG ((DEBUG_ERROR, "EMMC_DLL_TXCLK:0x%x\n", word32(EMMC_DLL_TXCLK)));
//DEBUG ((DEBUG_ERROR, "EMMC_DLL_STRBIN:0x%x\n", word32(EMMC_DLL_STRBIN)));
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
SdhciGetClockRate(
IN UINTN TargetFreq,
OUT UINTN *BaseFreq
)
{
UINT32 CClkEmmcSel, Div;
if (TargetFreq == 0 || BaseFreq == NULL)
return -1;
//word32(NS_CRU_BASE + CRU_GPLL_CON1) = 0x70002 << 6; //GPLL:600MHz
//word32(NS_CRU_BASE + CRU_CPLL_CON1) = 0x70002 << 6; //CPLL:750MHZ
/*GPLL:1184MHz, CPLL:750MHZ
2'b00: clk_gpll_mux
2'b01: clk_cpll_mux
2'b10: xin_osc0_func*/
if (TargetFreq >= 200000000) {
CClkEmmcSel = 0;
Div = 6;
} else if (TargetFreq >= 150000000) {
CClkEmmcSel = 0;
Div = 8;
} else if (TargetFreq >= 100000000) {
CClkEmmcSel = 0;
Div = 12;
} else if (TargetFreq >= 50000000) {
CClkEmmcSel = 0;
Div = 24;
} else if (TargetFreq >= 24000000) {
CClkEmmcSel = 2;
Div = 1;
} else { /* 375KHZ*/
CClkEmmcSel = 2;
Div = 64;
}
DEBUG((DEBUG_ERROR, "+++++SetEmmcClk: %d, %d, %d\n", TargetFreq, CClkEmmcSel, Div));
*BaseFreq = TargetFreq;
MmioWrite32(EMMC_CLOCK_BASE, ((( 0x3 << 14 )|( 0x3F << 8 )) << 16 ) |
( CClkEmmcSel << 14 ) |
(( Div - 1 ) << 8));
//DEBUG ((DEBUG_ERROR, "CRU_0X434: 0x%x\n", word32(NS_CRU_BASE + 0x0434)));
//DEBUG ((DEBUG_ERROR, "CRU_0X438: 0x%x\n", word32(NS_CRU_BASE + 0x0438)));
//DEBUG ((DEBUG_ERROR, "GPLL_CON1: 0x%x\n", word32(NS_CRU_BASE + CRU_GPLL_CON1)));
//DEBUG ((DEBUG_ERROR, "CPLL_CON1: 0x%x\n", word32(NS_CRU_BASE + CRU_CPLL_CON1)));
SdhciSetPHY(TargetFreq);
return EFI_SUCCESS;
}

29
edk2-rockchip/Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RockchipSdhci.h
View File

@@ -1,29 +0,0 @@
/** @file
*
* Copyright (c) Rockchip Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#ifndef _ROCKCHIP_SDHCI_H_
#define _ROCKCHIP_SDHCI_H_
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h>
EFI_STATUS
SdhciGetClockRate (
IN UINTN TargetFreq,
OUT UINTN *BaseFreq
);
#endif

BIN
edk2-rockchip/Platform/Rockchip/RK3588/LogoDxe/Logo.bmp
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144
edk2-rockchip/Platform/Rockchip/RK3588/LogoDxe/Logo.c
View File

@@ -1,144 +0,0 @@
/** @file
Logo DXE Driver, install Edkii Platform Logo protocol.
Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
Copyright (c) 2022 Rockchip Electronics Co. Ltd.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Protocol/HiiDatabase.h>
#include <Protocol/GraphicsOutput.h>
#include <Protocol/HiiImageEx.h>
#include <Protocol/PlatformLogo.h>
#include <Protocol/HiiPackageList.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h>
typedef struct {
EFI_IMAGE_ID ImageId;
EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
INTN OffsetX;
INTN OffsetY;
} LOGO_ENTRY;
STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
STATIC EFI_HII_HANDLE mHiiHandle;
STATIC LOGO_ENTRY mLogos[] = {
{
IMAGE_TOKEN (IMG_LOGO),
EdkiiPlatformLogoDisplayAttributeCenter,
0,
0
}
};
/**
Load a platform logo image and return its data and attributes.
@param This The pointer to this protocol instance.
@param Instance The visible image instance is found.
@param Image Points to the image.
@param Attribute The display attributes of the image returned.
@param OffsetX The X offset of the image regarding the Attribute.
@param OffsetY The Y offset of the image regarding the Attribute.
@retval EFI_SUCCESS The image was fetched successfully.
@retval EFI_NOT_FOUND The specified image could not be found.
**/
STATIC
EFI_STATUS
EFIAPI
GetImage (
IN EDKII_PLATFORM_LOGO_PROTOCOL *This,
IN OUT UINT32 *Instance,
OUT EFI_IMAGE_INPUT *Image,
OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
OUT INTN *OffsetX,
OUT INTN *OffsetY
)
{
UINT32 Current;
if (Instance == NULL || Image == NULL ||
Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
return EFI_INVALID_PARAMETER;
}
Current = *Instance;
if (Current >= ARRAY_SIZE (mLogos)) {
return EFI_NOT_FOUND;
}
(*Instance)++;
*Attribute = mLogos[Current].Attribute;
*OffsetX = mLogos[Current].OffsetX;
*OffsetY = mLogos[Current].OffsetY;
return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
mLogos[Current].ImageId, Image);
}
STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
GetImage
};
/**
Entrypoint of this module.
This function is the entrypoint of this module. It installs the Edkii
Platform Logo protocol.
@param ImageHandle The firmware allocated handle for the EFI image.
@param SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
**/
EFI_STATUS
EFIAPI
InitializeLogo (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HII_PACKAGE_LIST_HEADER *PackageList;
EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
EFI_HANDLE Handle;
Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
(VOID **) &HiiDatabase);
ASSERT_EFI_ERROR (Status);
Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
(VOID **) &mHiiImageEx);
ASSERT_EFI_ERROR (Status);
//
// Retrieve HII package list from ImageHandle
//
Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
(VOID **) &PackageList, ImageHandle, NULL,
EFI_OPEN_PROTOCOL_GET_PROTOCOL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR,
"HII Image Package with logo not found in PE/COFF resource section\n"));
return Status;
}
//
// Publish HII package list to HII Database.
//
Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
&mHiiHandle);
if (!EFI_ERROR (Status)) {
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
&gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
}
return Status;
}

10
edk2-rockchip/Platform/Rockchip/RK3588/LogoDxe/Logo.idf
View File

@@ -1,10 +0,0 @@
// @file
// Platform Logo image definition file.
//
// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
#image IMG_LOGO Logo.bmp

48
edk2-rockchip/Platform/Rockchip/RK3588/LogoDxe/LogoDxe.inf
View File

@@ -1,48 +0,0 @@
## @file
# The default logo bitmap picture shown on setup screen.
#
# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
# Copyright (c) 2022 Rockchip Electronics Co. Ltd.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = LogoDxe
FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InitializeLogo
#
# This flag specifies whether HII resource section is generated into PE image.
#
UEFI_HII_RESOURCE_SECTION = TRUE
[Sources]
Logo.bmp
Logo.c
Logo.idf
[Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
UefiBootServicesTableLib
UefiDriverEntryPoint
DebugLib
[Protocols]
gEfiHiiDatabaseProtocolGuid ## CONSUMES
gEfiHiiImageExProtocolGuid ## CONSUMES
gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES
gEdkiiPlatformLogoProtocolGuid ## PRODUCES
[Depex]
gEfiHiiDatabaseProtocolGuid AND
gEfiHiiImageExProtocolGuid

1079
edk2-rockchip/Platform/Rockchip/RK3588/PlatformSmbiosDxe/PlatformSmbiosDxe.c
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64
edk2-rockchip/Platform/Rockchip/RK3588/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
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@@ -1,64 +0,0 @@
#/** @file
#
# SMBIOS Table for the RaspberryPi platform
#
# Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com>
# Copyright (c) Microsoft Corporation. All rights reserved.
# Copyright (c) 2013 Linaro.org
# Copyright (c) 2020, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x0001001A
BASE_NAME = PlatformSmbiosDxe
FILE_GUID = BAD0554E-22E9-4D83-9AFD-CC87727A1A45
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = PlatformSmbiosDriverEntryPoint
[Sources]
PlatformSmbiosDxe.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPkg/ArmPkg.dec
Platform/Rockchip/RK3588/RK3588.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
ArmLib
UefiBootServicesTableLib
MemoryAllocationLib
BaseMemoryLib
BaseLib
UefiLib
UefiDriverEntryPoint
DebugLib
PrintLib
TimeBaseLib
[Protocols]
gEfiSmbiosProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
# gRaspberryPiFirmwareProtocolGuid ## CONSUMES
[Guids]
# gConfigDxeFormSetGuid
[Depex]
gEfiSmbiosProtocolGuid
# AND gRaspberryPiFirmwareProtocolGuid
[Pcd]
gArmTokenSpaceGuid.PcdFdBaseAddress
gArmTokenSpaceGuid.PcdFdSize
gArmTokenSpaceGuid.PcdSystemMemorySize
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
# gRaspberryPiTokenSpaceGuid.PcdFdtSize
# gRaspberryPiTokenSpaceGuid.PcdRamMoreThan3GB
# gRaspberryPiTokenSpaceGuid.PcdRamLimitTo3GB

35
edk2-rockchip/Platform/Rockchip/RK3588/RK3588.dec
View File

@@ -1,35 +0,0 @@
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
DEC_SPECIFICATION = 0x0001001a
PACKAGE_NAME = RK3588
PACKAGE_GUID = 9364fc90-45e7-11ec-9726-f42a7dcb925d
PACKAGE_VERSION = 0.1
################################################################################
#
# Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
# Supported Module Types:
# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
#
################################################################################
[Includes.common]
Include # Root include for the package
[Guids.common]
gRK3588TokenSpaceGuid = { 0xaad4eac0, 0x45e7, 0x11ec, { 0x95, 0xb4, 0xf4, 0x2a, 0x7d, 0xcb, 0x92, 0x5d } }
[PcdsFixedAtBuild.common]
gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L""|VOID*|0x00000001
gRK3588TokenSpaceGuid.PcdAndroidBootFile|{ 0x36, 0x8b, 0x73, 0x3a, 0xc5, 0xb9, 0x63, 0x47, 0xab, 0xbd, 0x6c, 0xbd, 0x4b, 0x25, 0xf9, 0xff }|VOID*|0x00000002
gRK3588TokenSpaceGuid.PcdAndroidFastbootFile|{ 0x2a, 0x50, 0x88, 0x95, 0x70, 0x53, 0xe3, 0x11, 0x86, 0x31, 0xd7, 0xc5, 0x95, 0x13, 0x64, 0xc8 }|VOID*|0x00000003
gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L""|VOID*|0x00000004
gRK3588TokenSpaceGuid.AcpiEnable|FALSE|BOOLEAN|0x00000005
gRK3588TokenSpaceGuid.PcdKernelBootArg|L""|VOID*|0x00000006
gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x0|UINT64|0x00000007

554
edk2-rockchip/Platform/Rockchip/RK3588/RK3588.dsc
View File

@@ -1,554 +0,0 @@
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = RK3588
PLATFORM_GUID = d080df36-45e7-11ec-9726-f42a7dcb925d
PLATFORM_VERSION = 0.2
DSC_SPECIFICATION = 0x00010019
OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
SUPPORTED_ARCHITECTURES = AARCH64
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
FLASH_DEFINITION = Platform/Rockchip/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
DEFINE CONFIG_NO_DEBUGLIB = TRUE
DEFINE CP_UNCONNECTED = 0x0
DEFINE CP_PCIE = 0x01
DEFINE CP_SATA = 0x10
DEFINE CP_USB3 = 0x20
#
# Network definition
#
DEFINE NETWORK_SNP_ENABLE = FALSE
DEFINE NETWORK_IP6_ENABLE = FALSE
DEFINE NETWORK_TLS_ENABLE = FALSE
DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
DEFINE NETWORK_ISCSI_ENABLE = FALSE
DEFINE NETWORK_VLAN_ENABLE = FALSE
!include Silicon/Rockchip/Rockchip.dsc.inc
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
ArmPlatformLib|Platform/Rockchip/RK3588/Library/RK3588Lib/RK3588Lib.inf
RockchipPlatformLib|Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RockchipPlatformLib.inf
CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf
DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
# UiApp dependencies
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
#SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
#RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
# USB Requirements
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
# PCIe
PciSegmentLib|Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.inf
PciHostBridgeLib|Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/Rk3588PciHostBridgeLib.inf
Pcie30PhyLib|Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
# VariableRuntimeDxe Requirements
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
AndroidBootImgLib|edk2/EmbeddedPkg/Library/AndroidBootImgLib/AndroidBootImgLib.inf
RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
[LibraryClasses.common.SEC]
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
RockchipPlatformLib|Platform/Rockchip/RK3588/Library/RockchipPlatformLib/RockchipPlatformLib.inf
[BuildOptions]
GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Platform/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsFeatureFlag.common]
# If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
# It could be set FALSE to save size.
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
[PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Alpha"
# System Memory (1GB)
gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
gRK3588TokenSpaceGuid.PcdTotalMemorySize|0x200000000
# RK3588 CPU profile
gArmPlatformTokenSpaceGuid.PcdCoreCount|4
gArmPlatformTokenSpaceGuid.PcdClusterCount|1
#
# ARM PrimeCell
#
# I2C
gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x51 }
gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x2 }
gRockchipTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x2 }
gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000
gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000
gRockchipTokenSpaceGuid.PcdI2cBusCount|1
gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x51 } #/* RTCYM8563TS 0x51@bus2 */
gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x2 }
## UART2 - Serial Terminal
DEFINE SERIAL_BASE = 0xFEB50000 # UART2
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
## SPI - SPI2 for test
gRockchipTokenSpaceGuid.SpiTestBaseAddr|0xFEB20000
gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000
## PL031 RealTimeClock
#gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0xF8003000
## NOR FLASH
gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000
## CRU
gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000
#gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000
#
# ARM General Interrupt Controller
#
gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10
# GUID of the UI app
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
#
# DW SD card controller
#
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeBaseAddress|0xfe2c0000
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeClockFrequencyInHz|100000000
gDesignWareTokenSpaceGuid.PcdDwPermitObsoleteDrivers|TRUE
gDesignWareTokenSpaceGuid.PcdDwEmmcDxeFifoDepth|256
#
# SDHCI controller
#
gRockchipTokenSpaceGuid.PcdSdhciDxeBaseAddress|0xfe2e0000
#
# PCIe controller
#
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4ApbBaseAddress|0xfe150000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4DbiBaseAddress|0xf5000000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgBaseAddress|0xf0000000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4CfgSize|0x100000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoBaseAddress|0xf0100000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4IoSize|0x10000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress|0xf0200000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize|0xe00000
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemBaseAddress64|0x901000000 #deduct 0x1000000 ECAM space
gRockchipTokenSpaceGuid.PcdPcieRootPort3x4MemSize64|0x3f000000
#
#
# Fastboot
#
gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbVendorId|0x2207
gEmbeddedTokenSpaceGuid.PcdAndroidFastbootUsbProductId|0x0001
#
# USB OHCI controller
#
gRockchipTokenSpaceGuid.PcdOhciBaseAddress|0xfc840000
gRockchipTokenSpaceGuid.PcdNumOhciController|2
gRockchipTokenSpaceGuid.PcdOhciSize|0x80000
#
# USB2 EHCI controller
#
gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000
gRockchipTokenSpaceGuid.PcdNumEhciController|2
gRockchipTokenSpaceGuid.PcdEhciSize|0x80000
#
# DWC3 controller
#
gRockchipTokenSpaceGuid.PcdDwc3BaseAddress|0xfc000000
gRockchipTokenSpaceGuid.PcdNumDwc3Controller|2
gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000
#
# USB XHCI controller
#
gRockchipTokenSpaceGuid.PcdXhciBaseAddress|0xfc000000
gRockchipTokenSpaceGuid.PcdNumXhciController|2
gRockchipTokenSpaceGuid.PcdXhciSize|0x400000
#
# Android Loader
#
gRK3588TokenSpaceGuid.PcdAndroidBootDevicePath|L"\\EFI\\BOOT\\GRUBAA64.EFI"
gRK3588TokenSpaceGuid.PcdSdBootDevicePath|L"VenHw(0D51905B-B77E-452A-A2C0-ECA0CC8D514A,00E023F70000000000)/SD(0x0)"
gRK3588TokenSpaceGuid.PcdKernelBootArg|L"earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=614e0000-0000 rw rootwait"
gEmbeddedTokenSpaceGuid.PcdAndroidBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(3,GPT,7A3F0000-0000-446A-8000-702F00006273,0x8000,0x20000)"
#
# Make VariableRuntimeDxe work at emulated non-volatile variable mode.
#
# gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
# ACPI Enable
!ifdef $(ROCKCHIP_ACPIEN)
gRK3588TokenSpaceGuid.AcpiEnable|TRUE
!endif
#
# Display
#
gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001
gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0
#gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1
gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0
#gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1
#
# ComboPhy
#
gRockchipTokenSpaceGuid.PcdComboPhyMode|{ $(CP_SATA), $(CP_USB3), $(CP_PCIE) }
[PcdsDynamicDefault.common]
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x007C0000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x007CF000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x007D0000
#
# Display
#
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x780
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x438
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
#
################################################################################
[Components.common]
#
# PEI Phase modules
#
ArmPlatformPkg/PrePi/PeiUniCore.inf
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf
#
# DXE
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
}
#
# Architectural Protocols
#
ArmPkg/Drivers/CpuDxe/CpuDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
#EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
<LibraryClasses>
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
}
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
#PCIe
MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/Rk3588PciHostBridgeLib.inf
Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
#MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
#INF MdeModulePkg/Bus/Pci/EhciDxe/XhciDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
# MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
# MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
#Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
Platform/Rockchip/RK3588/LogoDxe/LogoDxe.inf
Platform/Rockchip/RK3588/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
#
# ACPI Support
#
!ifdef $(ROCKCHIP_ACPIEN)
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
Platform/Rockchip/RK3588/AcpiTables/AcpiTables.inf
!else
# DTB
EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf {
<LibraryClasses>
DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf
}
!endif
#
# GPIO
#
Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
#ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
#
# Virtual Keyboard
#
EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
# Platform drivers
Platform/Rockchip/RK3588/RK3588Dxe/RK3588Dxe.inf
# I2C drivers
Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
#
# MMC/SD
#
#EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
#Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
#Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
#
# NOR FLASH
#
Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
Silicon/Rockchip/Drivers/NorFlashDxe/RkFvbDxe.inf
Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
#
# AHCI Support
#
Silicon/Rockchip/Drivers/SataControllerDxe/SataControllerDxe.inf
Silicon/Rockchip/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
#
# SPI TEST
#
# Silicon/Rockchip/Library/SpiLib/SpiTest.inf
#
# SMBIOS Support
#
Platform/Rockchip/RK3588/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# USB Ohci Controller
#
Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
#
# USB Ehci Controller
#
Silicon/Rockchip/Drivers/EhciDxe/EhciDxe.inf
#
# USB Dwc3 Controller
#
Silicon/Rockchip/Drivers/UsbDwc3InitDxe/UsbDwc3.inf
#
# USB Xhci Controller
#
Silicon/Rockchip/Drivers/XhciDxe/XhciDxe.inf
#
# USB Host Support
#
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
#
# USB Mass Storage Support
#
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# USB Kb Support
#
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
#
# USB Mouse Support
#
MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
#
# USB MouseAbsolutePointer Support
#
MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
#
# USB Peripheral Support
#
EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
#
# Fastboot
#
EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
#
# Android Boot applications
#
EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
#
# UEFI Network Stack
#
!include NetworkPkg/Network.dsc.inc
#
# AX88772 Ethernet Driver
#
Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
#
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf
#
# Bds
#
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
MdeModulePkg/Application/UiApp/UiApp.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
ShellPkg/Application/Shell/Shell.inf {
<LibraryClasses>
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf
NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
#NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
<PcdsFixedAtBuild>
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
}
!ifdef $(INCLUDE_TFTP_COMMAND)
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)

367
edk2-rockchip/Platform/Rockchip/RK3588/RK3588.fdf
View File

@@ -1,367 +0,0 @@
#
# Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.NOR_FLASH_IMAGE]
BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
Size = 0x00800000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
# This one is tricky, it must be: BlockSize * NumBlocks = Size
BlockSize = 0x00001000
NumBlocks = 0x800
################################################################################
#
# Following are lists of FD Region layout which correspond to the locations of different
# images within the flash device.
#
# Regions must be defined in ascending order and may not overlap.
#
# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
# the pipe "|" character, followed by the size of the region, also in hex with the leading
# "0x" characters. Like:
# Offset|Size
# PcdOffsetCName|PcdSizeCName
# RegionType <FV, DATA, or FILE>
#
################################################################################
0x00200000|0x000F0000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = BL33_AP_UEFI
# NV_VARIABLE_STORE
0x007C0000|0x00010000
gRockchipTokenSpaceGuid.PcdNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
# NV_FTW_WORKING header
0x007D0000|0x00010000
gRockchipTokenSpaceGuid.PcdNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
# NV_FTW_WORKING data
0x007E0000|0x00010000
gRockchipTokenSpaceGuid.PcdNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FvMain]
BlockSize = 0x40
NumBlocks = 0 # This FV gets compressed so make it just big enough
FvAlignment = 8 # FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
APRIORI DXE {
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
}
INF MdeModulePkg/Core/Dxe/DxeMain.inf
#
# PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
#
# Multiple Console IO support
#
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
!ifdef $(ROCKCHIP_VOPEN)
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
!endif
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
#
# ACPI Support
#
!ifdef $(ROCKCHIP_ACPIEN)
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF RuleOverride = ACPITABLE Platform/Rockchip/RK3588/AcpiTables/AcpiTables.inf
!else
# DTB
INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 {
SECTION RAW = Platform/Rockchip/DeviceTree/rk3588.dtb
}
!endif
#
# GPIO
#
INF Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
#INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf
#
# I2C
#
INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf
INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf
# INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf
#
# Virtual Keyboard
#
INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf
#
# Display Support
#
!ifdef $(ROCKCHIP_VOPEN)
INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
#INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
INF Platform/Rockchip/RK3588/LogoDxe/LogoDxe.inf
INF Platform/Rockchip/RK3588/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
!endif
INF Platform/Rockchip/RK3588/RK3588Dxe/RK3588Dxe.inf
#
# SMBIOS Support
#
INF Platform/Rockchip/RK3588/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# USB Ehci Controller
#
INF Silicon/Rockchip/Drivers/EhciDxe/EhciDxe.inf
#
# USB Ohci Controller
#
INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
#
# USB Dwc3 Controller
#
INF Silicon/Rockchip/Drivers/UsbDwc3InitDxe/UsbDwc3.inf
#
# USB Xhci Controller
#
INF Silicon/Rockchip/Drivers/XhciDxe/XhciDxe.inf
#
# USB Host Support
#
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
#
# USB Mass Storage Support
#
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# USB Kb Support
#
INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
#
# USB Mouse Support
#
INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
#
# USB MouseAbsolutePointer Support
#
INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf
#
# USB Peripheral Support
#
INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
#
# Fastboot
#
INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
!ifdef $(ROCKCHIP_PCIE30)
#PCIe
# INF Silicon/Rockchip/Drivers/PciPlatform/PcieInitDxe.inf
# Required by PCI
INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
# PCI Support
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
#INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf
#INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
#INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
# INF MdeModulePkg/Bus/Pci/EhciDxe/XhciDxe.inf
INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
!endif
#
# Android Boot applications
#
INF EmbeddedPkg/Application/AndroidBoot/AndroidBootApp.inf
#
# UEFI Network Stack
#
!include NetworkPkg/Network.fdf.inc
#
# AX88772 Ethernet Driver for Apple Ethernet Adapter
#
INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf
#
# FAT filesystem + GPT/MBR partitioning
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# Multimedia Card Interface
#
#INF Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf
INF Silicon/Rockchip/Drivers/MmcDxe/MmcDxe.inf
#INF Silicon/Rockchip/Drivers/DwEmmcDxe/DwEmmcDxe.inf
INF Silicon/Rockchip/Drivers/SdhciHostDxe/SdhciHostDxe.inf
#
# AHCI Support
#
INF Silicon/Rockchip/Drivers/SataControllerDxe/SataControllerDxe.inf
INF Silicon/Rockchip/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
#
# SPI NOR FLASH
#
INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf
# Variable services
INF Silicon/Rockchip/Drivers/NorFlashDxe/RkFvbDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
# Human interface
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
#
# UEFI applications
#
INF ShellPkg/Application/Shell/Shell.inf
!ifdef $(INCLUDE_TFTP_COMMAND)
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif #$(INCLUDE_TFTP_COMMAND)
#INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf
#
# Bds
#
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
[FV.BL33_AP_UEFI]
FvAlignment = 8
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF ArmPlatformPkg/PrePi/PeiUniCore.inf
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
}
}
!include Silicon/Rockchip/Rockchip.fdf.inc
!ifdef $(ROCKCHIP_ACPIEN)
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
RAW ACPI Optional |.acpi
RAW ASL Optional |.aml
}
[Rule.Common.USER_DEFINED.ACPITABLE]
FILE FREEFORM = $(NAMED_GUID) {
RAW ACPI |.acpi
RAW ASL |.aml
}
!endif

53
edk2-rockchip/Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.c
View File

@@ -1,53 +0,0 @@
/** @file
*
* Copyright (c) 2018, Linaro. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/EmbeddedGpio.h>
GPIO_CONTROLLER gGpioDevice[] = {
//
// { base address, gpio index, gpio count }
//
{ 0xFDD60000, 0, 32 }, // GPIO0
{ 0xFE740000, 32, 32 }, // GPIO1
{ 0xFE750000, 64, 32 }, // GPIO2
{ 0xFE760000, 96, 32 }, // GPIO3
{ 0xFE770000, 128, 32 }, // GPIO3
};
PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = {
//
// { global gpio count, gpio controller counter, GPIO_CONTROLLER }
//
160, 20, gGpioDevice
};
EFI_STATUS
EFIAPI
RK3588GpioEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
// Install the Embedded Platform GPIO Protocol onto a new handle
Handle = NULL;
Status = gBS->InstallMultipleProtocolInterfaces(
&Handle,
&gPlatformGpioProtocolGuid, &gPlatformGpioDevice,
NULL
);
if (EFI_ERROR(Status)) {
Status = EFI_OUT_OF_RESOURCES;
}
return Status;
}

30
edk2-rockchip/Platform/Rockchip/RK3588/RK3588GpioDxe/RK3588GpioDxe.inf
View File

@@ -1,30 +0,0 @@
#
# Copyright (c) 2018, Linaro. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
[Defines]
INF_VERSION = 0x0001001a
BASE_NAME = RK3588Gpio
FILE_GUID = 271ea88c-45ed-11ec-9726-f42a7dcb925d
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = RK3588GpioEntryPoint
[Sources.common]
RK3588GpioDxe.c
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
DebugLib
UefiDriverEntryPoint
[Protocols]
gPlatformGpioProtocolGuid
[Depex]
TRUE

29
edk2-rockchip/Silicon/Rockchip/Applications/MaskromReset/maskrom.c
View File

@@ -1,29 +0,0 @@
#include <Uefi.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiApplicationEntryPoint.h>
#include <Library/UefiRuntimeServicesTableLib.h>
/**
The user Entry Point for Application. The user code starts with this function
as the real entry point for the application.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
UefiMain (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
gRT->ResetSystem (EfiResetPlatformSpecific, EFI_SUCCESS, StrSize(L"MASKROM"), L"MASKROM");
return EFI_SUCCESS;
}

24
edk2-rockchip/Silicon/Rockchip/Applications/MaskromReset/maskrom.inf
View File

@@ -1,24 +0,0 @@
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = maskrom
FILE_GUID = 6987437F-ED34-44db-AE97-1FA5E4ED2116
MODULE_TYPE = UEFI_APPLICATION
VERSION_STRING = 1.0
ENTRY_POINT = UefiMain
[Sources]
maskrom.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Rockchip/RockchipPkg.dec
[LibraryClasses]
UefiApplicationEntryPoint
UefiLib
PcdLib
DebugLib
[Guids]
gMaskromFileGuid

1
edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
View File

@@ -29,7 +29,6 @@
MdePkg/MdePkg.dec
Silicon/Rockchip/RockchipPkg.dec
Silicon/Rockchip/RK3588/RK3588.dec
Platform/Rockchip/RK3588/RK3588.dec
[LibraryClasses]
ArmLib

1
edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf
View File

@@ -58,7 +58,6 @@
[Protocols]
gEfiDevicePathProtocolGuid
gEfiFirmwareVolumeBlockProtocolGuid
gRockchipSpiFlashProtocolGuid
gUniNorFlashProtocolGuid
gEfiDiskIoProtocolGuid
gEfiBlockIoProtocolGuid

151
edk2-rockchip/Silicon/Rockchip/Drivers/UpdateFdtDxe/UpdateFdtDxe.c
View File

@@ -1,151 +0,0 @@
/** @file
*
* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
* Copyright (c) 2015, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Uefi.h>
#include <Pi/PiDxeCis.h>
#include <Library/DebugLib.h>
#include <libfdt.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Guid/Fdt.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/FdtUpdateLib.h>
STATIC
EFI_STATUS
InstallFdtIntoConfigurationTable (
IN VOID* FdtBlob,
IN UINTN FdtSize
)
{
EFI_STATUS Status;
// Check the FDT header is valid. We only make this check in DEBUG mode in case the FDT header change on
// production device and this ASSERT() becomes not valid.
if(!(fdt_check_header (FdtBlob) == 0))
{
DEBUG ((EFI_D_ERROR,"can not find FdtBlob \n"));
return EFI_INVALID_PARAMETER;
}
// Ensure the Size of the Device Tree is smaller than the size of the read file
if(!((UINTN)fdt_totalsize (FdtBlob) <= FdtSize))
{
DEBUG ((EFI_D_ERROR,"FdtBlob <= FdtSize \n"));
return EFI_INVALID_PARAMETER;
}
// Install the FDT into the Configuration Table
Status = gBS->InstallConfigurationTable (&gFdtTableGuid, FdtBlob);
return Status;
}
EFI_STATUS
SetNvramSpace (VOID)
{
EFI_STATUS Status;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0};
if (PcdGet64(PcdReservedNvramSize) == 0) {
return EFI_SUCCESS;
}
Status = gDS->GetMemorySpaceDescriptor(PcdGet64(PcdReservedNvramBase),&desp);
if(EFI_ERROR(Status)){
DEBUG ((EFI_D_ERROR,"get memory space error:--------- \n"));
return Status;
}
desp.Attributes |= EFI_MEMORY_RUNTIME | EFI_MEMORY_WB;
Status = gDS->SetMemorySpaceAttributes(PcdGet64(PcdReservedNvramBase),PcdGet64(PcdReservedNvramSize), desp.Attributes);
if(EFI_ERROR(Status)){
DEBUG ((EFI_D_ERROR,"set memory space error:--------- \n"));
return Status;
}
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI UpdateFdt (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable)
{
INTN Error;
VOID* Fdt;
UINT32 Size;
UINTN NewFdtBlobSize;
UINTN NewFdtBlobBase;
EFI_STATUS Status = EFI_SUCCESS;
UINT32 Index = 0;
UINTN FDTConfigTable;
(VOID) SetNvramSpace ();
Fdt = (VOID*)(PcdGet64(FdtFileAddress));
Error = fdt_check_header ((VOID*)(PcdGet64(FdtFileAddress)));
DEBUG ((EFI_D_ERROR,"fdtfileaddress:--------- 0x%lx\n",PcdGet64(FdtFileAddress)));
if (Error != 0)
{
DEBUG ((EFI_D_ERROR,"ERROR: Device Tree header not valid (%a)\n", fdt_strerror(Error)));
return EFI_INVALID_PARAMETER;
}
Size = (UINTN)fdt_totalsize ((VOID*)(PcdGet64(FdtFileAddress)));
NewFdtBlobSize = Size + ADD_FILE_LENGTH;
Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase);
if (EFI_ERROR (Status))
{
return EFI_OUT_OF_RESOURCES;
}
(VOID) CopyMem((VOID*)NewFdtBlobBase, Fdt, Size);
Status = EFIFdtUpdate(NewFdtBlobBase);
if (EFI_ERROR (Status))
{
DEBUG((EFI_D_ERROR, "%a(%d):EFIFdtUpdate Fail!\n", __FUNCTION__,__LINE__));
goto EXIT;
}
Status = InstallFdtIntoConfigurationTable ((VOID*)(UINTN)NewFdtBlobBase, NewFdtBlobSize);
DEBUG ((EFI_D_ERROR, "NewFdtBlobBase: 0x%lx NewFdtBlobSize:0x%lx\n",NewFdtBlobBase,NewFdtBlobSize));
if (EFI_ERROR (Status))
{
DEBUG ((EFI_D_ERROR, "installfdtconfiguration table fail():\n"));
goto EXIT;
}
for (Index = 0; Index < gST->NumberOfTableEntries; Index ++)
{
if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid)))
{
FDTConfigTable = (UINTN)gST->ConfigurationTable[Index].VendorTable;
DEBUG ((EFI_D_ERROR, "FDTConfigTable Address: 0x%lx\n",FDTConfigTable));
break;
}
}
return Status;
EXIT:
gBS->FreePages(NewFdtBlobBase,EFI_SIZE_TO_PAGES(NewFdtBlobSize));
return Status;
}

56
edk2-rockchip/Silicon/Rockchip/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
View File

@@ -1,56 +0,0 @@
#/** @file
#
# Copyright (c) 2015, Hisilicon Limited. All rights reserved.
# Copyright (c) 2015, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = UpdateFdtDxe
FILE_GUID = 517e1b74-3177-11ec-95b4-f42a7dcb925d
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = UpdateFdt
[Sources.common]
UpdateFdtDxe.c
[Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
ArmPkg/ArmPkg.dec
OpenPlatformPkg/Chips/Rockchip/RockchipPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
[LibraryClasses]
UefiBootServicesTableLib
MemoryAllocationLib
UefiDriverEntryPoint
DebugLib
BaseLib
FdtLib
PcdLib
FdtUpdateLib
DxeServicesTableLib
[Guids]
gFdtTableGuid
[Protocols]
gRockchipBoardNicProtocolGuid
[Pcd]
gRockchipTokenSpaceGuid.FdtFileAddress
gRockchipTokenSpaceGuid.PcdReservedNvramSize
gRockchipTokenSpaceGuid.PcdReservedNvramBase
[Depex]
gEfiGenericMemTestProtocolGuid

102
edk2-rockchip/Silicon/Rockchip/Drivers/VersionInfoPeim/VersionInfoPeim.c
View File

@@ -1,102 +0,0 @@
/** @file
*
* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
* Copyright (c) 2016, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Uefi.h>
#include <PiPei.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/HobLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include <Guid/VersionInfoHobGuid.h>
struct MonthDescription {
CONST CHAR8* MonthStr;
UINT32 MonthInt;
} gMonthDescription[] = {
{ "Jan", 1 },
{ "Feb", 2 },
{ "Mar", 3 },
{ "Apr", 4 },
{ "May", 5 },
{ "Jun", 6 },
{ "Jul", 7 },
{ "Aug", 8 },
{ "Sep", 9 },
{ "Oct", 10 },
{ "Nov", 11 },
{ "Dec", 12 },
{ "???", 1 }, // Use 1 as default month
};
VOID GetReleaseTime (EFI_TIME *Time)
{
CONST CHAR8 *ReleaseDate = __DATE__;
CONST CHAR8 *ReleaseTime = __TIME__;
UINTN i;
for(i=0;i<12;i++)
{
if(0 == AsciiStrnCmp(ReleaseDate, gMonthDescription[i].MonthStr, 3))
{
break;
}
}
Time->Month = gMonthDescription[i].MonthInt;
Time->Day = AsciiStrDecimalToUintn(ReleaseDate+4);
Time->Year = AsciiStrDecimalToUintn(ReleaseDate+7);
Time->Hour = AsciiStrDecimalToUintn(ReleaseTime);
Time->Minute = AsciiStrDecimalToUintn(ReleaseTime+3);
Time->Second = AsciiStrDecimalToUintn(ReleaseTime+6);
return;
}
EFI_STATUS
EFIAPI
VersionInfoEntry (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
CHAR8 Buffer[100];
UINTN CharCount;
VERSION_INFO *VersionInfo;
EFI_TIME Time = {0};
CONST CHAR16 *ReleaseString =
(CHAR16 *) FixedPcdGetPtr (PcdFirmwareVersionString);
GetReleaseTime (&Time);
CharCount = AsciiSPrint (
Buffer,
sizeof (Buffer),
"\n\rBoot firmware (version %s built at %t)\n\r\n\r",
ReleaseString,
&Time
);
SerialPortWrite ((UINT8 *) Buffer, CharCount);
VersionInfo = BuildGuidHob (&gVersionInfoHobGuid,
sizeof (VERSION_INFO) -
sizeof (VersionInfo->String) +
StrSize (ReleaseString));
if (VersionInfo == NULL) {
DEBUG ((EFI_D_ERROR, "[%a]:[%d] Build HOB failed!\n", __FILE__, __LINE__));
return EFI_OUT_OF_RESOURCES;
}
CopyMem (&VersionInfo->BuildTime, &Time, sizeof (EFI_TIME));
CopyMem (VersionInfo->String, ReleaseString, StrSize (ReleaseString));
return EFI_SUCCESS;
}

47
edk2-rockchip/Silicon/Rockchip/Drivers/VersionInfoPeim/VersionInfoPeim.inf
View File

@@ -1,47 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = VersionInfoPeim
FILE_GUID = 63733b70-3177-11ec-95b4-f42a7dcb925d
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = VersionInfoEntry
[Sources.common]
VersionInfoPeim.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Rockchip/RockchipPkg.dec
[LibraryClasses]
PeimEntryPoint
PcdLib
DebugLib
HobLib
BaseLib
BaseMemoryLib
PrintLib
SerialPortLib
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
[Guids]
gVersionInfoHobGuid
[Depex]
TRUE
[BuildOptions]

29
edk2-rockchip/Silicon/Rockchip/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c
View File

@@ -1,29 +0,0 @@
/** @file
*
* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
* Copyright (c) 2016, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <PiDxe.h>
#include <Library/NonDiscoverableDeviceRegistrationLib.h>
#include <Library/PlatformSysCtrlLib.h>
EFI_STATUS
EFIAPI
EhciVirtualPciIoInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
return RegisterNonDiscoverableMmioDevice (
NonDiscoverableDeviceTypeEhci,
NonDiscoverableDeviceDmaTypeCoherent,
NULL,
NULL,
1,
PlatformGetEhciBase (),
SIZE_4KB);
}

33
edk2-rockchip/Silicon/Rockchip/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
View File

@@ -1,33 +0,0 @@
#/** @file
#
# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
# Copyright (c) 2016, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = VirtualEhciPciIo
FILE_GUID = 6a3761fc-3177-11ec-95b4-f42a7dcb925d
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = EhciVirtualPciIoInitialize
[Sources]
VirtualEhciPciIo.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Rockchip/RockchipNonOsi.dec
Silicon/Rockchip/RockchipPkg.dec
[LibraryClasses]
NonDiscoverableDeviceRegistrationLib
PlatformSysCtrlLib
UefiDriverEntryPoint

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