Update README.md

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

.gitmodules

@@ -14,3 +14,6 @@
 [submodule "devicetree/mainline/upstream"]
 	path = devicetree/mainline/upstream
 	url = https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
+[submodule "edk2-platforms"]
+	path = edk2-platforms
+	url = https://github.com/tianocore/edk2-platforms.git

README.md

@@ -69,7 +69,7 @@ Note that this list is subject to change at any time as devices gain better supp
 ### Mainline compatibility mode
 | OS | Version | Tested/supported hardware | Notes |
 | --- | --- | --- | --- |
-| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41<br> - Fedora Workstation Rawhide | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.13 lack HDMI output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
+| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41<br> - Fedora Workstation Rawhide | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.15 lack display output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
 
 > [!NOTE]
 > Mainline support is only available on [Platinum](#platinum) platforms.
@@ -120,7 +120,7 @@ If your platform is not yet supported, using an image meant for another device i
 ## 3. Flash the firmware
 UEFI can be flashed to either an SPI NOR flash, SD card or eMMC module:
 * For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
-* For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
+* For SPI NOR or soldered eMMC, instructions can be found at: <https://docs.radxa.com/en/rock5/lowlevel-development/bootloader_spi_flash>.
 
   In short, you can flash the image from Linux booted on the device or by using RKDevTool on another computer. The latter requires entering Maskrom mode on the device. The way to do this slightly varies across platforms, refer to your vendor documentation.
 
@@ -171,22 +171,31 @@ The firmware provides two compatibility modes:
 [Platinum](#platinum) platforms will have the `Mainline` option enabled by default, while [Bronze](#bronze) ones will fall back to `Vendor`.
 
 > [!TIP]
-> In `Mainline` mode with generic Linux kernels older than 6.13, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
+> In `Mainline` mode with generic Linux kernels older than 6.15, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
 
 ### Custom Device Tree Blob (DTB) override and overlays
-It is also possible to provide a custom DTB and overlays. To enable this, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
+It is also possible to provide a custom DTB and overlays. This is useful in cases where the firmware DTB is outdated, does not match the kernel used or for testing purposes. To enable overrides, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
 
-The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases, this will be the first FAT32 EFI System Partition.
+The firmware will now look for overrides in all supported file systems / partitions (FAT, ext4) on the selected boot device.
 
-**Important:** The `dtb` directory must be placed at the root of the partition. It should not be inside any sub-directory.
+**Important:**
+* The paths below are relative to the root of the partition. They must not be inside any sub-directory.
+* All overrides (base DTB and overlays) must be stored within a single partition. Using a base DTB from one partition and overlays from another is not allowed.
 
-* The base DTB must be located at `\dtb\base\<PLATFORM-DT-NAME>.dtb`.
+The base DTB can be placed in:
+* `\dtb`
+* `\dtb\base`
+* `\dtb\rockchip` - Fedora images have the kernel DTBs in this location on the second ext4 boot partition.
 
-* The overlays can be placed in:
-  * `\dtb\overlays` - will be applied first, regardless of the platform.
-  * `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+and must have the `<PLATFORM-DT-NAME>.dtb` file name.
 
-  and must have the `.dtbo` extension.
+The overlays can be placed in:
+* `\dtb\overlays` - will be applied first, regardless of the platform.
+* `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+
+and must have the `.dtbo` extension.
+
+In addition to the default paths above, it is possible to specify custom ones via the `Preferred Base DTB Path` and `Preferred Overlays Path` setup options in the menu described above.
 
 `<PLATFORM-DT-NAME>` can be:
 | Name                                    | Platform                      |
@@ -214,15 +223,16 @@ The firmware will now look for overrides in the partition of a selected boot opt
 | `rk3588s-nanopi-m6`                     | NanoPi M6                     |
 | `rk3588-hinlink-h88k`                   | H88K                          |
 
-In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.
+**Notes:**
+* The firmware applies some fix-ups to the DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied when providing overrides by other means, such as the Grub `devicetree` command.
 
-The firmware applies some fix-ups to its own DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied to a custom base DTB - overlays must be used instead.
+* In the absence of a base DTB override, the overlays are applied on top of the firmware-provided DTB.
 
-If the application of an overlay fails (e.g. due to it being invalid in regard to the base DTB), all overlays are discarded, including those that got applied up to that point.
+* If the application of an overlay fails (e.g. due to incompatibility with the base DTB), all other overlays are discarded.
 
-If the custom base DTB is invalid, the firmware-provided one will be passed to the OS instead.
+* If the base DTB override is invalid, the firmware-provided one will be passed to the OS instead.
 
-This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.
+* This process is logged to the [serial console](#advanced-troubleshooting). It is the only way to see potential errors.
 
 # Updating the firmware
 If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.

build.sh

@@ -138,7 +138,7 @@ function _build(){
 
     export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
     export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
-    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/devicetree:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
+    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/devicetree:${ROOTDIR}/edk2-non-osi:${ROOTDIR}/edk2-platforms:${ROOTDIR}"
 
     make -C "${ROOTDIR}/edk2/BaseTools"
     source "${ROOTDIR}/edk2/edksetup.sh"

devicetree/mainline/rk3588-buzztv-p6.dts

@@ -60,6 +60,31 @@
 		pinctrl-0 = <&ir_receiver_pin>;
 	};
 
+	rfkill {
+		compatible = "rfkill-gpio";
+		label = "rfkill-pcie-wlan";
+		radio-type = "wlan";
+		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+	};
+
+	spdif_dit: spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif_sound: spdif-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif_tx1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_dit>;
+		};
+	};
+
 	vcc12v_dcin: regulator-vcc12v-dcin {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc12v_dcin";
@@ -195,6 +220,11 @@
 };
 
 &hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmim0_tx0_cec
+		     &hdmim1_tx0_hpd
+		     &hdmim0_tx0_scl
+		     &hdmim0_tx0_sda>;
 	status = "okay";
 };
 
@@ -210,7 +240,11 @@
 	};
 };
 
-&hdptxphy_hdmi0 {
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdptxphy0 {
 	status = "okay";
 };
 
@@ -340,6 +374,10 @@
 	};
 };
 
+&i2s5_8ch {
+ 	status = "okay";
+};
+
 /* RTL8852BE */
 &pcie2x1l0 {
 	pinctrl-names = "default";
@@ -394,6 +432,10 @@
 	};
 };
 
+&pd_gpu {
+ 	domain-supply = <&vdd_gpu_s0>;
+};
+
 &pinctrl {
 	hym8563 {
 		hym8563_int: hym8563-int {
@@ -503,6 +545,12 @@
 	status = "okay";
 };
 
+&spdif_tx1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdif1m1_tx>;
+	status = "okay";
+};
+
 &spi2 {
 	status = "okay";
 	assigned-clocks = <&cru CLK_SPI2>;

devicetree/mainline/rk3588-friendlyelec-cm3588-nas-fixup.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-friendlyelec-cm3588-nas.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};

devicetree/mainline/rk3588-nanopc-t6-fixup.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-nanopc-t6.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};

devicetree/mainline/rk3588-rock-5-itx-fixup.dts

@@ -6,6 +6,14 @@
 	/delete-node/ pcie-oscillator;
 };
 
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};
+
 /*
  * Remove the "pcie30_refclk" gated-fixed-clock to maintain compatibility
  * with kernels older than v6.13-rc1. It is backed by a GPIO regulator

devicetree/mainline/rk3588s-indiedroid-nova-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-indiedroid-nova.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-khadas-edge2-fixup.dts

@@ -251,10 +251,18 @@
 	};
 };
 
-&hdptxphy_hdmi0 {
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdptxphy0 {
 	status = "okay";
 };
 
+&i2s5_8ch {
+ 	status = "okay";
+};
+
 &vop_mmu {
 	status = "okay";
 };

devicetree/mainline/rk3588s-nanopi-r6c-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-nanopi-r6c.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-nanopi-r6s-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-nanopi-r6s.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-rock-5a-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-rock-5a.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+  devicetree/mainline/rk3588s-indiedroid-nova-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -94,6 +94,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/BuzzTV/PowerStation6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -99,6 +99,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }
@@ -327,8 +329,8 @@ HdmiTxIomux (
     case 0:
       GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
       GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
-      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
-      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PD4, 3); // hdmim1_tx0_hpd
+      GpioPinSetPull (3, GPIO_PIN_PD4, GPIO_PIN_PULL_NONE);
       GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
       GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
       GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda

edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -143,6 +143,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -145,6 +145,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -97,6 +97,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts
+  devicetree/mainline/rk3588-friendlyelec-cm3588-nas-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
+  devicetree/mainline/rk3588-nanopc-t6-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -95,6 +95,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/FriendlyElec/NanoPi-M6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -94,6 +94,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts
+  devicetree/mainline/rk3588s-nanopi-r6c-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -94,6 +94,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-nanopi-r6s.dts
+  devicetree/mainline/rk3588s-nanopi-r6s-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -92,6 +92,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -94,6 +94,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -104,6 +104,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -95,6 +95,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -95,6 +95,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Radxa/ROCK5A/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+  devicetree/mainline/rk3588s-rock-5a-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -93,6 +93,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -96,6 +96,8 @@ Rk806Configure (
 
   RK806Init ();
 
+  RK806PinSetFunction (MASTER, 1, 2); // rk806_dvs1_pwrdn
+
   for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE (rk806_init_data); RegCfgIndex++) {
     RK806RegulatorInit (rk806_init_data[RegCfgIndex]);
   }

edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc

@@ -187,6 +187,7 @@
   INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
   INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   INF FatPkg/EnhancedFatDxe/Fat.inf
+!include Features/Ext4Pkg/Ext4.fdf.inc
   INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
   #

edk2-rockchip/Silicon/Rockchip/Include/Library/RK806.h

@@ -75,6 +75,20 @@
 #define RK806_RST_MODE2           0x02
 #define VERSION_AB                0x01
 
+#define RK806_SLEEP_CONFIG0  0x62
+#define RK806_SLEEP_CONFIG1  0x63
+#define RK806_SLEEP_GPIO     0x71
+
+#define RK806_PWRCTRL1_DR    BIT(0)
+#define RK806_PWRCTRL2_DR    BIT(1)
+#define RK806_PWRCTRL3_DR    BIT(2)
+#define RK806_PWRCTRL1_DATA  BIT(4)
+#define RK806_PWRCTRL2_DATA  BIT(5)
+#define RK806_PWRCTRL3_DATA  BIT(6)
+#define RK806_PWRCTRL1_FUN   0x07
+#define RK806_PWRCTRL2_FUN   0x70
+#define RK806_PWRCTRL3_FUN   0x07
+
 struct regulator_init_data {
   const char    *supply_regulator;           /* or NULL for system supply */
   INT32         reg_id;
@@ -94,6 +108,14 @@ struct rk8xx_reg_info {
   UINT8     range_num;
 };
 
+struct rk806_pin_config {
+  UINT8    fun_reg;
+  UINT8    fun_msk;
+  UINT8    reg;
+  UINT8    dir_msk;
+  UINT8    val_msk;
+};
+
 #define RK8XX_DESC_COM(_name, _reg_info, _ops) \
 {                                               \
         .reg_info		= (_reg_info),  \
@@ -180,4 +202,11 @@ RK806RegulatorInit (
   struct regulator_init_data  init_data
   );
 
+RETURN_STATUS
+RK806PinSetFunction (
+  IN UINT8  RegId,
+  IN UINT8  Pin,
+  IN UINT8  Function
+  );
+
 #endif

edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.c

@@ -1,5 +1,6 @@
 #include <Library/RockchipPlatformLib.h>
 #include "Soc.h"
+#include <Library/BaseLib.h>
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/PcdLib.h>
@@ -253,6 +254,30 @@ static const struct rk8xx_reg_info  rk806_pldo[] = {
   { 3400000, 0,     RK806_PLDO_ON_VSEL (6), RK806_PLDO_SLP_VSEL (6), NA, RK806_PLDO_VSEL_MASK, 0xE8, },
 };
 
+static const struct rk806_pin_config  rk806_gpio_cfgs[] = {
+  {
+    .fun_reg = RK806_SLEEP_CONFIG0,
+    .fun_msk = RK806_PWRCTRL1_FUN,
+    .reg     = RK806_SLEEP_GPIO,
+    .val_msk = RK806_PWRCTRL1_DATA,
+    .dir_msk = RK806_PWRCTRL1_DR,
+  },
+  {
+    .fun_reg = RK806_SLEEP_CONFIG0,
+    .fun_msk = RK806_PWRCTRL2_FUN,
+    .reg     = RK806_SLEEP_GPIO,
+    .val_msk = RK806_PWRCTRL2_DATA,
+    .dir_msk = RK806_PWRCTRL2_DR,
+  },
+  {
+    .fun_reg = RK806_SLEEP_CONFIG1,
+    .fun_msk = RK806_PWRCTRL3_FUN,
+    .reg     = RK806_SLEEP_GPIO,
+    .val_msk = RK806_PWRCTRL3_DATA,
+    .dir_msk = RK806_PWRCTRL3_DR,
+  }
+};
+
 #if 0
 static void
 io_mem_show (
@@ -399,11 +424,11 @@ pmic_clrsetbits (
   RETURN_STATUS  ret;
 
   ret = pmic_reg_read (cs_id, reg, &byte, 0x01);
-  if (ret < 0) {
+  if (ret) {
     return ret;
   }
 
-  byte = (ret & ~clr) | set;
+  byte = (byte & ~clr) | set;
 
   pmic_reg_write (cs_id, reg, &byte, 1);
   ret = pmic_reg_read (cs_id, reg, &byte, 0x01);
@@ -752,3 +777,34 @@ RK806Init (
 
   return RETURN_SUCCESS;
 }
+
+RETURN_STATUS
+RK806PinSetFunction (
+  IN UINT8  RegId,
+  IN UINT8  Pin,
+  IN UINT8  Function
+  )
+{
+  if ((Pin < 1) || (Pin > 3) || (Function > 5)) {
+    ASSERT (FALSE);
+    return RETURN_INVALID_PARAMETER;
+  }
+
+  const struct rk806_pin_config  *conf = &rk806_gpio_cfgs[Pin - 1];
+  UINT8                          mask  = conf->fun_msk;
+  UINT8                          cs_id = (RegId & 0xf00) >> 8;
+  UINT8                          val;
+
+  DEBUG ((
+    DEBUG_INFO,
+    "%a: RegId=0x%x, Pin=%u, Function=%u\n",
+    __func__,
+    RegId,
+    Pin,
+    Function
+    ));
+
+  val = Function << LowBitSet32 (mask);
+
+  return pmic_clrsetbits (cs_id, conf->fun_reg, mask, val);
+}

edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.inf

@@ -27,6 +27,7 @@
   RK806.c
 
 [LibraryClasses]
+  BaseLib
   DebugLib
   IoLib
   SpiLib

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf

@@ -2,7 +2,7 @@
 #
 #  Flattened Device Tree platform driver
 #
-#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -29,6 +29,7 @@
 [LibraryClasses]
   BaseLib
   DebugLib
+  DevicePathLib
   PrintLib
   DxeServicesLib
   MemoryAllocationLib
@@ -53,6 +54,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatMode
   gRK3588TokenSpaceGuid.PcdFdtForceGop
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath
   gRK3588TokenSpaceGuid.PcdComboPhy0Mode
   gRK3588TokenSpaceGuid.PcdComboPhy1Mode
   gRK3588TokenSpaceGuid.PcdComboPhy2Mode

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c

@@ -1,12 +1,13 @@
 /** @file
  *
  *  Copyright (c) 2020, Jeremy Linton
- *  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+ *  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
  **/
 
+#include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
 #include <Library/RockchipPlatformLib.h>
 #include <Library/UefiRuntimeServicesTableLib.h>
@@ -49,12 +50,13 @@ SetupConfigTableVariables (
   VOID
   )
 {
-  UINTN       Size;
-  UINT32      Var32;
-  UINT8       Var8;
-  EFI_STATUS  Status;
-  UINTN       Index;
-  UINT32      FirstFdtCompatModeSupported;
+  UINTN                            Size;
+  UINT32                           Var32;
+  UINT8                            Var8;
+  EFI_STATUS                       Status;
+  UINTN                            Index;
+  UINT32                           FirstFdtCompatModeSupported;
+  FDT_OVERRIDE_PATH_VARSTORE_DATA  FdtOverridePath;
 
   Size   = sizeof (UINT32);
   Status = gRT->GetVariable (
@@ -147,4 +149,57 @@ SetupConfigTableVariables (
     Status = PcdSet8S (PcdFdtSupportOverrides, FixedPcdGet8 (PcdFdtSupportOverridesDefault));
     ASSERT_EFI_ERROR (Status);
   }
+
+  Size   = sizeof (UINT8);
+  Status = gRT->GetVariable (
+                  L"FdtOverrideFixup",
+                  &gRK3588DxeFormSetGuid,
+                  NULL,
+                  &Size,
+                  &Var8
+                  );
+  if (EFI_ERROR (Status)) {
+    Status = PcdSet8S (PcdFdtOverrideFixup, FixedPcdGet8 (PcdFdtOverrideFixupDefault));
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  Size   = sizeof (FDT_OVERRIDE_PATH_VARSTORE_DATA);
+  Status = gRT->GetVariable (
+                  L"FdtOverrideBasePath",
+                  &gRK3588DxeFormSetGuid,
+                  NULL,
+                  &Size,
+                  &FdtOverridePath
+                  );
+  if (EFI_ERROR (Status) || (FdtOverridePath.Path[0] == L' ')) {
+    if (FixedPcdGetSize (PcdFdtOverrideBasePathDefault) <= Size) {
+      Status = PcdSetPtrS (PcdFdtOverrideBasePath, &Size, FixedPcdGetPtr (PcdFdtOverrideBasePathDefault));
+    } else {
+      ASSERT (FALSE);
+      ZeroMem (&FdtOverridePath, Size);
+      Status = PcdSetPtrS (PcdFdtOverrideBasePath, &Size, &FdtOverridePath);
+    }
+
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  Size   = sizeof (FDT_OVERRIDE_PATH_VARSTORE_DATA);
+  Status = gRT->GetVariable (
+                  L"FdtOverrideOverlayPath",
+                  &gRK3588DxeFormSetGuid,
+                  NULL,
+                  &Size,
+                  &FdtOverridePath
+                  );
+  if (EFI_ERROR (Status) || (FdtOverridePath.Path[0] == L' ')) {
+    if (FixedPcdGetSize (PcdFdtOverrideOverlayPathDefault) <= Size) {
+      Status = PcdSetPtrS (PcdFdtOverrideOverlayPath, &Size, FixedPcdGetPtr (PcdFdtOverrideOverlayPathDefault));
+    } else {
+      ASSERT (FALSE);
+      ZeroMem (&FdtOverridePath, Size);
+      Status = PcdSetPtrS (PcdFdtOverrideOverlayPath, &Size, &FdtOverridePath);
+    }
+
+    ASSERT_EFI_ERROR (Status);
+  }
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf

@@ -108,6 +108,12 @@
   gRK3588TokenSpaceGuid.PcdFdtForceGop
   gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePathDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPathDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath
 
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput
   gRK3588TokenSpaceGuid.PcdCoolingFanState

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni

@@ -258,11 +258,43 @@
 #string STR_FDT_COMPAT_MODE_MAINLINE                       #language en-US "Mainline"
 
 #string STR_FDT_FORCE_GOP_PROMPT                           #language en-US "Force UEFI GOP Display"
-#string STR_FDT_FORCE_GOP_HELP                             #language en-US "This option allows using the basic display output provided by UEFI GOP (HDMI/DP/DSI) on Linux kernels older than 6.13, which lack native driver support."
+#string STR_FDT_FORCE_GOP_HELP                             #language en-US "This option allows using the basic display output provided by UEFI GOP (HDMI/DP/DSI) on older Linux kernels, which lack native driver support."
 
 #string STR_FDT_SUPPORT_OVERRIDES_PROMPT                   #language en-US "Support DTB override & overlays"
 #string STR_FDT_SUPPORT_OVERRIDES_HELP                     #language en-US "Enable or disable support for overriding the firmware-provided DTB and installing overlays.\n\nCheck firmware documentation for more details."
 
+#string STR_FDT_OVERRIDE_SUBTITLE                          #language en-US "DTB Override"
+
+#string STR_FDT_OVERRIDE_FIXUP_PROMPT                      #language en-US "Firmware Fix-ups"
+#string STR_FDT_OVERRIDE_FIXUP_HELP                        #language en-US "Enable or disable firmware fix-ups for the DTB override."
+
+#string STR_FDT_OVERRIDE_BASE_PATH_PROMPT                  #language en-US "Preferred Base DTB Path"
+#string STR_FDT_OVERRIDE_BASE_PATH_HELP                    #language en-US "Enter the preferred file or directory path for the base DTB override, relative to the file system root.\n\n"
+                                                                           "Once a boot device is selected, the firmware will scan all the supported file systems on it (FAT, ext4) and try to load the specified override.\n\n"
+                                                                           "- If a directory path is specified, the platform FDT file name will be appended to it (<PLATFORM-DT-NAME>).\n"
+                                                                           "- If a file path is specified, it will be used as is.\n"
+                                                                           "- If no override exists, the firmware-provided DTB will be used instead.\n\n"
+                                                                           "Examples:\n"
+                                                                           " \\dtbs\n"
+                                                                           " \\dtbs\\my-board.dtb\n\n"
+                                                                           "Default alternative paths:\n"
+                                                                           " \\dtb\n"
+                                                                           " \\dtb\\base\n"
+                                                                           " \\dtb\\rockchip\n\n"
+                                                                           "To reset this option to the default value, set it to a space character, save and reboot."
+
+#string STR_FDT_OVERRIDE_OVERLAY_PATH_PROMPT               #language en-US "Preferred Overlays Path"
+#string STR_FDT_OVERRIDE_OVERLAY_PATH_HELP                 #language en-US "Enter the preferred directory path for the DTB overlays, relative to the file system root.\n\n"
+                                                                           "Once a boot device is selected, the firmware will scan all the supported file systems on it (FAT, ext4) and try to load all overlays in the specified directory.\n\n"
+                                                                           "- If the installation of an overlay fails, all other overlays will be discarded.\n\n"
+                                                                           "Examples:\n"
+                                                                           " \\my-overlays\n"
+                                                                           " \\dtbs\\overlays\n\n"
+                                                                           "Default alternative paths:\n"
+                                                                           " \\dtb\\overlays\n"
+                                                                           " \\dtb\\overlays\\<PLATFORM-DT-NAME>\n\n"
+                                                                           "To reset this option to the default value, set it to a space character, save and reboot."
+
 /*
  * Cooling fan configuration
  */

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr

@@ -213,6 +213,21 @@ formset
       name  = FdtSupportOverrides,
       guid  = RK3588DXE_FORMSET_GUID;
 
+    efivarstore UINT8,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FdtOverrideFixup,
+      guid  = RK3588DXE_FORMSET_GUID;
+
+    efivarstore FDT_OVERRIDE_PATH_VARSTORE_DATA,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FdtOverrideBasePath,
+      guid  = RK3588DXE_FORMSET_GUID;
+
+    efivarstore FDT_OVERRIDE_PATH_VARSTORE_DATA,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FdtOverrideOverlayPath,
+      guid  = RK3588DXE_FORMSET_GUID;
+
     efivarstore COOLING_FAN_STATE_VARSTORE_DATA,
       attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
       name  = CoolingFanState,
@@ -852,6 +867,38 @@ formset
             option text = STRING_TOKEN(STR_DISABLED), value = FALSE, flags = 0;
             option text = STRING_TOKEN(STR_ENABLED), value = TRUE, flags = 0;
           endoneof;
+
+          suppressif ideqval FdtSupportOverrides.State == 0;
+            subtitle text = STRING_TOKEN(STR_NULL_STRING);
+            subtitle text = STRING_TOKEN(STR_FDT_OVERRIDE_SUBTITLE);
+
+            oneof varid = FdtOverrideFixup,
+              prompt      = STRING_TOKEN(STR_FDT_OVERRIDE_FIXUP_PROMPT),
+              help        = STRING_TOKEN(STR_FDT_OVERRIDE_FIXUP_HELP),
+              flags       = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED,
+              default     = FixedPcdGet8 (PcdFdtOverrideFixupDefault),
+              option text = STRING_TOKEN(STR_DISABLED), value = FALSE, flags = 0;
+              option text = STRING_TOKEN(STR_ENABLED), value = TRUE, flags = 0;
+            endoneof;
+
+            subtitle text = STRING_TOKEN(STR_NULL_STRING);
+
+            string varid = FdtOverrideBasePath.Path,
+              prompt  = STRING_TOKEN(STR_FDT_OVERRIDE_BASE_PATH_PROMPT),
+              help    = STRING_TOKEN(STR_FDT_OVERRIDE_BASE_PATH_HELP),
+              flags   = INTERACTIVE | RESET_REQUIRED,
+              minsize = 0,
+              maxsize = FDT_OVERRIDE_PATH_MAX_LEN,
+            endstring;
+
+            string varid = FdtOverrideOverlayPath.Path,
+              prompt  = STRING_TOKEN(STR_FDT_OVERRIDE_OVERLAY_PATH_PROMPT),
+              help    = STRING_TOKEN(STR_FDT_OVERRIDE_OVERLAY_PATH_HELP),
+              flags   = INTERACTIVE | RESET_REQUIRED,
+              minsize = 0,
+              maxsize = FDT_OVERRIDE_PATH_MAX_LEN,
+            endstring;
+          endif;
         endif;
     endform;
 

edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h

@@ -89,6 +89,12 @@ typedef struct {
   UINT8    State;
 } FDT_SUPPORT_OVERRIDES_VARSTORE_DATA;
 
+#define FDT_OVERRIDE_PATH_MAX_LEN   254
+#define FDT_OVERRIDE_PATH_MAX_SIZE  255
+typedef struct {
+  CHAR16    Path[FDT_OVERRIDE_PATH_MAX_SIZE];
+} FDT_OVERRIDE_PATH_VARSTORE_DATA;
+
 #define COOLING_FAN_STATE_DISABLED  0
 #define COOLING_FAN_STATE_ENABLED   1
 typedef struct {

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c

@@ -5,6 +5,7 @@
  *  Copyright (c) 2023, David Gwynne <david@gwynne.id.au>
  *  Copyright (c) 2023, Jared McNeill <jmcneill@invisible.ca>
  *  Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
+ *  Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
@@ -18,100 +19,85 @@
 #include <Library/CruLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/PcdLib.h>
+#include <VarStoreData.h>
 
-#define PCIE30_PHY_GRF  0xfd5b8000
-/* PCIEPHY_GRF */
-#define GRF_PCIE30_PHY_CON(n)       (PCIE30_PHY_GRF + 0x0000 + (n) * 0x4)         /* 0 .. 9 */
-#define GRF_PCIE30_PHY_STATUS(n)    (PCIE30_PHY_GRF + 0x0080 + (n) * 0x4)         /* 0 .. 2 */
-#define GRF_PCIE30_PHY_PRT0_CON(n)  (PCIE30_PHY_GRF + 0x0100 + (n) * 0x4)         /* 0 .. 39 */
-/* CON1 and CON9 */
-#define GRF_PCIE30PHY_DA_OCM_MASK  BIT15
-#define GRF_PCIE30PHY_DA_OCM       BIT15
-/* CON5 */
-#define GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT  0
-#define GRF_PCIE30PHY_LANE0_LINK_NUM_MASK   (0xfU << GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT)
-/* CON6 */
-#define GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT  0
-#define GRF_PCIE30PHY_LANE1_LINK_NUM_MASK   (0xfU << GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT)
+#define PHP_GRF_BASE       0xfd5b0000
+#define PCIE3PHY_GRF_BASE  0xfd5b8000
 
-/* STATUS0 */
-#define GRF_PCIE30PHY_SRAM_INIT_DONE  BIT14
+/* PHP_GRF */
+#define PHP_GRF_PCIESEL_CON  0x100
 
-#define SOFTRST_INDEX  27
-#define SOFTRST_BIT    14
+/* PCIE3PHY_GRF */
+#define PCIE3PHY_GRF_CMN_CON0      0x0
+#define PCIE3PHY_GRF_PHY0_STATUS1  0x904
+#define PCIE3PHY_GRF_PHY1_STATUS1  0xa04
+#define PCIE3PHY_SRAM_INIT_DONE(reg)  ((reg & BIT0) != 0)
 
-STATIC
-VOID
-GrfUpdateRegister (
-  IN EFI_PHYSICAL_ADDRESS  Reg,
-  IN UINT32                Mask,
-  IN UINT32                Val
-  )
-{
-  ASSERT ((Mask & ~0xFFFF) == 0);
-  ASSERT ((Val & ~0xFFFF) == 0);
-  ASSERT ((Mask & Val) == Val);
-
-  MmioWrite32 (Reg, (Mask << 16) | Val);
-}
+STATIC EFI_STATUS  mInitStatus = EFI_NOT_READY;
 
 EFI_STATUS
 Pcie30PhyInit (
   VOID
   )
 {
-  // UINTN Retry;
+  UINT8   Mode;
+  UINT32  Reg;
+  UINTN   Retry;
+
+  if (mInitStatus != EFI_NOT_READY) {
+    return mInitStatus;
+  }
+
+  Mode = PcdGet8 (PcdPcie30PhyMode);
 
   DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n"));
-  DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", PcdGet8 (PcdPcie30PhyMode)));
+  DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", Mode));
 
-  // MicroSecondDelay(100000);
-
-  /* Disable power domain */
+  /* Enable power domain */
   MmioWrite32 (0xFD8D8150, 0x1 << 23 | 0x1 << 21);  // PD_PCIE & PD_PHP
 
-  /* Phy mode: from pcd Pcie30PhyMode */
-  MmioWrite32 (GRF_PCIE30_PHY_CON (0), (0x7 << 16) | PcdGet8 (PcdPcie30PhyMode));
+  /* Phy mode */
+  Reg = Mode;
+  MmioWrite32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_CMN_CON0, (0x7 << 16) | Reg);
 
+  /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+  Reg &= 0x3;
+  if (Reg) {
+    MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, (0x3 << 16) | Reg);
+  }
+
+  /* Assert PHY Reset */
   MmioWrite32 (0xFD7C8A00, (0x1 << 10) | (0x1 << 26));
+  MicroSecondDelay (1);
 
   /* Deassert PCIe PMA output clamp mode */
-  MmioWrite32 (GRF_PCIE30_PHY_CON (0), (0x1 << 8) | (0x1 << 24));
+  MmioWrite32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_CMN_CON0, (0x1 << 8) | (0x1 << 24));
 
   /* Deassert PHY Reset */
   MmioWrite32 (0xFD7C8A00, (0x1 << 26));
 
-  // /* Enable clocks */
-  // PmuCruEnableClock (2, 13);
-  // PmuCruEnableClock (2, 14);
-  // CruEnableClock (33, 8);
+  for (Retry = 500; Retry > 0; Retry--) {
+    Reg = MmioRead32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_PHY0_STATUS1);
+    if (Mode == PCIE30_PHY_MODE_AGGREGATION) {
+      Reg &= MmioRead32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_PHY1_STATUS1);
+    }
 
-  // /* Assert reset */
-  // CruAssertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
-  // gBS->Stall (1000);
+    if (PCIE3PHY_SRAM_INIT_DONE (Reg)) {
+      break;
+    }
 
-  // MicroSecondDelay (1);
+    MicroSecondDelay (100);
+  }
 
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (9), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (5), GRF_PCIE30PHY_LANE0_LINK_NUM_MASK, PCIE30PHY_LANE0_LINK_NUM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (6), GRF_PCIE30PHY_LANE1_LINK_NUM_MASK, PCIE30PHY_LANE1_LINK_NUM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (1), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
-
-  // /* De-assert reset */
-  // CruDeassertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
-
-  // for (Retry = 500; Retry > 0; Retry--) {
-  //     MicroSecondDelay (100);
-
-  //     if ((MmioRead32 (GRF_PCIE30_PHY_STATUS (0)) & GRF_PCIE30PHY_SRAM_INIT_DONE) != 0) {
-  //         break;
-  //     }
-  // }
-  // if (Retry == 0) {
-  //     DEBUG ((DEBUG_WARN, "PCIe30: Failed to enable PCIe 3.0 PHY\n"));
-  //     return EFI_TIMEOUT;
-  // }
+  if (Retry == 0) {
+    DEBUG ((DEBUG_WARN, "PCIe30: PHY init failed\n"));
+    mInitStatus = EFI_TIMEOUT;
+    goto Exit;
+  }
 
   DEBUG ((DEBUG_INFO, "PCIe30: PHY init complete\n"));
-  return EFI_SUCCESS;
+  mInitStatus = EFI_SUCCESS;
+
+Exit:
+  return mInitStatus;
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c

@@ -3,7 +3,7 @@
   Copyright 2017, 2020 NXP
   Copyright 2021-2023, Jared McNeill <jmcneill@invisible.ca>
   Copyright 2023, Molly Sophia <mollysophia379@gmail.com>
-  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -577,6 +577,7 @@ InitializePciHost (
   EFI_PHYSICAL_ADDRESS  ApbBase  = PCIE_APB_BASE (Segment);
   EFI_PHYSICAL_ADDRESS  DbiBase  = PCIE_DBI_BASE (Segment);
   EFI_PHYSICAL_ADDRESS  PcieBase = PCIE_CFG_BASE (Segment);
+  EFI_STATUS            Status;
   UINTN                 Retry;
   UINT32                LinkSpeed;
   UINT32                LinkWidth;
@@ -622,7 +623,10 @@ InitializePciHost (
 
   if ((Segment == PCIE_SEGMENT_PCIE30X4) || (Segment == PCIE_SEGMENT_PCIE30X2)) {
     /* Configure PCIe 3.0 PHY */
-    Pcie30PhyInit ();
+    Status = Pcie30PhyInit ();
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
   }
 
   /* Combo PHY for PCIe 2.0 is configured earlier by RK3588Dxe */

edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec

@@ -51,6 +51,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatModeDefault|0|UINT32|0x00010351
   gRK3588TokenSpaceGuid.PcdFdtForceGopDefault|0|UINT8|0x00010352
   gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault|0|UINT8|0x00010353
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault|0|UINT8|0x00010354
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePathDefault|L""|VOID*|0x00010355
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPathDefault|L""|VOID*|0x00010356
 
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|FALSE|BOOLEAN|0x10401
 
@@ -120,6 +123,19 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatMode|0|UINT32|0x00000351
   gRK3588TokenSpaceGuid.PcdFdtForceGop|0|UINT8|0x00000352
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|0|UINT8|0x00000353
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup|0|UINT8|0x00000354
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath|{ 0x0 }|FDT_OVERRIDE_PATH_VARSTORE_DATA|0x00000355 {
+    <Packages>
+      Silicon/Rockchip/RK3588/RK3588.dec
+    <HeaderFiles>
+      VarStoreData.h
+  }
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath|{ 0x0 }|FDT_OVERRIDE_PATH_VARSTORE_DATA|0x00000356 {
+    <Packages>
+      Silicon/Rockchip/RK3588/RK3588.dec
+    <HeaderFiles>
+      VarStoreData.h
+  }
 
   gRK3588TokenSpaceGuid.PcdCoolingFanState|0|UINT32|0x00000401
   gRK3588TokenSpaceGuid.PcdCoolingFanSpeed|0|UINT32|0x00000402

edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc

@@ -286,6 +286,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatModeDefault|$(FDT_COMPAT_MODE_MAINLINE)
   gRK3588TokenSpaceGuid.PcdFdtForceGopDefault|FALSE
   gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault|FALSE
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault|TRUE
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePathDefault|L""
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPathDefault|L""
 
   #
   # Display support flags and default values
@@ -373,6 +376,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatMode|L"FdtCompatMode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtCompatModeDefault
   gRK3588TokenSpaceGuid.PcdFdtForceGop|L"FdtForceGop"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtForceGopDefault
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|L"FdtSupportOverrides"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup|L"FdtOverrideFixup"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath|L"FdtOverrideBasePath"|gRK3588DxeFormSetGuid|0x0|{ 0x0 }
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath|L"FdtOverrideOverlayPath"|gRK3588DxeFormSetGuid|0x0|{ 0x0 }
 
   #
   # Cooling Fan

edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc

@@ -699,6 +699,7 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
 !endif
   }
   FatPkg/EnhancedFatDxe/Fat.inf
+!include Features/Ext4Pkg/Ext4.dsc.inc
   MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
   #