Switch devicetree-rebasing to kernel.googlesource.com mirror

CI builds have been failing lately with:
Error: fatal: unable to access
'https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/':
Failed to connect to git.kernel.org port 443 after
134198 ms: Couldn't connect to server

Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

.gitmodules

@@ -13,4 +13,7 @@
 	branch = rk3588
 [submodule "devicetree/mainline/upstream"]
 	path = devicetree/mainline/upstream
-	url = https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
+	url = https://kernel.googlesource.com/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
+[submodule "edk2-platforms"]
+	path = edk2-platforms
+	url = https://github.com/tianocore/edk2-platforms.git

README.md

@@ -69,7 +69,7 @@ Note that this list is subject to change at any time as devices gain better supp
 ### Mainline compatibility mode
 | OS | Version | Tested/supported hardware | Notes |
 | --- | --- | --- | --- |
-| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41<br> - Fedora Workstation Rawhide | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.13 lack HDMI output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
+| Generic upstream Linux | Kernel 6.10 or newer.<br> Tested with:<br> - Ubuntu 24.10<br> - Fedora Workstation 41<br> - Fedora Workstation Rawhide | Platform and kernel version dependent, see [Collabora's RK3588 upstream status](https://gitlab.collabora.com/hardware-enablement/rockchip-3588/notes-for-rockchip-3588/-/blob/main/mainline-status.md). | * Kernels older than 6.15 lack display output. To work around this, see: [Device Tree configuration](#device-tree-configuration). |
 
 > [!NOTE]
 > Mainline support is only available on [Platinum](#platinum) platforms.
@@ -120,7 +120,7 @@ If your platform is not yet supported, using an image meant for another device i
 ## 3. Flash the firmware
 UEFI can be flashed to either an SPI NOR flash, SD card or eMMC module:
 * For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
-* For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
+* For SPI NOR or soldered eMMC, instructions can be found at: <https://docs.radxa.com/en/rock5/lowlevel-development/bootloader_spi_flash>.
 
   In short, you can flash the image from Linux booted on the device or by using RKDevTool on another computer. The latter requires entering Maskrom mode on the device. The way to do this slightly varies across platforms, refer to your vendor documentation.
 
@@ -171,22 +171,31 @@ The firmware provides two compatibility modes:
 [Platinum](#platinum) platforms will have the `Mainline` option enabled by default, while [Bronze](#bronze) ones will fall back to `Vendor`.
 
 > [!TIP]
-> In `Mainline` mode with generic Linux kernels older than 6.13, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
+> In `Mainline` mode with generic Linux kernels older than 6.15, the HDMI output will not be usable. To use the UEFI-initialized display instead, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and enable `Force UEFI GOP Display`. Note that GPU acceleration cannot work in this mode.
 
 ### Custom Device Tree Blob (DTB) override and overlays
-It is also possible to provide a custom DTB and overlays. To enable this, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
+It is also possible to provide a custom DTB and overlays. This is useful in cases where the firmware DTB is outdated, does not match the kernel used or for testing purposes. To enable overrides, go to `Device Manager`->`Rockchip Platform Configuration`->`ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
 
-The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases, this will be the first FAT32 EFI System Partition.
+The firmware will now look for overrides in all supported file systems / partitions (FAT, ext4) on the selected boot device.
 
-**Important:** The `dtb` directory must be placed at the root of the partition. It should not be inside any sub-directory.
+**Important:**
+* The paths below are relative to the root of the partition. They must not be inside any sub-directory.
+* All overrides (base DTB and overlays) must be stored within a single partition. Using a base DTB from one partition and overlays from another is not allowed.
 
-* The base DTB must be located at `\dtb\base\<PLATFORM-DT-NAME>.dtb`.
+The base DTB can be placed in:
+* `\dtb`
+* `\dtb\base`
+* `\dtb\rockchip` - Fedora images have the kernel DTBs in this location on the second ext4 boot partition.
 
-* The overlays can be placed in:
-  * `\dtb\overlays` - will be applied first, regardless of the platform.
-  * `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+and must have the `<PLATFORM-DT-NAME>.dtb` file name.
 
-  and must have the `.dtbo` extension.
+The overlays can be placed in:
+* `\dtb\overlays` - will be applied first, regardless of the platform.
+* `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+
+and must have the `.dtbo` extension.
+
+In addition to the default paths above, it is possible to specify custom ones via the `Preferred Base DTB Path` and `Preferred Overlays Path` setup options in the menu described above.
 
 `<PLATFORM-DT-NAME>` can be:
 | Name                                    | Platform                      |
@@ -214,15 +223,16 @@ The firmware will now look for overrides in the partition of a selected boot opt
 | `rk3588s-nanopi-m6`                     | NanoPi M6                     |
 | `rk3588-hinlink-h88k`                   | H88K                          |
 
-In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.
+**Notes:**
+* The firmware applies some fix-ups to the DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied when providing overrides by other means, such as the Grub `devicetree` command.
 
-The firmware applies some fix-ups to its own DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied to a custom base DTB - overlays must be used instead.
+* In the absence of a base DTB override, the overlays are applied on top of the firmware-provided DTB.
 
-If the application of an overlay fails (e.g. due to it being invalid in regard to the base DTB), all overlays are discarded, including those that got applied up to that point.
+* If the application of an overlay fails (e.g. due to incompatibility with the base DTB), all other overlays are discarded.
 
-If the custom base DTB is invalid, the firmware-provided one will be passed to the OS instead.
+* If the base DTB override is invalid, the firmware-provided one will be passed to the OS instead.
 
-This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.
+* This process is logged to the [serial console](#advanced-troubleshooting). It is the only way to see potential errors.
 
 # Updating the firmware
 If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.

build.sh

@@ -11,10 +11,11 @@ function _help(){
     echo "  -r, --release MODE          Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
     echo "  -t, --toolchain TOOLCHAIN   Set toolchain, default is 'GCC'."
     echo "  --open-tfa ENABLE           Use open-source TF-A submodule. Default: ${OPEN_TFA}"
-    echo "  -C, --clean                 Clean workspace and output."
-    echo "  -D, --distclean             Clean up all files that are not in repo."
     echo "  --tfa-flags \"FLAGS\"         Flags appended to open TF-A build process."
     echo "  --edk2-flags \"FLAGS\"        Flags appended to the EDK2 build process."
+    echo "  --skip-patchsets            Skip applying upstream submodule patchsets during development."
+    echo "  -C, --clean                 Clean workspace and output."
+    echo "  -D, --distclean             Clean up all files that are not in repo."
     echo "  -h, --help                  Show this help."
     echo
     exit "${1}"
@@ -22,6 +23,59 @@ function _help(){
 
 function _error() { echo "${@}" >&2; exit 1; }
 
+function apply_patchset() {
+    ${SKIP_PATCHSETS} && return 0
+
+    local patches_dir="$1"
+    local target_dir="$2"
+
+    [ ! -d "${patches_dir}" ] && return 0
+
+    if [ ! -d "${target_dir}" ]; then
+        echo "Patchset target directory does not exist: ${target_dir}"
+        return 1
+    fi
+
+    echo "Checking patchset ${patches_dir} for ${target_dir}"
+
+    local patchset_name=$(basename "${patches_dir}")
+    local patchset_marker="${target_dir}/.patchset_${patchset_name}"
+
+    if [ ! -f "${patchset_marker}" ] || [ "${patches_dir}" -nt "${patchset_marker}" ]; then
+        echo "Patchset needs to be (re)applied"
+        if ! git -C "${target_dir}" reset --hard || ! git -C "${target_dir}" clean -xfd; then
+            echo "Failed to reset git repository - aborting"
+            return 1
+        fi
+    else
+        echo "Patchset already applied - skipping"
+        return 0
+    fi
+
+    local patch_file
+    local patch_count=0
+
+    for patch_file in "${patches_dir}"/*.patch; do
+        [ -f "${patch_file}" ] || continue
+
+        local patch_name=$(basename "${patch_file}")
+        echo "Patch ${patch_count}: ${patch_name}"
+
+        if patch -p1 -d "${target_dir}" < "${patch_file}"; then
+            echo "  Successfully applied"
+            ((patch_count++))
+        else
+            echo "  Failed to apply - aborting"
+            return 1
+        fi
+    done
+
+    touch "${patchset_marker}"
+
+    echo "Patchset summary: ${patch_count} applied"
+    return 0
+}
+
 function _build_idblock() {
     echo " => Building idblock.bin"
     pushd ${WORKSPACE}
@@ -58,7 +112,7 @@ function _build_fit() {
     BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}"
     BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}"
 
-    if [ ${OPEN_TFA} == 1 ]; then
+    if ${OPEN_TFA}; then
         BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf"
     fi
 
@@ -117,7 +171,9 @@ function _build(){
     #
     # Build TF-A
     #
-    if [ ${OPEN_TFA} == 1 ]; then
+    if ${OPEN_TFA}; then
+        apply_patchset "${ROOTDIR}/arm-trusted-firmware-patches" "${ROOTDIR}/arm-trusted-firmware" || exit 1
+
         pushd arm-trusted-firmware
 
         if [ ${RELEASE_TYPE} == "DEBUG" ]; then
@@ -134,11 +190,21 @@ function _build(){
     #
     # Build EDK2
     #
+    apply_patchset "${ROOTDIR}/edk2-patches" "${ROOTDIR}/edk2" || exit 1
+    apply_patchset "${ROOTDIR}/devicetree/mainline/patches" "${ROOTDIR}/devicetree/mainline/upstream" || exit 1
+
     [ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf"
 
     export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
     export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
-    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/devicetree:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
+    PACKAGES_PATH="${ROOTDIR}"
+    PACKAGES_PATH+=":${ROOTDIR}/devicetree"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-non-osi"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-platforms"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-rockchip"
+    PACKAGES_PATH+=":${ROOTDIR}/edk2-rockchip-non-osi"
+    export PACKAGES_PATH
 
     make -C "${ROOTDIR}/edk2/BaseTools"
     source "${ROOTDIR}/edk2/edksetup.sh"
@@ -176,9 +242,10 @@ typeset -u RELEASE_TYPE
 DEVICE=""
 RELEASE_TYPE=DEBUG
 TOOLCHAIN=GCC
-OPEN_TFA=1
+OPEN_TFA=true
 TFA_FLAGS=""
 EDK2_FLAGS=""
+SKIP_PATCHSETS=false
 CLEAN=false
 DISTCLEAN=false
 OUTDIR="${PWD}"
@@ -186,7 +253,7 @@ OUTDIR="${PWD}"
 #
 # Get options
 #
-OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $?
+OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,skip-patchsets,clean,distclean,help" -n build.sh -- "${@}") || _help $?
 eval set -- "${OPTS}"
 while true; do
     case "${1}" in
@@ -196,6 +263,7 @@ while true; do
         --open-tfa) OPEN_TFA="${2}"; shift 2 ;;
         --tfa-flags) TFA_FLAGS="${2}"; shift 2 ;;
         --edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;;
+        --skip-patchsets) SKIP_PATCHSETS=true; shift ;;
         -C|--clean) CLEAN=true; shift ;;
         -D|--distclean) DISTCLEAN=true; shift ;;
         -h|--help) _help 0; shift ;;

devicetree/mainline/rk3588-buzztv-p6.dts

@@ -60,6 +60,31 @@
 		pinctrl-0 = <&ir_receiver_pin>;
 	};
 
+	rfkill {
+		compatible = "rfkill-gpio";
+		label = "rfkill-pcie-wlan";
+		radio-type = "wlan";
+		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+	};
+
+	spdif_dit: spdif-dit {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	spdif_sound: spdif-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "SPDIF";
+
+		simple-audio-card,cpu {
+			sound-dai = <&spdif_tx1>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&spdif_dit>;
+		};
+	};
+
 	vcc12v_dcin: regulator-vcc12v-dcin {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc12v_dcin";
@@ -195,6 +220,11 @@
 };
 
 &hdmi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmim0_tx0_cec
+		     &hdmim1_tx0_hpd
+		     &hdmim0_tx0_scl
+		     &hdmim0_tx0_sda>;
 	status = "okay";
 };
 
@@ -210,7 +240,11 @@
 	};
 };
 
-&hdptxphy_hdmi0 {
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdptxphy0 {
 	status = "okay";
 };
 
@@ -340,6 +374,10 @@
 	};
 };
 
+&i2s5_8ch {
+ 	status = "okay";
+};
+
 /* RTL8852BE */
 &pcie2x1l0 {
 	pinctrl-names = "default";
@@ -394,6 +432,10 @@
 	};
 };
 
+&pd_gpu {
+ 	domain-supply = <&vdd_gpu_s0>;
+};
+
 &pinctrl {
 	hym8563 {
 		hym8563_int: hym8563-int {
@@ -503,6 +545,12 @@
 	status = "okay";
 };
 
+&spdif_tx1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spdif1m1_tx>;
+	status = "okay";
+};
+
 &spi2 {
 	status = "okay";
 	assigned-clocks = <&cru CLK_SPI2>;

devicetree/mainline/rk3588-friendlyelec-cm3588-nas-fixup.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-friendlyelec-cm3588-nas.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};

devicetree/mainline/rk3588-nanopc-t6-fixup.dts

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-nanopc-t6.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};

devicetree/mainline/rk3588-rock-5-itx-fixup.dts

@@ -6,6 +6,14 @@
 	/delete-node/ pcie-oscillator;
 };
 
+&hdmi1_sound {
+	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};
+
 /*
  * Remove the "pcie30_refclk" gated-fixed-clock to maintain compatibility
  * with kernels older than v6.13-rc1. It is backed by a GPIO regulator

devicetree/mainline/rk3588s-indiedroid-nova-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-indiedroid-nova.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-khadas-edge2-fixup.dts

@@ -251,10 +251,18 @@
 	};
 };
 
-&hdptxphy_hdmi0 {
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&hdptxphy0 {
 	status = "okay";
 };
 
+&i2s5_8ch {
+ 	status = "okay";
+};
+
 &vop_mmu {
 	status = "okay";
 };

devicetree/mainline/rk3588s-nanopi-r6c-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-nanopi-r6c.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-nanopi-r6s-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-nanopi-r6s.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

devicetree/mainline/rk3588s-rock-5a-fixup.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-rock-5a.dts"
+
+&hdmi0_sound {
+ 	status = "okay";
+};
+
+&i2s5_8ch {
+ 	status = "okay";
+};

edk2-patches/0001-MdePkg-BaseFdtLib-Add-more-wrappers.patch

@@ -0,0 +1,103 @@
+From 7f9f0713b06cadff7071271c76d10a2091c8823d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Mario=20B=C4=83l=C4=83nic=C4=83?=
+ <mariobalanica02@gmail.com>
+Date: Fri, 5 Dec 2025 14:02:15 +0200
+Subject: [PATCH] MdePkg/BaseFdtLib: Add more wrappers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add FDT_HEADER field accessors and FdtOverlayApply() wrapper.
+
+Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
+---
+ MdePkg/Include/Library/FdtLib.h    | 29 ++++++++++++++++++++++++++++-
+ MdePkg/Library/BaseFdtLib/FdtLib.c | 18 ++++++++++++++++++
+ 2 files changed, 46 insertions(+), 1 deletion(-)
+
+diff --git a/MdePkg/Include/Library/FdtLib.h b/MdePkg/Include/Library/FdtLib.h
+index a7f63f3d5a..16e8179af4 100644
+--- a/MdePkg/Include/Library/FdtLib.h
++++ b/MdePkg/Include/Library/FdtLib.h
+@@ -181,7 +181,16 @@ typedef struct {
+ 
+ #define FdtGetHeader(Fdt, Field) \
+   (Fdt32ToCpu (((const FDT_HEADER *)(Fdt))->Field))
+-#define FdtTotalSize(Fdt)  (FdtGetHeader ((Fdt), TotalSize))
++#define FdtMagic(Fdt)            (FdtGetHeader ((Fdt), Magic))
++#define FdtTotalSize(Fdt)        (FdtGetHeader ((Fdt), TotalSize))
++#define FdtOffsetDtStruct(Fdt)   (FdtGetHeader ((Fdt), OffsetDtStruct))
++#define FdtOffsetDtStrings(Fdt)  (FdtGetHeader ((Fdt), OffsetDtStrings))
++#define FdtOffsetMemRsvmap(Fdt)  (FdtGetHeader ((Fdt), OffsetMemRsvmap))
++#define FdtVersion(Fdt)          (FdtGetHeader ((Fdt), Version))
++#define FdtLastCompVersion(Fdt)  (FdtGetHeader ((Fdt), LastCompVersion))
++#define FdtBootCpuidPhys(Fdt)    (FdtGetHeader ((Fdt), BootCpuidPhys))
++#define FdtSizeDtStrings(Fdt)    (FdtGetHeader ((Fdt), SizeDtStrings))
++#define FdtSizeDtStruct(Fdt)     (FdtGetHeader ((Fdt), SizeDtStruct))
+ 
+ #define FdtForEachSubnode(Node, Fdt, Parent) \
+   for (Node = FdtFirstSubnode (Fdt, Parent); \
+@@ -191,6 +200,9 @@ typedef struct {
+ #define FdtSetPropString(Fdt, NodeOffset, Name, String) \
+   FdtSetProp ((Fdt), (NodeOffset), (Name), (String), AsciiStrLen (String) + 1)
+ 
++#define FdtSetPropEmpty(Fdt, NodeOffset, Name) \
++  FdtSetProp ((Fdt), (NodeOffset), (Name), NULL, 0)
++
+ /**
+   Convert UINT16 data of the FDT blob to little-endian
+ 
+@@ -960,6 +972,21 @@ FdtGetPhandle (
+   IN INT32       NodeOffset
+   );
+ 
++/**
++  Applies a DT overlay on a base DT.
++
++  @param[in] Fdt            The pointer to FDT blob.
++  @param[in] Fdto           The pointer to FDT overlay blob.
++
++  @return 0 on success, or negative error code.
++**/
++INT32
++EFIAPI
++FdtOverlayApply (
++  IN VOID  *Fdt,
++  IN VOID  *Fdto
++  );
++
+ /* Debug functions. */
+ CONST
+ CHAR8
+diff --git a/MdePkg/Library/BaseFdtLib/FdtLib.c b/MdePkg/Library/BaseFdtLib/FdtLib.c
+index 3dacfbee45..8c986650dc 100644
+--- a/MdePkg/Library/BaseFdtLib/FdtLib.c
++++ b/MdePkg/Library/BaseFdtLib/FdtLib.c
+@@ -918,6 +918,24 @@ FdtGetPhandle (
+   return fdt_get_phandle (Fdt, NodeOffset);
+ }
+ 
++/**
++  Applies a DT overlay on a base DT.
++
++  @param[in] Fdt            The pointer to FDT blob.
++  @param[in] Fdto           The pointer to FDT overlay blob.
++
++  @return 0 on success, or negative error code.
++**/
++INT32
++EFIAPI
++FdtOverlayApply (
++  IN VOID  *Fdt,
++  IN VOID  *Fdto
++  )
++{
++  return fdt_overlay_apply (Fdt, Fdto);
++}
++
+ /* Debug functions. */
+ CONST
+ CHAR8
+-- 
+2.39.1.windows.1
+

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopOpRomOverride.c

@@ -0,0 +1,213 @@
+/** @file
+ *
+ *  AMD GOP OpROM override
+ *
+ *  Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <Protocol/DriverFamilyOverride.h>
+#include <Protocol/LoadedImage.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+STATIC CONST EFI_GUID  mAmdGopDriverGuids[] = {
+  { 0x62c34cea, 0xa08d, 0x4676, { 0x81, 0xe5, 0xf1, 0x6b, 0x0e, 0xe2, 0x2f, 0x22 }
+  }, // AmdGopPreSoc15Dxe.inf
+  { 0x92f10585, 0xfb63, 0x430f, { 0x81, 0x88, 0x71, 0xfe, 0xeb, 0x2d, 0xda, 0x5b }
+  }, // AmdGopPostSoc15Dxe.inf
+};
+
+STATIC
+UINT32
+AmdGopDriverFamilyOverrideGetVersion (
+  IN EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL  *This
+  )
+{
+  return MAX_UINT32;
+}
+
+STATIC EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL  mAmdGopDriverFamilyOverride = {
+  AmdGopDriverFamilyOverrideGetVersion
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+AmdGopUnloadImage (
+  IN  EFI_HANDLE  ImageHandle
+  )
+{
+  EFI_STATUS                 Status;
+  EFI_LOADED_IMAGE_PROTOCOL  *LoadedImage;
+  EFI_IMAGE_UNLOAD           OriginalUnload;
+
+  Status = gBS->HandleProtocol (
+                  ImageHandle,
+                  &gEfiLoadedImageProtocolGuid,
+                  (VOID **)&LoadedImage
+                  );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  Status = gBS->HandleProtocol (
+                  ImageHandle,
+                  &gEfiCallerIdGuid,
+                  (VOID **)&OriginalUnload
+                  );
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+    return Status;
+  }
+
+  gBS->UninstallMultipleProtocolInterfaces (
+         ImageHandle,
+         &gEfiDriverFamilyOverrideProtocolGuid,
+         &mAmdGopDriverFamilyOverride,
+         &gEfiCallerIdGuid,
+         OriginalUnload,
+         NULL
+         );
+
+  LoadedImage->Unload = OriginalUnload;
+
+  return LoadedImage->Unload (ImageHandle);
+}
+
+STATIC
+EFI_GUID *
+GetLoadedImageGuid (
+  IN EFI_LOADED_IMAGE_PROTOCOL  *LoadedImage
+  )
+{
+  EFI_DEVICE_PATH_PROTOCOL  *DevPathNode;
+  EFI_GUID                  *NameGuid;
+
+  if ((LoadedImage == NULL) || (LoadedImage->FilePath == NULL)) {
+    return NULL;
+  }
+
+  DevPathNode = LoadedImage->FilePath;
+
+  while (!IsDevicePathEnd (DevPathNode)) {
+    NameGuid = EfiGetNameGuidFromFwVolDevicePathNode (
+                 (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)DevPathNode
+                 );
+    if (NameGuid != NULL) {
+      return NameGuid;
+    }
+
+    DevPathNode = NextDevicePathNode (DevPathNode);
+  }
+
+  return NULL;
+}
+
+STATIC VOID  *mDriverBindingEventRegistration;
+
+STATIC
+VOID
+EFIAPI
+NotifyDriverBinding (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+  EFI_STATUS                 Status;
+  UINTN                      BufferSize;
+  EFI_HANDLE                 Handle;
+  EFI_LOADED_IMAGE_PROTOCOL  *LoadedImage;
+  EFI_GUID                   *LoadedImageGuid;
+  UINTN                      Index;
+
+  while (TRUE) {
+    BufferSize = sizeof (EFI_HANDLE);
+    Status     = gBS->LocateHandle (
+                        ByRegisterNotify,
+                        NULL,
+                        mDriverBindingEventRegistration,
+                        &BufferSize,
+                        &Handle
+                        );
+    if (EFI_ERROR (Status)) {
+      if (Status != EFI_NOT_FOUND) {
+        ASSERT_EFI_ERROR (Status);
+      }
+
+      break;
+    }
+
+    Status = gBS->HandleProtocol (
+                    Handle,
+                    &gEfiLoadedImageProtocolGuid,
+                    (VOID **)&LoadedImage
+                    );
+    if (EFI_ERROR (Status)) {
+      continue;
+    }
+
+    LoadedImageGuid = GetLoadedImageGuid (LoadedImage);
+    if (LoadedImageGuid == NULL) {
+      continue;
+    }
+
+    for (Index = 0; Index < ARRAY_SIZE (mAmdGopDriverGuids); Index++) {
+      if (!CompareGuid (LoadedImageGuid, &mAmdGopDriverGuids[Index])) {
+        continue;
+      }
+
+      DEBUG ((DEBUG_INFO, "%a: %g\n", gEfiCallerBaseName, LoadedImageGuid));
+
+      Status = gBS->InstallMultipleProtocolInterfaces (
+                      &Handle,
+                      &gEfiDriverFamilyOverrideProtocolGuid,
+                      &mAmdGopDriverFamilyOverride,
+                      NULL
+                      );
+      if (EFI_ERROR (Status)) {
+        ASSERT_EFI_ERROR (Status);
+        break;
+      }
+
+      if (LoadedImage->Unload != NULL) {
+        Status = gBS->InstallMultipleProtocolInterfaces (
+                        &Handle,
+                        &gEfiCallerIdGuid,
+                        LoadedImage->Unload,
+                        NULL
+                        );
+        if (EFI_ERROR (Status)) {
+          ASSERT_EFI_ERROR (Status);
+          break;
+        }
+
+        LoadedImage->Unload = AmdGopUnloadImage;
+      }
+    }
+  }
+}
+
+EFI_STATUS
+EFIAPI
+AmdGopOpRomOverrideInitialize (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  EfiCreateProtocolNotifyEvent (
+    &gEfiDriverBindingProtocolGuid,
+    TPL_CALLBACK,
+    NotifyDriverBinding,
+    NULL,
+    &mDriverBindingEventRegistration
+    );
+
+  return EFI_SUCCESS;
+}

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopOpRomOverrideDxe.inf

@@ -0,0 +1,40 @@
+#/** @file
+#
+#  AMD GOP OpROM override
+#
+#  Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AmdGopOpRomOverrideDxe
+  FILE_GUID                      = 261d0e39-4663-4f0f-94ad-2903b7bb31e1
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = AmdGopOpRomOverrideInitialize
+
+[Sources]
+  AmdGopOpRomOverride.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  DevicePathLib
+  UefiBootServicesTableLib
+  UefiLib
+  UefiDriverEntryPoint
+
+[Protocols]
+  gEfiDriverBindingProtocolGuid
+  gEfiDriverFamilyOverrideProtocolGuid
+  gEfiLoadedImageProtocolGuid
+
+[Depex]
+  TRUE

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopPostSoc15Dxe.inf

@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AMDGopPostSoc15Dxe
+  FILE_GUID                      = 92f10585-fb63-430f-8188-71feeb2dda5b
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.AARCH64]
+  PE32|AArch64/ARM64Gop_2_10.efi|*

edk2-rockchip-non-osi/Drivers/AMD/Gop/AmdGopPreSoc15Dxe.inf

@@ -0,0 +1,9 @@
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AMDGopPreSoc15Dxe
+  FILE_GUID                      = 62c34cea-a08d-4676-81e5-f16b0ee22f22
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+[Binaries.AARCH64]
+  PE32|AArch64/Arm64Gop_1_68.efi|*

edk2-rockchip-non-osi/Drivers/AMD/Gop/README.md

@@ -0,0 +1,19 @@
+# AMD AARCH64 Gop Driver
+
+## Important Notes
+
+- This driver should be considered "as is" and may not be supported with further updates, upgrades or bug fixes.
+- Contact info: James Huang  (James.Huang@amd.com), Plamen Belomorski (Plamen.Belomorski@amd.com).
+- When a headless GPU ROM image is found, return “unsupported” from Supported.
+
+## Pre-SOC15 Gop Driver
+
+**Supported Asic Device ID ranges:**
+
+(0x6880, 0x689f), (0x68A0, 0x68Bf), (0x68C0, 0x68Df), (0x68E0, 0x68FF), (0x9640, 0x964f), (0x9800, 0x980f), (0x9990, 0x99Af), (0x6700, 0x671f), (0x6720, 0x673f), (0x6740, 0x675f), (0x6840, 0x685f), (0x6760, 0x677f), (0x6780, 0x679f),  (0x6800, 0x681f),  (0x6820, 0x683f), (0x6600, 0x663f), (0x6660, 0x667f), (0x1304, 0x131d), (0x6640, 0x665f), (0x67a0, 0x67bf), (0x9830, 0x983f), (0x98b0, 0x98bf), (0x6900, 0x691f), (0x6920, 0x693f), (0x6960, 0x697f), (0x7300, 0x7304), (0x67C0, 0x67DF), (0x67E0, 0x67Ff), (0x6980, 0x699f), (0x6940, 0x695f), (0x9850, 0x985f), (0x9870, 0x988f), (0x98e0, 0x98ff), (0x9890, 0x98af), (0x98c0, 0x98df)
+
+## Post-SOC15 Gop Driver
+
+For the DIDs that are not supported in pre-SoC15 GOP, please use this Post-SoC15 GOP driver.
+
+https://www.amd.com/en/resources/support-articles/release-notes/RN-AAR.html

edk2-rockchip/Platform/Ameridroid/IndiedroidNova/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+  devicetree/mainline/rk3588s-indiedroid-nova-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/BuzzTV/PowerStation6/Library/RockchipPlatformLib/RockchipPlatformLib.c

@@ -329,8 +329,8 @@ HdmiTxIomux (
     case 0:
       GpioPinSetFunction (4, GPIO_PIN_PC1, 5); // hdmim0_tx0_cec
       GpioPinSetPull (4, GPIO_PIN_PC1, GPIO_PIN_PULL_NONE);
-      GpioPinSetFunction (1, GPIO_PIN_PA5, 5); // hdmim0_tx0_hpd
-      GpioPinSetPull (1, GPIO_PIN_PA5, GPIO_PIN_PULL_NONE);
+      GpioPinSetFunction (3, GPIO_PIN_PD4, 3); // hdmim1_tx0_hpd
+      GpioPinSetPull (3, GPIO_PIN_PD4, GPIO_PIN_PULL_NONE);
       GpioPinSetFunction (4, GPIO_PIN_PB7, 5); // hdmim0_tx0_scl
       GpioPinSetPull (4, GPIO_PIN_PB7, GPIO_PIN_PULL_NONE);
       GpioPinSetFunction (4, GPIO_PIN_PC0, 5); // hdmim0_tx0_sda

edk2-rockchip/Platform/FriendlyElec/NanoPC-CM3588-NAS/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts
+  devicetree/mainline/rk3588-friendlyelec-cm3588-nas-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
+  devicetree/mainline/rk3588-nanopc-t6-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts
+  devicetree/mainline/rk3588s-nanopi-r6c-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-nanopi-r6s.dts
+  devicetree/mainline/rk3588s-nanopi-r6s-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Platform/Radxa/ROCK5A/DeviceTree/Mainline.inf

@@ -14,7 +14,7 @@
   VERSION_STRING                 = 1.0
 
 [Sources]
-  devicetree/mainline/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+  devicetree/mainline/rk3588s-rock-5a-fixup.dts
 
 [Packages]
   MdePkg/MdePkg.dec

edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.c

@@ -1,6 +1,7 @@
 /** @file
 UEFI Component Name and Name2 protocol for OHCI driver.
 
+Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
 Copyright (c) 2013-2015 Intel Corporation.
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -166,9 +167,9 @@ OhciComponentNameGetControllerName (
   OUT CHAR16                       **ControllerName
   )
 {
-  EFI_STATUS           Status;
-  USB_OHCI_HC_DEV      *OhciDev;
-  EFI_USB_HC_PROTOCOL  *UsbHc;
+  EFI_STATUS            Status;
+  USB_OHCI_HC_DEV       *OhciDev;
+  EFI_USB2_HC_PROTOCOL  *Usb2Hc;
 
   //
   // This is a device driver, so ChildHandle must be NULL.
@@ -194,8 +195,8 @@ OhciComponentNameGetControllerName (
   //
   Status = gBS->OpenProtocol (
                   ControllerHandle,
-                  &gEfiUsbHcProtocolGuid,
-                  (VOID **)&UsbHc,
+                  &gEfiUsb2HcProtocolGuid,
+                  (VOID **)&Usb2Hc,
                   gOhciDriverBinding.DriverBindingHandle,
                   ControllerHandle,
                   EFI_OPEN_PROTOCOL_GET_PROTOCOL
@@ -204,7 +205,7 @@ OhciComponentNameGetControllerName (
     return Status;
   }
 
-  OhciDev = USB_OHCI_HC_DEV_FROM_THIS (UsbHc);
+  OhciDev = USB_OHCI_HC_DEV_FROM_THIS (Usb2Hc);
 
   return LookupUnicodeString2 (
            Language,

edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.h

@@ -2,6 +2,7 @@
 Provides the definition of Usb Hc Protocol and OHCI controller
 private data structure.
 
+Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
 Copyright (c) 2013-2016 Intel Corporation.
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -13,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 #include <Uefi.h>
 
-#include <Protocol/UsbHostController.h>
+#include <Protocol/Usb2HostController.h>
 #include <Library/DmaLib.h>
 
 #include <Guid/EventGroup.h>
@@ -62,7 +63,6 @@ typedef struct {
 
 struct _USB_OHCI_HC_DEV {
   UINTN                       Signature;
-  EFI_USB_HC_PROTOCOL         UsbHc;
   EFI_USB2_HC_PROTOCOL        Usb2Hc;
   UINT32                      UsbHcBaseAddress;
   HCCA_MEMORY_BLOCK           *HccaMemoryBlock;
@@ -87,174 +87,189 @@ struct _USB_OHCI_HC_DEV {
   OHCI_DEVICE_PROTOCOL        *Protocol;
 };
 
-#define USB_OHCI_HC_DEV_FROM_THIS(a)  CR(a, USB_OHCI_HC_DEV, UsbHc, USB_OHCI_HC_DEV_SIGNATURE)
+#define USB_OHCI_HC_DEV_FROM_THIS(a)  CR(a, USB_OHCI_HC_DEV, Usb2Hc, USB_OHCI_HC_DEV_SIGNATURE)
 
 //
 // Func List
 //
 
+/**
+  Retrieves the Host Controller capabilities.
+
+  @param  This           A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  MaxSpeed       Host controller data transfer speed.
+  @param  PortNumber     Number of the root hub ports.
+  @param  Is64BitCapable TRUE if controller supports 64-bit memory addressing,
+                         FALSE otherwise.
+
+  @retval EFI_SUCCESS           The host controller capabilities were retrieved successfully.
+  @retval EFI_INVALID_PARAMETER One of the input args was NULL.
+  @retval EFI_DEVICE_ERROR      An error was encountered while attempting to
+                                retrieve the capabilities.
+
+**/
+EFI_STATUS
+EFIAPI
+OhciGetCapability (
+  IN  EFI_USB2_HC_PROTOCOL  *This,
+  OUT UINT8                 *MaxSpeed,
+  OUT UINT8                 *PortNumber,
+  OUT UINT8                 *Is64BitCapable
+  );
+
 /**
   Provides software reset for the USB host controller.
 
-  @param  This                  This EFI_USB_HC_PROTOCOL instance.
-  @param  Attributes            A bit mask of the reset operation to perform.
+  @param  This       A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  Attributes A bit mask of the reset operation to perform.
 
   @retval EFI_SUCCESS           The reset operation succeeded.
   @retval EFI_INVALID_PARAMETER Attributes is not valid.
-  @retval EFI_UNSUPPOURTED      The type of reset specified by Attributes is
-                                not currently supported by the host controller.
-  @retval EFI_DEVICE_ERROR      Host controller isn't halted to reset.
+  @retval EFI_UNSUPPORTED       The type of reset specified by Attributes is not currently
+                                supported by the host controller hardware.
+  @retval EFI_ACCESS_DENIED     Reset operation is rejected due to the debug port being configured
+                                and active; only EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG or
+                                EFI_USB_HC_RESET_HOST_WITH_DEBUG reset Attributes can be used to
+                                perform reset operation for this host controller.
+  @retval EFI_DEVICE_ERROR      An error was encountered while attempting to
+                                retrieve the capabilities.
 
 **/
 EFI_STATUS
 EFIAPI
 OhciReset (
-  IN EFI_USB_HC_PROTOCOL  *This,
-  IN UINT16               Attributes
+  IN EFI_USB2_HC_PROTOCOL  *This,
+  IN UINT16                Attributes
   );
 
 /**
-  Retrieve the current state of the USB host controller.
+  Retrieves current state of the USB host controller.
 
-  @param  This                  This EFI_USB_HC_PROTOCOL instance.
-  @param  State                 Variable to return the current host controller
-                                state.
+  @param  This  A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  State A pointer to the EFI_USB_HC_STATE data structure that
+                indicates current state of the USB host controller.
 
-  @retval EFI_SUCCESS           Host controller state was returned in State.
+  @retval EFI_SUCCESS           The state information of the host controller was returned in State.
   @retval EFI_INVALID_PARAMETER State is NULL.
-  @retval EFI_DEVICE_ERROR      An error was encountered while attempting to
-                                retrieve the host controller's current state.
+  @retval EFI_DEVICE_ERROR      An error was encountered while attempting to retrieve the
+                                host controller's current state.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciGetState (
-  IN  EFI_USB_HC_PROTOCOL  *This,
-  OUT EFI_USB_HC_STATE     *State
+  IN  EFI_USB2_HC_PROTOCOL  *This,
+  OUT EFI_USB_HC_STATE      *State
   );
 
 /**
   Sets the USB host controller to a specific state.
 
-  @param  This                  This EFI_USB_HC_PROTOCOL instance.
-  @param  State                 The state of the host controller that will be set.
+  @param  This  A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  State Indicates the state of the host controller that will be set.
 
-  @retval EFI_SUCCESS           The USB host controller was successfully placed
-                                in the state specified by State.
-  @retval EFI_INVALID_PARAMETER State is invalid.
-  @retval EFI_DEVICE_ERROR      Failed to set the state due to device error.
+  @retval EFI_SUCCESS           The USB host controller was successfully placed in the state
+                                specified by State.
+  @retval EFI_INVALID_PARAMETER State is not valid.
+  @retval EFI_DEVICE_ERROR      Failed to set the state specified by State due to device error.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciSetState (
-  IN EFI_USB_HC_PROTOCOL  *This,
-  IN EFI_USB_HC_STATE     State
+  IN EFI_USB2_HC_PROTOCOL  *This,
+  IN EFI_USB_HC_STATE      State
   );
 
 /**
-
   Submits control transfer to a target USB device.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  DeviceAddress         Represents the address of the target device on the USB,
-                                which is assigned during USB enumeration.
-  @param  IsSlowDevice          Indicates whether the target device is slow device
-                                or full-speed device.
-  @param  MaxPaketLength        Indicates the maximum packet size that the
-                                default control transfer endpoint is capable of
-                                sending or receiving.
-  @param  Request               A pointer to the USB device request that will be sent
-                                to the USB device.
-  @param  TransferDirection     Specifies the data direction for the transfer.
-                                There are three values available, DataIn, DataOut
-                                and NoData.
-  @param  Data                  A pointer to the buffer of data that will be transmitted
-                                to USB device or received from USB device.
-  @param  DataLength            Indicates the size, in bytes, of the data buffer
-                                specified by Data.
-  @param  TimeOut               Indicates the maximum time, in microseconds,
-                                which the transfer is allowed to complete.
-  @param  TransferResult        A pointer to the detailed result information generated
-                                by this control transfer.
+  @param  This                A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  DeviceAddress       Represents the address of the target device on the USB.
+  @param  DeviceSpeed         Indicates device speed.
+  @param  MaximumPacketLength Indicates the maximum packet size that the default control transfer
+                              endpoint is capable of sending or receiving.
+  @param  Request             A pointer to the USB device request that will be sent to the USB device.
+  @param  TransferDirection   Specifies the data direction for the transfer. There are three values
+                              available, EfiUsbDataIn, EfiUsbDataOut and EfiUsbNoData.
+  @param  Data                A pointer to the buffer of data that will be transmitted to USB device or
+                              received from USB device.
+  @param  DataLength          On input, indicates the size, in bytes, of the data buffer specified by Data.
+                              On output, indicates the amount of data actually transferred.
+  @param  TimeOut             Indicates the maximum time, in milliseconds, which the transfer is
+                              allowed to complete.
+  @param  Translator          A pointer to the transaction translator data.
+  @param  TransferResult      A pointer to the detailed result information generated by this control
+                              transfer.
 
   @retval EFI_SUCCESS           The control transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The control transfer could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The control transfer could not be completed due to a lack of resources.
   @retval EFI_TIMEOUT           The control transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The control transfer failed due to host controller or device error.
-                                Caller should check TranferResult for detailed error information.
-
---*/
+                                Caller should check TransferResult for detailed error information.
 
+**/
 EFI_STATUS
 EFIAPI
 OhciControlTransfer (
-  IN     EFI_USB_HC_PROTOCOL     *This,
-  IN     UINT8                   DeviceAddress,
-  IN     BOOLEAN                 IsSlowDevice,
-  IN     UINT8                   MaxPacketLength,
-  IN     EFI_USB_DEVICE_REQUEST  *Request,
-  IN     EFI_USB_DATA_DIRECTION  TransferDirection,
-  IN OUT VOID                    *Data                 OPTIONAL,
-  IN OUT UINTN                   *DataLength           OPTIONAL,
-  IN     UINTN                   TimeOut,
-  OUT    UINT32                  *TransferResult
+  IN     EFI_USB2_HC_PROTOCOL                *This,
+  IN     UINT8                               DeviceAddress,
+  IN     UINT8                               DeviceSpeed,
+  IN     UINTN                               MaximumPacketLength,
+  IN     EFI_USB_DEVICE_REQUEST              *Request,
+  IN     EFI_USB_DATA_DIRECTION              TransferDirection,
+  IN OUT VOID                                *Data       OPTIONAL,
+  IN OUT UINTN                               *DataLength OPTIONAL,
+  IN     UINTN                               TimeOut,
+  IN     EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
+  OUT    UINT32                              *TransferResult
   );
 
 /**
-
   Submits bulk transfer to a bulk endpoint of a USB device.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  DeviceAddress         Represents the address of the target device on the USB,
-                                which is assigned during USB enumeration.
-  @param  EndPointAddress       The combination of an endpoint number and an
-                                endpoint direction of the target USB device.
-                                Each endpoint address supports data transfer in
-                                one direction except the control endpoint
-                                (whose default endpoint address is 0).
-                                It is the caller's responsibility to make sure that
-                                the EndPointAddress represents a bulk endpoint.
-  @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint
-                                is capable of sending or receiving.
-  @param  Data                  A pointer to the buffer of data that will be transmitted
-                                to USB device or received from USB device.
-  @param  DataLength            When input, indicates the size, in bytes, of the data buffer
-                                specified by Data. When output, indicates the actually
-                                transferred data size.
-  @param  DataToggle            A pointer to the data toggle value. On input, it indicates
-                                the initial data toggle value the bulk transfer should adopt;
-                                on output, it is updated to indicate the data toggle value
-                                of the subsequent bulk transfer.
-  @param  TimeOut               Indicates the maximum time, in microseconds, which the
-                                transfer is allowed to complete.
-  TransferResult                A pointer to the detailed result information of the
-                                bulk transfer.
+  @param  This                A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  DeviceAddress       Represents the address of the target device on the USB.
+  @param  EndPointAddress     The combination of an endpoint number and an endpoint direction of the
+                              target USB device.
+  @param  DeviceSpeed         Indicates device speed.
+  @param  MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of
+                              sending or receiving.
+  @param  DataBuffersNumber   Number of data buffers prepared for the transfer.
+  @param  Data                Array of pointers to the buffers of data that will be transmitted to USB
+                              device or received from USB device.
+  @param  DataLength          When input, indicates the size, in bytes, of the data buffers specified by
+                              Data. When output, indicates the actually transferred data size.
+  @param  DataToggle          A pointer to the data toggle value.
+  @param  TimeOut             Indicates the maximum time, in milliseconds, which the transfer is
+                              allowed to complete.
+  @param  Translator          A pointer to the transaction translator data.
+  @param  TransferResult      A pointer to the detailed result information of the bulk transfer.
 
   @retval EFI_SUCCESS           The bulk transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The bulk transfer could not be submitted due to lack of resource.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The bulk transfer could not be submitted due to a lack of resources.
   @retval EFI_TIMEOUT           The bulk transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The bulk transfer failed due to host controller or device error.
-                                Caller should check TranferResult for detailed error information.
+                                Caller should check TransferResult for detailed error information.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciBulkTransfer (
-  IN     EFI_USB_HC_PROTOCOL  *This,
-  IN     UINT8                DeviceAddress,
-  IN     UINT8                EndPointAddress,
-  IN     UINT8                MaxPacketLength,
-  IN OUT VOID                 *Data,
-  IN OUT UINTN                *DataLength,
-  IN OUT UINT8                *DataToggle,
-  IN     UINTN                TimeOut,
-  OUT    UINT32               *TransferResult
+  IN     EFI_USB2_HC_PROTOCOL                *This,
+  IN     UINT8                               DeviceAddress,
+  IN     UINT8                               EndPointAddress,
+  IN     UINT8                               DeviceSpeed,
+  IN     UINTN                               MaximumPacketLength,
+  IN     UINT8                               DataBuffersNumber,
+  IN OUT VOID                                *Data[EFI_USB_MAX_BULK_BUFFER_NUM],
+  IN OUT UINTN                               *DataLength,
+  IN OUT UINT8                               *DataToggle,
+  IN     UINTN                               TimeOut,
+  IN     EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
+  OUT    UINT32                              *TransferResult
   );
 
 /**
@@ -272,7 +287,7 @@ OhciBulkTransfer (
                                 the EndPointAddress represents an interrupt endpoint.
   @param  IsSlowDevice          Indicates whether the target device is slow device
                                 or full-speed device.
-  @param  MaxPacketLength       Indicates the maximum packet size the target endpoint
+  @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint
                                 is capable of sending or receiving.
   @param  IsNewTransfer         If TRUE, an asynchronous interrupt pipe is built between
                                 the host and the target interrupt endpoint.
@@ -309,14 +324,13 @@ OhciBulkTransfer (
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 
 **/
-
 EFI_STATUS
 OhciInterruptTransfer (
   IN     USB_OHCI_HC_DEV                  *Ohc,
   IN     UINT8                            DeviceAddress,
   IN     UINT8                            EndPointAddress,
   IN     BOOLEAN                          IsSlowDevice,
-  IN     UINT8                            MaxPacketLength,
+  IN     UINT8                            MaximumPacketLength,
   IN     BOOLEAN                          IsNewTransfer,
   IN OUT UINT8                            *DataToggle        OPTIONAL,
   IN     UINTN                            PollingInterval    OPTIONAL,
@@ -330,45 +344,30 @@ OhciInterruptTransfer (
   );
 
 /**
-
   Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device.
+  Translator parameter doesn't exist in UEFI2.0 spec, but it will be updated in the following specification version.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  DeviceAddress         Represents the address of the target device on the USB,
-                                which is assigned during USB enumeration.
-  @param  EndPointAddress       The combination of an endpoint number and an endpoint
-                                direction of the target USB device. Each endpoint address
-                                supports data transfer in one direction except the
-                                control endpoint (whose default endpoint address is 0).
-                                It is the caller's responsibility to make sure that
-                                the EndPointAddress represents an interrupt endpoint.
-  @param  IsSlowDevice          Indicates whether the target device is slow device
-                                or full-speed device.
-  @param  MaxiumPacketLength    Indicates the maximum packet size the target endpoint
-                                is capable of sending or receiving.
-  @param  IsNewTransfer         If TRUE, an asynchronous interrupt pipe is built between
-                                the host and the target interrupt endpoint.
-                                If FALSE, the specified asynchronous interrupt pipe
-                                is canceled.
-  @param  DataToggle            A pointer to the data toggle value.  On input, it is valid
-                                when IsNewTransfer is TRUE, and it indicates the initial
-                                data toggle value the asynchronous interrupt transfer
-                                should adopt.
-                                On output, it is valid when IsNewTransfer is FALSE,
-                                and it is updated to indicate the data toggle value of
-                                the subsequent asynchronous interrupt transfer.
-  @param  PollingInterval       Indicates the interval, in milliseconds, that the
-                                asynchronous interrupt transfer is polled.
-                                This parameter is required when IsNewTransfer is TRUE.
-  @param  DataLength            Indicates the length of data to be received at the
-                                rate specified by PollingInterval from the target
-                                asynchronous interrupt endpoint.  This parameter
-                                is only required when IsNewTransfer is TRUE.
-  @param  CallBackFunction      The Callback function.This function is called at the
-                                rate specified by PollingInterval.This parameter is
-                                only required when IsNewTransfer is TRUE.
-  @param  Context               The context that is passed to the CallBackFunction.
-                                This is an optional parameter and may be NULL.
+  @param  This                A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  DeviceAddress       Represents the address of the target device on the USB.
+  @param  EndPointAddress     The combination of an endpoint number and an endpoint direction of the
+                              target USB device.
+  @param  DeviceSpeed         Indicates device speed.
+  @param  MaximumPacketLength Indicates the maximum packet size the target endpoint is capable of
+                              sending or receiving.
+  @param  IsNewTransfer       If TRUE, an asynchronous interrupt pipe is built between the host and the
+                              target interrupt endpoint. If FALSE, the specified asynchronous interrupt
+                              pipe is canceled. If TRUE, and an interrupt transfer exists for the target
+                              end point, then EFI_INVALID_PARAMETER is returned.
+  @param  DataToggle          A pointer to the data toggle value.
+  @param  PollingInterval     Indicates the interval, in milliseconds, that the asynchronous interrupt
+                              transfer is polled.
+  @param  DataLength          Indicates the length of data to be received at the rate specified by
+                              PollingInterval from the target asynchronous interrupt endpoint.
+  @param  Translator          A pointr to the transaction translator data.
+  @param  CallBackFunction    The Callback function. This function is called at the rate specified by
+                              PollingInterval.
+  @param  Context             The context that is passed to the CallBackFunction. This is an
+                              optional parameter and may be NULL.
 
   @retval EFI_SUCCESS           The asynchronous interrupt transfer request has been successfully
                                 submitted or canceled.
@@ -376,228 +375,276 @@ OhciInterruptTransfer (
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciAsyncInterruptTransfer (
-  IN     EFI_USB_HC_PROTOCOL              *This,
-  IN     UINT8                            DeviceAddress,
-  IN     UINT8                            EndPointAddress,
-  IN     BOOLEAN                          IsSlowDevice,
-  IN     UINT8                            MaxPacketLength,
-  IN     BOOLEAN                          IsNewTransfer,
-  IN OUT UINT8                            *DataToggle        OPTIONAL,
-  IN     UINTN                            PollingInterval    OPTIONAL,
-  IN     UINTN                            DataLength         OPTIONAL,
-  IN     EFI_ASYNC_USB_TRANSFER_CALLBACK  CallBackFunction   OPTIONAL,
-  IN     VOID                             *Context           OPTIONAL
+  IN     EFI_USB2_HC_PROTOCOL                *This,
+  IN     UINT8                               DeviceAddress,
+  IN     UINT8                               EndPointAddress,
+  IN     UINT8                               DeviceSpeed,
+  IN     UINTN                               MaxiumPacketLength,
+  IN     BOOLEAN                             IsNewTransfer,
+  IN OUT UINT8                               *DataToggle,
+  IN     UINTN                               PollingInterval  OPTIONAL,
+  IN     UINTN                               DataLength       OPTIONAL,
+  IN     EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator      OPTIONAL,
+  IN     EFI_ASYNC_USB_TRANSFER_CALLBACK     CallBackFunction OPTIONAL,
+  IN     VOID                                *Context         OPTIONAL
   );
 
 /**
+  Submits synchronous interrupt transfer to an interrupt endpoint of a USB device.
+  Translator parameter doesn't exist in UEFI2.0 spec, but it will be updated in the following specification version.
 
-  Submits synchronous interrupt transfer to an interrupt endpoint
-  of a USB device.
+  @param  This                  A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  DeviceAddress         Represents the address of the target device on the USB.
+  @param  EndPointAddress       The combination of an endpoint number and an endpoint direction of the
+                                target USB device.
+  @param  DeviceSpeed           Indicates device speed.
+  @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint is capable of
+                                sending or receiving.
+  @param  Data                  A pointer to the buffer of data that will be transmitted to USB device or
+                                received from USB device.
+  @param  DataLength            On input, the size, in bytes, of the data buffer specified by Data. On
+                                output, the number of bytes transferred.
+  @param  DataToggle            A pointer to the data toggle value.
+  @param  TimeOut               Indicates the maximum time, in milliseconds, which the transfer is
+                                allowed to complete.
+  @param  Translator            A pointr to the transaction translator data.
+  @param  TransferResult        A pointer to the detailed result information from the synchronous
+                                interrupt transfer.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  DeviceAddress         Represents the address of the target device on the USB,
-                                which is assigned during USB enumeration.
-  @param  EndPointAddress       The combination of an endpoint number and an endpoint
-                                direction of the target USB device. Each endpoint
-                                address supports data transfer in one direction
-                                except the control endpoint (whose default
-                                endpoint address is 0). It is the caller's responsibility
-                                to make sure that the EndPointAddress represents
-                                an interrupt endpoint.
-  @param  IsSlowDevice          Indicates whether the target device is slow device
-                                or full-speed device.
-  @param  MaxPacketLength       Indicates the maximum packet size the target endpoint
-                                is capable of sending or receiving.
-  @param  Data                  A pointer to the buffer of data that will be transmitted
-                                to USB device or received from USB device.
-  @param  DataLength            On input, the size, in bytes, of the data buffer specified
-                                by Data. On output, the number of bytes transferred.
-  @param  DataToggle            A pointer to the data toggle value. On input, it indicates
-                                the initial data toggle value the synchronous interrupt
-                                transfer should adopt;
-                                on output, it is updated to indicate the data toggle value
-                                of the subsequent synchronous interrupt transfer.
-  @param  TimeOut               Indicates the maximum time, in microseconds, which the
-                                transfer is allowed to complete.
-  @param  TransferResult        A pointer to the detailed result information from
-                                the synchronous interrupt transfer.
-
-  @retval EFI_UNSUPPORTED       This interface not available.
-  @retval EFI_INVALID_PARAMETER Parameters not follow spec
+  @retval EFI_SUCCESS           The synchronous interrupt transfer was completed successfully.
+  @retval EFI_INVALID_PARAMETER Some parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The synchronous interrupt transfer could not be submitted due to a lack of resources.
+  @retval EFI_TIMEOUT           The synchronous interrupt transfer failed due to timeout.
+  @retval EFI_DEVICE_ERROR      The synchronous interrupt transfer failed due to host controller or device error.
+                                Caller should check TransferResult for detailed error information.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciSyncInterruptTransfer (
-  IN     EFI_USB_HC_PROTOCOL  *This,
-  IN     UINT8                DeviceAddress,
-  IN     UINT8                EndPointAddress,
-  IN     BOOLEAN              IsSlowDevice,
-  IN     UINT8                MaxPacketLength,
-  IN OUT VOID                 *Data,
-  IN OUT UINTN                *DataLength,
-  IN OUT UINT8                *DataToggle,
-  IN     UINTN                TimeOut,
-  OUT    UINT32               *TransferResult
+  IN     EFI_USB2_HC_PROTOCOL                *This,
+  IN     UINT8                               DeviceAddress,
+  IN     UINT8                               EndPointAddress,
+  IN     UINT8                               DeviceSpeed,
+  IN     UINTN                               MaximumPacketLength,
+  IN OUT VOID                                *Data,
+  IN OUT UINTN                               *DataLength,
+  IN OUT UINT8                               *DataToggle,
+  IN     UINTN                               TimeOut,
+  IN     EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
+  OUT    UINT32                              *TransferResult
   );
 
 /**
+  Submits isochronous transfer to an isochronous endpoint of a USB device.
 
-  Submits isochronous transfer to a target USB device.
+  This function is used to submit isochronous transfer to a target endpoint of a USB device.
+  The target endpoint is specified by DeviceAddressand EndpointAddress. Isochronous transfers are
+  used when working with isochronous date. It provides periodic, continuous communication between
+  the host and a device. Isochronous transfers can beused only by full-speed, high-speed, and
+  super-speed devices.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  DeviceAddress         Represents the address of the target device on the USB,
-                                which is assigned during USB enumeration.
-  @param  EndPointAddress       End point address
-  @param  MaximumPacketLength   Indicates the maximum packet size that the
-                                default control transfer endpoint is capable of
+  High-speed isochronous transfers can be performed using multiple data buffers. The number of
+  buffers that are actually prepared for the transfer is specified by DataBuffersNumber. For
+  full-speed isochronous transfers this value is ignored.
+
+  Data represents a list of pointers to the data buffers. For full-speed isochronous transfers
+  only the data pointed by Data[0]shall be used. For high-speed isochronous transfers and for
+  the split transactions depending on DataLengththere several data buffers canbe used. For the
+  high-speed isochronous transfers the total number of buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM.
+
+  For split transactions performed on full-speed device by high-speed host controller the total
+  number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1.
+  If the isochronous transfer is successful, then EFI_SUCCESSis returned. The isochronous transfer
+  is designed to be completed within one USB frame time, if it cannot be completed, EFI_TIMEOUT
+  is returned. If an error other than timeout occurs during the USB transfer, then EFI_DEVICE_ERROR
+  is returned and the detailed status code will be returned in TransferResult.
+
+  EFI_INVALID_PARAMETERis returned if one of the following conditionsis satisfied:
+    - Data is NULL.
+    - DataLength is 0.
+    - DeviceSpeed is not one of the supported values listed above.
+    - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed devices,
+      and 1024 or less for high-speed and super-speed devices.
+    - TransferResult is NULL.
+
+  @param  This                  A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  DeviceAddress         Represents the address of the target device on the USB.
+  @param  EndPointAddress       The combination of an endpoint number and an endpoint direction of the
+                                target USB device.
+  @param  DeviceSpeed           Indicates device speed. The supported values are EFI_USB_SPEED_FULL,
+                                EFI_USB_SPEED_HIGH, or EFI_USB_SPEED_SUPER.
+  @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint is capable of
                                 sending or receiving.
-  @param  Data                  A pointer to the buffer of data that will be transmitted
-                                to USB device or received from USB device.
-  @param  DataLength            Indicates the size, in bytes, of the data buffer
-                                specified by Data.
-  @param  TransferResult        A pointer to the detailed result information generated
-                                by this control transfer.
+  @param  DataBuffersNumber     Number of data buffers prepared for the transfer.
+  @param  Data                  Array of pointers to the buffers of data that will be transmitted to USB
+                                device or received from USB device.
+  @param  DataLength            Specifies the length, in bytes, of the data to be sent to or received from
+                                the USB device.
+  @param  Translator            A pointer to the transaction translator data.
+  @param  TransferResult        A pointer to the detailed result information of the isochronous transfer.
 
-  @retval EFI_UNSUPPORTED       This interface not available
-  @retval EFI_INVALID_PARAMETER Data is NULL or DataLength is 0 or TransferResult is NULL
+  @retval EFI_SUCCESS           The isochronous transfer was completed successfully.
+  @retval EFI_INVALID_PARAMETER Some parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The isochronous transfer could not be submitted due to a lack of resources.
+  @retval EFI_TIMEOUT           The isochronous transfer cannot be completed within the one USB frame time.
+  @retval EFI_DEVICE_ERROR      The isochronous transfer failed due to host controller or device error.
+                                Caller should check TransferResult for detailed error information.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciIsochronousTransfer (
-  IN     EFI_USB_HC_PROTOCOL  *This,
-  IN     UINT8                DeviceAddress,
-  IN     UINT8                EndPointAddress,
-  IN     UINT8                MaximumPacketLength,
-  IN OUT VOID                 *Data,
-  IN OUT UINTN                DataLength,
-  OUT    UINT32               *TransferResult
+  IN     EFI_USB2_HC_PROTOCOL                *This,
+  IN     UINT8                               DeviceAddress,
+  IN     UINT8                               EndPointAddress,
+  IN     UINT8                               DeviceSpeed,
+  IN     UINTN                               MaximumPacketLength,
+  IN     UINT8                               DataBuffersNumber,
+  IN OUT VOID                                *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
+  IN     UINTN                               DataLength,
+  IN     EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
+  OUT    UINT32                              *TransferResult
   );
 
 /**
+  Submits nonblocking isochronous transfer to an isochronous endpoint of a USB device.
 
-  Submits Async isochronous transfer to a target USB device.
+  This is an asynchronous type of USB isochronous transfer. If the caller submits a USB
+  isochronous transfer request through this function, this function will return immediately.
 
-  @param  his                   A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  DeviceAddress         Represents the address of the target device on the USB,
-                                which is assigned during USB enumeration.
-  @param  EndPointAddress       End point address
-  @param  MaximumPacketLength   Indicates the maximum packet size that the
-                                default control transfer endpoint is capable of
+  When the isochronous transfer completes, the IsochronousCallbackfunction will be triggered,
+  the caller can know the transfer results. If the transfer is successful, the caller can get
+  the data received or sent in this callback function.
+
+  The target endpoint is specified by DeviceAddressand EndpointAddress. Isochronous transfers
+  are used when working with isochronous date. It provides periodic, continuous communication
+  between the host and a device. Isochronous transfers can be used only by full-speed, high-speed,
+  and super-speed devices.
+
+  High-speed isochronous transfers can be performed using multiple data buffers. The number of
+  buffers that are actually prepared for the transfer is specified by DataBuffersNumber. For
+  full-speed isochronous transfers this value is ignored.
+
+  Data represents a list of pointers to the data buffers. For full-speed isochronous transfers
+  only the data pointed by Data[0] shall be used. For high-speed isochronous transfers and for
+  the split transactions depending on DataLength there several data buffers can be used. For
+  the high-speed isochronous transfers the total number of buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM.
+
+  For split transactions performed on full-speed device by high-speed host controller the total
+  number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1.
+
+  EFI_INVALID_PARAMETER is returned if one of the following conditionsis satisfied:
+    - Data is NULL.
+    - DataLength is 0.
+    - DeviceSpeed is not one of the supported values listed above.
+    - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed
+      devices and 1024 or less for high-speed and super-speed devices.
+
+  @param  This                  A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  DeviceAddress         Represents the address of the target device on the USB.
+  @param  EndPointAddress       The combination of an endpoint number and an endpoint direction of the
+                                target USB device.
+  @param  DeviceSpeed           Indicates device speed. The supported values are EFI_USB_SPEED_FULL,
+                                EFI_USB_SPEED_HIGH, or EFI_USB_SPEED_SUPER.
+  @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint is capable of
                                 sending or receiving.
-  @param  Data                  A pointer to the buffer of data that will be transmitted
-                                to USB device or received from USB device.
-  @param  IsochronousCallBack   When the transfer complete, the call back function will be called
-  @param  Context               Pass to the call back function as parameter
+  @param  DataBuffersNumber     Number of data buffers prepared for the transfer.
+  @param  Data                  Array of pointers to the buffers of data that will be transmitted to USB
+                                device or received from USB device.
+  @param  DataLength            Specifies the length, in bytes, of the data to be sent to or received from
+                                the USB device.
+  @param  Translator            A pointer to the transaction translator data.
+  @param  IsochronousCallback   The Callback function. This function is called if the requested
+                                isochronous transfer is completed.
+  @param  Context               Data passed to the IsochronousCallback function. This is an
+                                optional parameter and may be NULL.
 
-  @retval EFI_UNSUPPORTED       This interface not available
-  @retval EFI_INVALID_PARAMETER Data is NULL or Datalength is 0
+  @retval EFI_SUCCESS           The asynchronous isochronous transfer request has been successfully
+                                submitted or canceled.
+  @retval EFI_INVALID_PARAMETER Some parameters are invalid.
+  @retval EFI_OUT_OF_RESOURCES  The asynchronous isochronous transfer could not be submitted due to
+                                a lack of resources.
 
 **/
-
 EFI_STATUS
 EFIAPI
 OhciAsyncIsochronousTransfer (
-  IN     EFI_USB_HC_PROTOCOL              *This,
-  IN     UINT8                            DeviceAddress,
-  IN     UINT8                            EndPointAddress,
-  IN     UINT8                            MaximumPacketLength,
-  IN OUT VOID                             *Data,
-  IN OUT UINTN                            DataLength,
-  IN     EFI_ASYNC_USB_TRANSFER_CALLBACK  IsochronousCallBack,
-  IN     VOID                             *Context OPTIONAL
+  IN     EFI_USB2_HC_PROTOCOL                *This,
+  IN     UINT8                               DeviceAddress,
+  IN     UINT8                               EndPointAddress,
+  IN     UINT8                               DeviceSpeed,
+  IN     UINTN                               MaximumPacketLength,
+  IN     UINT8                               DataBuffersNumber,
+  IN OUT VOID                                *Data[EFI_USB_MAX_ISO_BUFFER_NUM],
+  IN     UINTN                               DataLength,
+  IN     EFI_USB2_HC_TRANSACTION_TRANSLATOR  *Translator,
+  IN     EFI_ASYNC_USB_TRANSFER_CALLBACK     IsochronousCallBack,
+  IN     VOID                                *Context OPTIONAL
   );
 
 /**
-
-  Retrieves the number of root hub ports.
-
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  NumOfPorts            A pointer to the number of the root hub ports.
-
-  @retval EFI_SUCCESS           The port number was retrieved successfully.
-**/
-EFI_STATUS
-EFIAPI
-OhciGetRootHubNumOfPorts (
-  IN  EFI_USB_HC_PROTOCOL  *This,
-  OUT UINT8                *NumOfPorts
-  );
-
-/**
-
   Retrieves the current status of a USB root hub port.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL.
-  @param  PortNumber            Specifies the root hub port from which the status
-                                is to be retrieved.  This value is zero-based. For example,
-                                if a root hub has two ports, then the first port is numbered 0,
-                                and the second port is numbered 1.
-  @param  PortStatus            A pointer to the current port status bits and
-                                port status change bits.
+  @param  This       A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  PortNumber Specifies the root hub port from which the status is to be retrieved.
+                     This value is zero based.
+  @param  PortStatus A pointer to the current port status bits and port status change bits.
 
   @retval EFI_SUCCESS           The status of the USB root hub port specified by PortNumber
                                 was returned in PortStatus.
-  @retval EFI_INVALID_PARAMETER Port number not valid
-**/
+  @retval EFI_INVALID_PARAMETER PortNumber is invalid.
 
+**/
 EFI_STATUS
 EFIAPI
 OhciGetRootHubPortStatus (
-  IN  EFI_USB_HC_PROTOCOL  *This,
-  IN  UINT8                PortNumber,
-  OUT EFI_USB_PORT_STATUS  *PortStatus
+  IN        EFI_USB2_HC_PROTOCOL  *This,
+  IN        UINT8                 PortNumber,
+  OUT       EFI_USB_PORT_STATUS   *PortStatus
   );
 
 /**
-
   Sets a feature for the specified root hub port.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL.
-  @param  PortNumber            Specifies the root hub port whose feature
-                                is requested to be set.
-  @param  PortFeature           Indicates the feature selector associated
-                                with the feature set request.
+  @param  This        A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  PortNumber  Specifies the root hub port whose feature is requested to be set. This
+                      value is zero based.
+  @param  PortFeature Indicates the feature selector associated with the feature set request.
+
+  @retval EFI_SUCCESS           The feature specified by PortFeature was set for the USB
+                                root hub port specified by PortNumber.
+  @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function.
 
-  @retval EFI_SUCCESS           The feature specified by PortFeature was set for the
-                                USB root hub port specified by PortNumber.
-  @retval EFI_DEVICE_ERROR      Set feature failed because of hardware issue
-  @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
 **/
 EFI_STATUS
 EFIAPI
 OhciSetRootHubPortFeature (
-  IN EFI_USB_HC_PROTOCOL   *This,
+  IN EFI_USB2_HC_PROTOCOL  *This,
   IN UINT8                 PortNumber,
   IN EFI_USB_PORT_FEATURE  PortFeature
   );
 
 /**
-
   Clears a feature for the specified root hub port.
 
-  @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  PortNumber            Specifies the root hub port whose feature
-                                is requested to be cleared.
-  @param  PortFeature           Indicates the feature selector associated with the
-                                feature clear request.
+  @param  This        A pointer to the EFI_USB2_HC_PROTOCOL instance.
+  @param  PortNumber  Specifies the root hub port whose feature is requested to be cleared. This
+                      value is zero based.
+  @param  PortFeature Indicates the feature selector associated with the feature clear request.
+
+  @retval EFI_SUCCESS           The feature specified by PortFeature was cleared for the USB
+                                root hub port specified by PortNumber.
+  @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function.
 
-  @retval EFI_SUCCESS           The feature specified by PortFeature was cleared for the
-                                USB root hub port specified by PortNumber.
-  @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
-  @retval EFI_DEVICE_ERROR      Some error happened when clearing feature
 **/
 EFI_STATUS
 EFIAPI
 OhciClearRootHubPortFeature (
-  IN EFI_USB_HC_PROTOCOL   *This,
+  IN EFI_USB2_HC_PROTOCOL  *This,
   IN UINT8                 PortNumber,
   IN EFI_USB_PORT_FEATURE  PortFeature
   );
@@ -616,7 +663,6 @@ OhciClearRootHubPortFeature (
 **/
 EFI_STATUS
 EFIAPI
-
 OHCIDriverBindingSupported (
   IN EFI_DRIVER_BINDING_PROTOCOL  *This,
   IN EFI_HANDLE                   Controller,

edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf

@@ -1,6 +1,7 @@
 ## @file
 # OHCI USB Host Controller UEFI Driver
 #
+# Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
 # Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -62,8 +63,8 @@
   gEfiEndOfDxeEventGroupGuid
 
 [Protocols]
-  gOhciDeviceProtocolGuid                           ## TO_START
-  gEfiUsbHcProtocolGuid                         ## BY_START
+  gOhciDeviceProtocolGuid                       ## TO_START
+  gEfiUsb2HcProtocolGuid                        ## BY_START
 
 [Depex]
   TRUE

edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.h

@@ -24,7 +24,7 @@ struct _INTERRUPT_CONTEXT_ENTRY {
   ED_DESCRIPTOR                      *Ed;
   TD_DESCRIPTOR                      *DataTd;
   BOOLEAN                            IsSlowDevice;
-  UINT8                              MaxPacketLength;
+  UINT8                              MaximumPacketLength;
   UINTN                              PollingInterval;
   EFI_ASYNC_USB_TRANSFER_CALLBACK    CallBackFunction;
   VOID                               *Context;

edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c

@@ -272,14 +272,13 @@ CHAR8               *mEnclosureInfoType3Strings[] = {
         SMBIOS data definition  TYPE4  Processor Information
 ************************************************************************/
 SMBIOS_TABLE_TYPE4  mProcessorInfoType4 = {
-  { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0    },
+  { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0 },
   1,                               // Socket String
   CentralProcessor,                // ProcessorType;          ///< The enumeration value from PROCESSOR_TYPE_DATA.
   ProcessorFamilyIndicatorFamily2, // ProcessorFamily;        ///< The enumeration value from PROCESSOR_FAMILY2_DATA.
   2,                               // ProcessorManufacture String;
   {                                // ProcessorId;
-    { 0x00,                                  0x00,                        0x00, 0x00},
-    { 0x00,                                  0x00,                        0x00, 0x00}
+    0x00, 0x00, 0x00, 0x00
   },
   3,                    // ProcessorVersion String;
   {     // Voltage;
@@ -344,8 +343,8 @@ SMBIOS_TABLE_TYPE7  mCacheInfoType7_L1I = {
   // Enabled/Disabled   :1  (Enabled)
   // Operational Mode   :2  (Unknown)
   // Reserved           :6
-  0x0020,                   // Maximum Size (32KB)
-  0x0020,                   // Install Size (32KB)
+  { 0x0020,                            0 },   // Maximum Size (32KB)
+  { 0x0020,                            0 },   // Install Size (32KB)
   {     // Supported SRAM Type
     0,  // Other             :1
     0,  // Unknown           :1
@@ -387,8 +386,8 @@ SMBIOS_TABLE_TYPE7  mCacheInfoType7_L1D = {
   // Enabled/Disabled   :1  (Enabled)
   // Operational Mode   :2  (WB)
   // Reserved           :6
-  0x0020,                   // Maximum Size (32KB)
-  0x0020,                   // Install Size (32KB)
+  { 0x0020,                            0 },   // Maximum Size (32KB)
+  { 0x0020,                            0 },   // Install Size (32KB)
   {     // Supported SRAM Type
     0,  // Other             :1
     0,  // Unknown           :1
@@ -430,8 +429,8 @@ SMBIOS_TABLE_TYPE7  mCacheInfoType7_L2 = {
   // Enabled/Disabled   :1  (Enabled)
   // Operational Mode   :2  (WB)
   // Reserved           :6
-  0x0200,                   // Maximum Size (512KB)
-  0x0200,                   // Install Size (512KB)
+  { 0x0200,                            0 },   // Maximum Size (512KB)
+  { 0x0200,                            0 },   // Install Size (512KB)
   {     // Supported SRAM Type
     0,  // Other             :1
     0,  // Unknown           :1

edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c

@@ -17,15 +17,16 @@
 #include <Library/BaseLib.h>
 #include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
 #include <Library/DxeServicesTableLib.h>
+#include <Library/FdtLib.h>
 #include <Library/HobLib.h>
 #include <Library/MemoryAllocationLib.h>
 #include <Library/PcdLib.h>
+#include <Library/RkAtagsLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/UefiLib.h>
 #include <Library/UefiRuntimeLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/RkAtagsLib.h>
 #include <Protocol/DiskIo.h>
 #include <Protocol/LoadedImage.h>
 #include <Protocol/NonDiscoverableDevice.h>
@@ -34,7 +35,6 @@
 #include <Guid/SystemNvDataGuid.h>
 #include <Guid/VariableFormat.h>
 #include <Guid/EventGroup.h>
-#include <libfdt.h>
 
 #include "RkFvbDxe.h"
 
@@ -1349,7 +1349,7 @@ FvbCheckBootDiskDeviceHasFirmware (
   EFI_DISK_IO_PROTOCOL  *DiskIo;
   UINT64                Offset;
   UINTN                 Size;
-  struct fdt_header     FdtHeader;
+  FDT_HEADER            FdtHeader;
   VOID                  *Fdt = NULL;
   INT32                 Ret;
   INT32                 Node;
@@ -1378,19 +1378,19 @@ FvbCheckBootDiskDeviceHasFirmware (
     goto Exit;
   }
 
-  Ret = fdt_check_header (&FdtHeader);
+  Ret = FdtCheckHeader (&FdtHeader);
   if (Ret) {
     DEBUG ((
       DEBUG_ERROR,
       "%a: [%s] FIT has an invalid header! Ret=%a\n",
       __FUNCTION__,
       DevicePathText,
-      fdt_strerror (Ret)
+      FdtStrerror (Ret)
       ));
     goto Exit;
   }
 
-  Size = fdt_totalsize (&FdtHeader);
+  Size = FdtTotalSize (&FdtHeader);
   Fdt  = AllocatePool (Size);
 
   Status = DiskIo->ReadDisk (DiskIo, MediaId, Offset, Size, Fdt);
@@ -1407,14 +1407,14 @@ FvbCheckBootDiskDeviceHasFirmware (
     goto Exit;
   }
 
-  Node = fdt_path_offset (Fdt, "/images/edk2");
+  Node = FdtPathOffset (Fdt, "/images/edk2");
   if (Node < 0) {
     DEBUG ((
       DEBUG_ERROR,
       "%a: [%s] FIT: Couldn't locate '/images/edk2' node! Ret=%a\n",
       __FUNCTION__,
       DevicePathText,
-      fdt_strerror (Node)
+      FdtStrerror (Node)
       ));
     goto Exit;
   }

edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf

@@ -31,21 +31,20 @@
   Silicon/Rockchip/RockchipPkg.dec
 
 [LibraryClasses]
-  IoLib
   BaseLib
-  DebugLib
-  HobLib
-  UefiLib
-  UefiDriverEntryPoint
-  UefiBootServicesTableLib
-  UefiRuntimeLib
   BaseMemoryLib
+  DebugLib
   DevicePathLib
   DxeServicesTableLib
-  MemoryAllocationLib
-  UefiRuntimeServicesTableLib
-  RkAtagsLib
   FdtLib
+  HobLib
+  MemoryAllocationLib
+  PcdLib
+  RkAtagsLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+  UefiRuntimeLib
 
 [Guids]
   gEdkiiNvVarStoreFormattedGuid

edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc

@@ -127,6 +127,12 @@
   INF Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf
   INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
 
+!if $(RK_AMD_GOP_ENABLE) == TRUE
+  INF Drivers/AMD/Gop/AmdGopOpRomOverrideDxe.inf
+  INF Drivers/AMD/Gop/AmdGopPreSoc15Dxe.inf
+  INF Drivers/AMD/Gop/AmdGopPostSoc15Dxe.inf
+!endif
+
   #
   # USB Support
   #
@@ -187,6 +193,7 @@
   INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
   INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   INF FatPkg/EnhancedFatDxe/Fat.inf
+!include Features/Ext4Pkg/Ext4.fdf.inc
   INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
   #
@@ -221,6 +228,13 @@
   #
   INF EmbeddedPkg/Drivers/MemoryAttributeManagerDxe/MemoryAttributeManagerDxe.inf
 
+  #
+  # x64 Binary Compatibility Support
+  #
+!if $(RK_X86_EMULATOR_ENABLE) == TRUE
+  INF Emulator/X86EmulatorDxe/X86EmulatorDxe.inf
+!endif
+
   #
   # Bds
   #

edk2-rockchip/Silicon/Rockchip/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf

@@ -20,6 +20,7 @@
 
 [Packages]
   EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Rockchip/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec
 

edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf

@@ -53,9 +53,6 @@
   UefiLib
   UefiRuntimeServicesTableLib
 
-[FeaturePcd]
-  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
-
 [FixedPcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString

edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc

@@ -23,80 +23,6 @@ RK3588_MCFG_TABLE  Mcfg = {
       EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
       ),
   },
-  { // Main config space
-    {
-      PCIE_CFG_BASE (0),
-      0,  // PciSegmentNumber
-      1,  // PciBusMin
-      1,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_CFG_BASE (1),
-      1,  // PciSegmentNumber
-      1,  // PciBusMin
-      1,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_CFG_BASE (2),
-      2,  // PciSegmentNumber
-      1,  // PciBusMin
-      1,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_CFG_BASE (3),
-      3,  // PciSegmentNumber
-      1,  // PciBusMin
-      1,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_CFG_BASE (4),
-      4,  // PciSegmentNumber
-      1,  // PciBusMin
-      1,  // PciBusMax
-      0   // Reserved
-    }
-  },
-  { // Root Port DBI config space (for Windows)
-    {
-      PCIE_DBI_BASE (0),
-      0,  // PciSegmentNumber
-      0,  // PciBusMin
-      0,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_DBI_BASE (1),
-      1,  // PciSegmentNumber
-      0,  // PciBusMin
-      0,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_DBI_BASE (2),
-      2,  // PciSegmentNumber
-      0,  // PciBusMin
-      0,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_DBI_BASE (3),
-      3,  // PciSegmentNumber
-      0,  // PciBusMin
-      0,  // PciBusMax
-      0   // Reserved
-    },
-    {
-      PCIE_DBI_BASE (4),
-      4,  // PciSegmentNumber
-      0,  // PciBusMin
-      0,  // PciBusMax
-      0   // Reserved
-    }
-  }
 };
 
 VOID *CONST  ReferenceAcpiTable = &Mcfg;

edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl

@@ -16,7 +16,11 @@
     Name (_UID, Segment)                                                       \
     Name (_SEG, Segment)                                                       \
     Method (_BBN) {                                                            \
-      Return (PBMI)                                                            \
+      If (PBOF) {                                                              \
+        Return (PCIE_BUS_BASE (Segment) + PBMI)                                \
+      } Else {                                                                 \
+        Return (PBMI)                                                          \
+      }                                                                        \
     }                                                                          \
     Name (_STA, 0xF)                                                           \
                                                                                \
@@ -30,14 +34,34 @@
     Method (_CRS, 0, Serialized) {                                             \
       Name (RBUF, ResourceTemplate () {                                        \
         WORDBUSNUMBER_BUF (00, ResourceProducer)                               \
-        DWORDMEMORY_BUF (01, ResourceProducer)                                 \
+        QWORDMEMORY_BUF (01, ResourceProducer)                                 \
         QWORDMEMORY_BUF (02, ResourceProducer)                                 \
         QWORDIO_BUF (03, ResourceProducer)                                     \
       })                                                                       \
-      WORD_SET (00, PBMI, PBMA - PBMI + 1, 0)                                  \
-      DWORD_SET (01, PCIE_MEM_BASE (Segment), PCIE_MEM_SIZE, 0)                \
-      QWORD_SET (02, PCIE_MEM64_BASE (Segment), PCIE_MEM64_SIZE, 0)            \
-      QWORD_SET (03, PCIE_IO_BASE, PCIE_IO_SIZE, PCIE_IO_XLATE (Segment))      \
+      WORD_SET (                                                               \
+        00,                                                                    \
+        _BBN,                                                                  \
+        PBMA - PBMI + 1,                                                       \
+        0                                                                      \
+      )                                                                        \
+      QWORD_SET (                                                              \
+        01,                                                                    \
+        PCIE_MEM32_BUS_BASE,                                                   \
+        PCIE_MEM32_SIZE,                                                       \
+        PCIE_MEM32_TRANSLATION (Segment)                                       \
+      )                                                                        \
+      QWORD_SET (                                                              \
+        02,                                                                    \
+        PCIE_MEM64_BASE (Segment),                                             \
+        PCIE_MEM64_SIZE,                                                       \
+        0                                                                      \
+      )                                                                        \
+      QWORD_SET (                                                              \
+        03,                                                                    \
+        PCIE_IO_BUS_BASE,                                                      \
+        PCIE_IO_SIZE,                                                          \
+        PCIE_IO_TRANSLATION (Segment)                                          \
+      )                                                                        \
       Return (RBUF)                                                            \
     }                                                                          \
                                                                                \
@@ -61,7 +85,7 @@
         Name (RBUF, ResourceTemplate () {                                      \
           QWORDMEMORY_BUF (00, ResourceProducer)                               \
         })                                                                     \
-        QWORD_SET (00, PCIE_CFG_BASE (Segment), SIZE_256MB, 0)                 \
+        QWORD_SET (00, PCIE_CFG_BASE (Segment), PCIE_CFG_SIZE , 0)             \
         Return (RBUF)                                                          \
       }                                                                        \
     }                                                                          \
@@ -111,6 +135,7 @@
 Scope (\_SB_) {
   Name (PBMI, 0xABCD)   // PCI Bus Minimum
   Name (PBMA, 0xABCD)   // PCI Bus Maximum
+  Name (PBOF, 1)        // PCI Bus Offset
 
   PCIE_ROOT_COMPLEX (0, 292)
   PCIE_ROOT_COMPLEX (1, 287)

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c

@@ -218,9 +218,9 @@ AcpiFixupPcieEcam (
   UINT32                       PcieEcamMode;
   UINT8                        PcieBusMin;
   UINT8                        PcieBusMax;
-  UINT8                        McfgMainBusMin;
-  BOOLEAN                      McfgSplitRootPort;
-  BOOLEAN                      McfgSingleDevQuirk;
+  BOOLEAN                      PcieBusOffset;
+  BOOLEAN                      McfgDeviceFiltering;
+  BOOLEAN                      McfgSplitConfigSpaces;
 
   Index  = 0;
   Status = AcpiLocateTableBySignature (
@@ -241,23 +241,37 @@ AcpiFixupPcieEcam (
 
   PcieEcamMode = PcdGet32 (PcdAcpiPcieEcamCompatMode);
 
-  if ((PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV) ||
-      (PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON))
-  {
-    if (OsType == ExitBootServicesOsWindows) {
-      PcieEcamMode = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6;
-    } else {
-      PcieEcamMode &= ~ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6;
+  if (PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_AUTO) {
+    switch (OsType) {
+      case ExitBootServicesOsWindows:
+        PcieEcamMode = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6;
+        break;
+      case ExitBootServicesOsLinux:
+        PcieEcamMode = ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON;
+        break;
+      default:
+        PcieEcamMode = ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV;
+        break;
     }
   }
 
   switch (PcieEcamMode) {
     case ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6:
-      PcieBusMin         = 0;
-      PcieBusMax         = PCIE_BUS_LIMIT;
-      McfgMainBusMin     = 1;
-      McfgSplitRootPort  = TRUE;
-      McfgSingleDevQuirk = FALSE;
+      //
+      // This workaround ought to filter duplicate devices on the primary
+      // and secondary buses, but it appears that recent Windows versions
+      // only do so for bus numbers 0 and 1.
+      // Not all segments start at bus 0 anymore, since they need to be made
+      // distinct to the SMMU & ITS (see Rk3588Pcie.h). However, these features
+      // can't be enabled in Windows anyway, so we'll disable the bus offset and
+      // let it reassign bus numbers from 0.
+      // It's possible to enable PcieBusOffset by disabling McfgDeviceFiltering,
+      // but this will hide the root port and may cause the system to lock-up
+      // with certain endpoints that have broken CFG0 filtering.
+      //
+      PcieBusOffset         = FALSE;
+      McfgDeviceFiltering   = !PcieBusOffset;
+      McfgSplitConfigSpaces = TRUE;
 
       Index  = 0;
       Status = AcpiLocateTableBySignature (
@@ -281,44 +295,97 @@ AcpiFixupPcieEcam (
       break;
 
     case ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON:
-      PcieBusMin         = 0;
-      PcieBusMax         = PCIE_BUS_LIMIT;
-      McfgMainBusMin     = 0;
-      McfgSplitRootPort  = FALSE;
-      McfgSingleDevQuirk = FALSE;
+      PcieBusOffset         = TRUE;
+      McfgDeviceFiltering   = TRUE;
+      McfgSplitConfigSpaces = FALSE;
 
       CopyMem (McfgTable->Header.Header.OemId, "AMAZON", sizeof (McfgTable->Header.Header.OemId));
       McfgTable->Header.Header.OemTableId = SIGNATURE_64 ('G', 'R', 'A', 'V', 'I', 'T', 'O', 'N');
       break;
 
     default: // ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV
-      PcieBusMin         = 1;
-      PcieBusMax         = 1;
-      McfgMainBusMin     = 1;
-      McfgSplitRootPort  = FALSE;
-      McfgSingleDevQuirk = TRUE;
+      PcieBusOffset         = TRUE;
+      McfgDeviceFiltering   = FALSE;
+      McfgSplitConfigSpaces = FALSE;
       break;
   }
 
-  for (Index = 0; Index < ARRAY_SIZE (McfgTable->MainEntries); Index++) {
-    if (McfgSingleDevQuirk) {
-      if ((PcdGet32 (PcdPcieEcamCompliantSegmentsMask) & (1 << Index)) == 0) {
-        McfgTable->MainEntries[Index].BaseAddress += 0x8000;
+  PcieBusMin = 0;
+  PcieBusMax = PCIE_BUS_COUNT - 1;
+
+  if (!McfgDeviceFiltering) {
+    //
+    // Skip the primary bus as it only spans a single function (root port)
+    // and the remaining DBI region has to be filtered out.
+    //
+    PcieBusMin = 1;
+
+    if (!McfgSplitConfigSpaces) {
+      //
+      // It's not possible to have more than a single bus due to the
+      // the device offset workaround below.
+      //
+      PcieBusMax = PcieBusMin;
+    }
+  }
+
+  for (Index = 0; Index < NUM_PCIE_CONTROLLER; Index++) {
+    McfgTable->ConfigSpaces[0][Index].PciSegmentGroupNumber = Index;
+    McfgTable->ConfigSpaces[0][Index].BaseAddress           = PCIE_CFG_BASE (Index) + PCIE_BUS_BASE_OFFSET (Index);
+    McfgTable->ConfigSpaces[0][Index].StartBusNumber        = PcieBusMin;
+    McfgTable->ConfigSpaces[0][Index].EndBusNumber          = PcieBusMax;
+
+    if (PcieBusOffset) {
+      McfgTable->ConfigSpaces[0][Index].BaseAddress    -= PCIE_BUS_BASE_OFFSET (Index);
+      McfgTable->ConfigSpaces[0][Index].StartBusNumber += PCIE_BUS_BASE (Index);
+      McfgTable->ConfigSpaces[0][Index].EndBusNumber   += PCIE_BUS_BASE (Index);
+    }
+
+    if (McfgSplitConfigSpaces) {
+      McfgTable->ConfigSpaces[1][Index].PciSegmentGroupNumber = McfgTable->ConfigSpaces[0][Index].PciSegmentGroupNumber;
+      McfgTable->ConfigSpaces[1][Index].StartBusNumber        = McfgTable->ConfigSpaces[0][Index].StartBusNumber;
+
+      if (McfgDeviceFiltering) {
+        //
+        // The OS is expected to filter devices on the primary and secondary
+        // buses, so we can expose the root port in this entry (primary bus)
+        // and remaining buses in the first entry.
+        //
+        McfgTable->ConfigSpaces[1][Index].BaseAddress  = PCIE_DBI_BASE (Index);
+        McfgTable->ConfigSpaces[1][Index].EndBusNumber = McfgTable->ConfigSpaces[1][Index].StartBusNumber;
+
+        McfgTable->ConfigSpaces[0][Index].StartBusNumber += 1;
+      } else {
+        //
+        // The OS will not filter devices on any bus, so we can't expose
+        // the root port. Use this entry for buses following secondary and
+        // limit the first entry to the secondary bus only, so the device
+        // offset workaround below can work.
+        //
+        McfgTable->ConfigSpaces[1][Index].BaseAddress     = McfgTable->ConfigSpaces[0][Index].BaseAddress;
+        McfgTable->ConfigSpaces[1][Index].StartBusNumber += 1;
+        McfgTable->ConfigSpaces[1][Index].EndBusNumber    = McfgTable->ConfigSpaces[0][Index].EndBusNumber;
+
+        McfgTable->ConfigSpaces[0][Index].EndBusNumber = McfgTable->ConfigSpaces[0][Index].StartBusNumber;
       }
     }
 
-    McfgTable->MainEntries[Index].StartBusNumber = McfgMainBusMin;
-    McfgTable->MainEntries[Index].EndBusNumber   = PcieBusMax;
+    if (!McfgDeviceFiltering &&
+        ((PcdGet32 (PcdPcieEcamCompliantSegmentsMask) & (1 << Index)) == 0))
+    {
+      McfgTable->ConfigSpaces[0][Index].BaseAddress += 0x8000;
+    }
   }
 
-  if (McfgSplitRootPort == FALSE) {
-    McfgTable->Header.Header.Length -= sizeof (McfgTable->RootPortEntries);
+  if (!McfgSplitConfigSpaces) {
+    McfgTable->Header.Header.Length = OFFSET_OF (RK3588_MCFG_TABLE, ConfigSpaces[1]);
   }
 
   AcpiUpdateChecksum ((UINT8 *)McfgTable, McfgTable->Header.Header.Length);
 
   AcpiUpdateSdtNameInteger (mDsdtTable, "PBMI", PcieBusMin);
   AcpiUpdateSdtNameInteger (mDsdtTable, "PBMA", PcieBusMax);
+  AcpiUpdateSdtNameInteger (mDsdtTable, "PBOF", PcieBusOffset);
 
   return EFI_SUCCESS;
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf

@@ -2,7 +2,7 @@
 #
 #  Flattened Device Tree platform driver
 #
-#  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -28,15 +28,17 @@
 
 [LibraryClasses]
   BaseLib
+  BaseMemoryLib
   DebugLib
-  PrintLib
+  DevicePathLib
   DxeServicesLib
+  FdtLib
   MemoryAllocationLib
+  PrintLib
   RockchipPlatformLib
   UefiBootServicesTableLib
   UefiDriverEntryPoint
   UefiLib
-  FdtLib
 
 [Guids]
   gFdtTableGuid
@@ -53,6 +55,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatMode
   gRK3588TokenSpaceGuid.PcdFdtForceGop
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath
   gRK3588TokenSpaceGuid.PcdComboPhy0Mode
   gRK3588TokenSpaceGuid.PcdComboPhy1Mode
   gRK3588TokenSpaceGuid.PcdComboPhy2Mode

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c

@@ -1,12 +1,13 @@
 /** @file
  *
  *  Copyright (c) 2020, Jeremy Linton
- *  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+ *  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
  **/
 
+#include <Library/BaseMemoryLib.h>
 #include <Library/DebugLib.h>
 #include <Library/RockchipPlatformLib.h>
 #include <Library/UefiRuntimeServicesTableLib.h>
@@ -34,6 +35,23 @@ IsFdtCompatModeSupported (
   return PlatformGetDtbFileGuid (CompatMode) != NULL;
 }
 
+STATIC
+BOOLEAN
+IsAcpiPcieEcamCompatModeSupported (
+  IN UINT32  CompatMode
+  )
+{
+  switch (CompatMode) {
+    case ACPI_PCIE_ECAM_COMPAT_MODE_AUTO:
+    case ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV:
+    case ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6:
+    case ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON:
+      return TRUE;
+  }
+
+  return FALSE;
+}
+
 VOID
 EFIAPI
 ApplyConfigTableVariables (
@@ -49,12 +67,13 @@ SetupConfigTableVariables (
   VOID
   )
 {
-  UINTN       Size;
-  UINT32      Var32;
-  UINT8       Var8;
-  EFI_STATUS  Status;
-  UINTN       Index;
-  UINT32      FirstFdtCompatModeSupported;
+  UINTN                            Size;
+  UINT32                           Var32;
+  UINT8                            Var8;
+  EFI_STATUS                       Status;
+  UINTN                            Index;
+  UINT32                           FirstFdtCompatModeSupported;
+  FDT_OVERRIDE_PATH_VARSTORE_DATA  FdtOverridePath;
 
   Size   = sizeof (UINT32);
   Status = gRT->GetVariable (
@@ -77,7 +96,7 @@ SetupConfigTableVariables (
                   &Size,
                   &Var32
                   );
-  if (EFI_ERROR (Status)) {
+  if (EFI_ERROR (Status) || !IsAcpiPcieEcamCompatModeSupported (Var32)) {
     Status = PcdSet32S (PcdAcpiPcieEcamCompatMode, FixedPcdGet32 (PcdAcpiPcieEcamCompatModeDefault));
     ASSERT_EFI_ERROR (Status);
   }
@@ -147,4 +166,57 @@ SetupConfigTableVariables (
     Status = PcdSet8S (PcdFdtSupportOverrides, FixedPcdGet8 (PcdFdtSupportOverridesDefault));
     ASSERT_EFI_ERROR (Status);
   }
+
+  Size   = sizeof (UINT8);
+  Status = gRT->GetVariable (
+                  L"FdtOverrideFixup",
+                  &gRK3588DxeFormSetGuid,
+                  NULL,
+                  &Size,
+                  &Var8
+                  );
+  if (EFI_ERROR (Status)) {
+    Status = PcdSet8S (PcdFdtOverrideFixup, FixedPcdGet8 (PcdFdtOverrideFixupDefault));
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  Size   = sizeof (FDT_OVERRIDE_PATH_VARSTORE_DATA);
+  Status = gRT->GetVariable (
+                  L"FdtOverrideBasePath",
+                  &gRK3588DxeFormSetGuid,
+                  NULL,
+                  &Size,
+                  &FdtOverridePath
+                  );
+  if (EFI_ERROR (Status) || (FdtOverridePath.Path[0] == L' ')) {
+    if (FixedPcdGetSize (PcdFdtOverrideBasePathDefault) <= Size) {
+      Status = PcdSetPtrS (PcdFdtOverrideBasePath, &Size, FixedPcdGetPtr (PcdFdtOverrideBasePathDefault));
+    } else {
+      ASSERT (FALSE);
+      ZeroMem (&FdtOverridePath, Size);
+      Status = PcdSetPtrS (PcdFdtOverrideBasePath, &Size, &FdtOverridePath);
+    }
+
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  Size   = sizeof (FDT_OVERRIDE_PATH_VARSTORE_DATA);
+  Status = gRT->GetVariable (
+                  L"FdtOverrideOverlayPath",
+                  &gRK3588DxeFormSetGuid,
+                  NULL,
+                  &Size,
+                  &FdtOverridePath
+                  );
+  if (EFI_ERROR (Status) || (FdtOverridePath.Path[0] == L' ')) {
+    if (FixedPcdGetSize (PcdFdtOverrideOverlayPathDefault) <= Size) {
+      Status = PcdSetPtrS (PcdFdtOverrideOverlayPath, &Size, FixedPcdGetPtr (PcdFdtOverrideOverlayPathDefault));
+    } else {
+      ASSERT (FALSE);
+      ZeroMem (&FdtOverridePath, Size);
+      Status = PcdSetPtrS (PcdFdtOverrideOverlayPath, &Size, &FdtOverridePath);
+    }
+
+    ASSERT_EFI_ERROR (Status);
+  }
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf

@@ -108,6 +108,12 @@
   gRK3588TokenSpaceGuid.PcdFdtForceGop
   gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePathDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPathDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath
 
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput
   gRK3588TokenSpaceGuid.PcdCoolingFanState

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni

@@ -239,11 +239,10 @@
 #string STR_ACPI_PCIE_ECAM_COMPAT_MODE_PROMPT              #language en-US "PCIe ECAM Compatibility Mode"
 #string STR_ACPI_PCIE_ECAM_COMPAT_MODE_HELP                #language en-US "Choose how to expose the non-standard PCIe configuration space to the OS.\n\n"
                                                                            "Single Device - compatible with all OSes. Allows usage of a single or multi-function device. Switches are not supported.\n\n"
-                                                                           "NXPMX6 - compatible with Windows. Exposes the full bus topology and supports switches.\n\n"
-                                                                           "AMAZON GRAVITON - compatible with Linux. Exposes the full bus topology and supports switches.\n\n"
-                                                                           "The Auto modes select NXPMX6 for Windows and fall back to the second option when booting other OSes."
-#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV   #language en-US "Auto (NXPMX6 + Single Device)"
-#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON     #language en-US "Auto (NXPMX6 + AMAZON GRAVITON)"
+                                                                           "NXPMX6 - compatible with Windows. Switches are supported.\n\n"
+                                                                           "AMAZON GRAVITON - compatible with Linux. Switches are supported.\n\n"
+                                                                           "The Auto mode selects NXPMX6 for Windows, AMAZON GRAVTION for Linux or Single Device for other OSes."
+#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_AUTO                #language en-US "Auto"
 #string STR_ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV          #language en-US "Single Device"
 #string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6              #language en-US "NXPMX6"
 #string STR_ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON            #language en-US "AMAZON GRAVITON"
@@ -258,11 +257,43 @@
 #string STR_FDT_COMPAT_MODE_MAINLINE                       #language en-US "Mainline"
 
 #string STR_FDT_FORCE_GOP_PROMPT                           #language en-US "Force UEFI GOP Display"
-#string STR_FDT_FORCE_GOP_HELP                             #language en-US "This option allows using the basic display output provided by UEFI GOP (HDMI/DP/DSI) on Linux kernels older than 6.13, which lack native driver support."
+#string STR_FDT_FORCE_GOP_HELP                             #language en-US "This option allows using the basic display output provided by UEFI GOP (HDMI/DP/DSI) on older Linux kernels, which lack native driver support."
 
 #string STR_FDT_SUPPORT_OVERRIDES_PROMPT                   #language en-US "Support DTB override & overlays"
 #string STR_FDT_SUPPORT_OVERRIDES_HELP                     #language en-US "Enable or disable support for overriding the firmware-provided DTB and installing overlays.\n\nCheck firmware documentation for more details."
 
+#string STR_FDT_OVERRIDE_SUBTITLE                          #language en-US "DTB Override"
+
+#string STR_FDT_OVERRIDE_FIXUP_PROMPT                      #language en-US "Firmware Fix-ups"
+#string STR_FDT_OVERRIDE_FIXUP_HELP                        #language en-US "Enable or disable firmware fix-ups for the DTB override."
+
+#string STR_FDT_OVERRIDE_BASE_PATH_PROMPT                  #language en-US "Preferred Base DTB Path"
+#string STR_FDT_OVERRIDE_BASE_PATH_HELP                    #language en-US "Enter the preferred file or directory path for the base DTB override, relative to the file system root.\n\n"
+                                                                           "Once a boot device is selected, the firmware will scan all the supported file systems on it (FAT, ext4) and try to load the specified override.\n\n"
+                                                                           "- If a directory path is specified, the platform FDT file name will be appended to it (<PLATFORM-DT-NAME>).\n"
+                                                                           "- If a file path is specified, it will be used as is.\n"
+                                                                           "- If no override exists, the firmware-provided DTB will be used instead.\n\n"
+                                                                           "Examples:\n"
+                                                                           " \\dtbs\n"
+                                                                           " \\dtbs\\my-board.dtb\n\n"
+                                                                           "Default alternative paths:\n"
+                                                                           " \\dtb\n"
+                                                                           " \\dtb\\base\n"
+                                                                           " \\dtb\\rockchip\n\n"
+                                                                           "To reset this option to the default value, set it to a space character, save and reboot."
+
+#string STR_FDT_OVERRIDE_OVERLAY_PATH_PROMPT               #language en-US "Preferred Overlays Path"
+#string STR_FDT_OVERRIDE_OVERLAY_PATH_HELP                 #language en-US "Enter the preferred directory path for the DTB overlays, relative to the file system root.\n\n"
+                                                                           "Once a boot device is selected, the firmware will scan all the supported file systems on it (FAT, ext4) and try to load all overlays in the specified directory.\n\n"
+                                                                           "- If the installation of an overlay fails, all other overlays will be discarded.\n\n"
+                                                                           "Examples:\n"
+                                                                           " \\my-overlays\n"
+                                                                           " \\dtbs\\overlays\n\n"
+                                                                           "Default alternative paths:\n"
+                                                                           " \\dtb\\overlays\n"
+                                                                           " \\dtb\\overlays\\<PLATFORM-DT-NAME>\n\n"
+                                                                           "To reset this option to the default value, set it to a space character, save and reboot."
+
 /*
  * Cooling fan configuration
  */

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr

@@ -213,6 +213,21 @@ formset
       name  = FdtSupportOverrides,
       guid  = RK3588DXE_FORMSET_GUID;
 
+    efivarstore UINT8,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FdtOverrideFixup,
+      guid  = RK3588DXE_FORMSET_GUID;
+
+    efivarstore FDT_OVERRIDE_PATH_VARSTORE_DATA,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FdtOverrideBasePath,
+      guid  = RK3588DXE_FORMSET_GUID;
+
+    efivarstore FDT_OVERRIDE_PATH_VARSTORE_DATA,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = FdtOverrideOverlayPath,
+      guid  = RK3588DXE_FORMSET_GUID;
+
     efivarstore COOLING_FAN_STATE_VARSTORE_DATA,
       attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
       name  = CoolingFanState,
@@ -806,8 +821,7 @@ formset
             help        = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_HELP),
             flags       = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
             default     = FixedPcdGet32 (PcdAcpiPcieEcamCompatModeDefault),
-            option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV, flags = 0;
-            option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON, flags = 0;
+            option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_AUTO), value = ACPI_PCIE_ECAM_COMPAT_MODE_AUTO, flags = 0;
             option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV), value = ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV, flags = 0;
             option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6, flags = 0;
             option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON), value = ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON, flags = 0;
@@ -852,6 +866,38 @@ formset
             option text = STRING_TOKEN(STR_DISABLED), value = FALSE, flags = 0;
             option text = STRING_TOKEN(STR_ENABLED), value = TRUE, flags = 0;
           endoneof;
+
+          suppressif ideqval FdtSupportOverrides.State == 0;
+            subtitle text = STRING_TOKEN(STR_NULL_STRING);
+            subtitle text = STRING_TOKEN(STR_FDT_OVERRIDE_SUBTITLE);
+
+            oneof varid = FdtOverrideFixup,
+              prompt      = STRING_TOKEN(STR_FDT_OVERRIDE_FIXUP_PROMPT),
+              help        = STRING_TOKEN(STR_FDT_OVERRIDE_FIXUP_HELP),
+              flags       = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED,
+              default     = FixedPcdGet8 (PcdFdtOverrideFixupDefault),
+              option text = STRING_TOKEN(STR_DISABLED), value = FALSE, flags = 0;
+              option text = STRING_TOKEN(STR_ENABLED), value = TRUE, flags = 0;
+            endoneof;
+
+            subtitle text = STRING_TOKEN(STR_NULL_STRING);
+
+            string varid = FdtOverrideBasePath.Path,
+              prompt  = STRING_TOKEN(STR_FDT_OVERRIDE_BASE_PATH_PROMPT),
+              help    = STRING_TOKEN(STR_FDT_OVERRIDE_BASE_PATH_HELP),
+              flags   = INTERACTIVE | RESET_REQUIRED,
+              minsize = 0,
+              maxsize = FDT_OVERRIDE_PATH_MAX_LEN,
+            endstring;
+
+            string varid = FdtOverrideOverlayPath.Path,
+              prompt  = STRING_TOKEN(STR_FDT_OVERRIDE_OVERLAY_PATH_PROMPT),
+              help    = STRING_TOKEN(STR_FDT_OVERRIDE_OVERLAY_PATH_HELP),
+              flags   = INTERACTIVE | RESET_REQUIRED,
+              minsize = 0,
+              maxsize = FDT_OVERRIDE_PATH_MAX_LEN,
+            endstring;
+          endif;
         endif;
     endform;
 

edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h

@@ -118,8 +118,7 @@
 #pragma pack(push, 1)
 typedef struct {
   EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER                           Header;
-  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE    MainEntries[NUM_PCIE_CONTROLLER];
-  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE    RootPortEntries[NUM_PCIE_CONTROLLER];
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE    ConfigSpaces[2][NUM_PCIE_CONTROLLER];
 } RK3588_MCFG_TABLE;
 #pragma pack(pop)
 

edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h

@@ -1,10 +1,11 @@
 /** @file
-*
-*  Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
+ *
+ *  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
+ *  Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
 
 #ifndef RK3588PCIE_H
 #define RK3588PCIE_H
@@ -21,47 +22,72 @@ PciePinmuxInit (
   );
 
 //
-// PCIe 3x4 is the first PCIe controller in memory, the others
-// immediately follow it in the order of the segments below.
+// Hardware mapping
+//
+// PCIe 3x4 is the first PCIe controller in memory, immediately followed
+// by the others in the order of the segments below.
 //
-
 #define NUM_PCIE_CONTROLLER  5
 
-/*
- * All pcie controllers supports PCIe 3.0
- * Here we name them using their device tree name in the linux kernel source
- */
 #define PCIE_SEGMENT_PCIE30X4  0
 #define PCIE_SEGMENT_PCIE30X2  1
 #define PCIE_SEGMENT_PCIE20L0  2
 #define PCIE_SEGMENT_PCIE20L1  3
 #define PCIE_SEGMENT_PCIE20L2  4
 
-#define PCIE_3X4_APB_BASE  0xfe150000
-#define PCIE_3X4_DBI_BASE  0xa40000000ULL
-#define PCIE_3X4_CFG_BASE  0x900000000ULL
-#define PCIE_3X4_MEM_BASE  0xf0000000
+#define PCIE_3X4_APB_BASE     0xfe150000
+#define PCIE_3X4_DBI_BASE     0xa40000000ULL
+#define PCIE_3X4_MMIO32_BASE  0xf0000000
+#define PCIE_3X4_MMIO64_BASE  0x900000000ULL
 
-#define PCIE_APB_SIZE  SIZE_64KB
-#define PCIE_DBI_SIZE  SIZE_4MB
-#define PCIE_CFG_SIZE  SIZE_1GB
-#define PCIE_MEM_SIZE  SIZE_16MB
+#define PCIE_APB_SIZE     SIZE_64KB
+#define PCIE_DBI_SIZE     SIZE_4MB
+#define PCIE_MMIO32_SIZE  SIZE_16MB
+#define PCIE_MMIO64_SIZE  SIZE_1GB
 
-#define PCIE_MEM64_OFFSET  0x10000000ULL
+#define PCIE_APB_BASE(Segment)     (PCIE_3X4_APB_BASE + (Segment * PCIE_APB_SIZE))
+#define PCIE_DBI_BASE(Segment)     (PCIE_3X4_DBI_BASE + (Segment * 1ULL * PCIE_DBI_SIZE))
+#define PCIE_MMIO32_BASE(Segment)  (PCIE_3X4_MMIO32_BASE + (Segment * PCIE_MMIO32_SIZE))
+#define PCIE_MMIO64_BASE(Segment)  (PCIE_3X4_MMIO64_BASE + (Segment * 1ULL * PCIE_MMIO64_SIZE))
 
-#define PCIE_APB_BASE(Segment)  (PCIE_3X4_APB_BASE + (Segment * PCIE_APB_SIZE))
-#define PCIE_DBI_BASE(Segment)  (PCIE_3X4_DBI_BASE + (Segment * 1ULL * PCIE_DBI_SIZE))
-#define PCIE_CFG_BASE(Segment)  (PCIE_3X4_CFG_BASE + (Segment * 1ULL * PCIE_CFG_SIZE))
+//
+// Software mapping
+//
+// Since the MMIO32 space is absurdly small, we only use it for I/O.
+// ECAM and MEM32 go at the top of the MMIO64 space. This preserves
+// the MEM64 alignment and allows EDK2 to allocate up to a single
+// large 512 MB BAR + remaining space until the ECAM base.
+//
+#define PCIE_MEM32_SIZE           SIZE_128MB
+#define PCIE_MEM32_BASE(Segment)  (PCIE_MMIO64_BASE (Segment) + PCIE_MMIO64_SIZE - PCIE_MEM32_SIZE)
+//
+// Likely not an issue here, but let's play it safe and ensure the bus
+// address does not overlap inbound system RAM, since I've seen DMA
+// corruption on a different IP due to this.
+//
+#define PCIE_MEM32_BUS_BASE              PCIE_MMIO32_BASE (0)
+#define PCIE_MEM32_TRANSLATION(Segment)  (PCIE_MEM32_BASE (Segment) - PCIE_MEM32_BUS_BASE)
 
-#define PCIE_MEM_BASE(Segment)    (PCIE_3X4_MEM_BASE + (Segment * PCIE_MEM_SIZE))
-#define PCIE_MEM64_BASE(Segment)  (PCIE_CFG_BASE(Segment) + PCIE_MEM64_OFFSET)
+// ECAM must start on a 256 MB boundary (28-bit B/D/F addressing).
+#define PCIE_CFG_SIZE           (SIZE_256MB - PCIE_MEM32_SIZE)
+#define PCIE_CFG_BASE(Segment)  (PCIE_MMIO64_BASE (Segment) + PCIE_MMIO64_SIZE - SIZE_256MB)
 
-#define PCIE_IO_BASE  0x0000
-#define PCIE_IO_SIZE  SIZE_64KB
-#define PCIE_IO_XLATE(Segment)  (PCIE_CFG_BASE(Segment) + PCIE_CFG_SIZE - PCIE_IO_SIZE)
+#define PCIE_MEM64_SIZE           (PCIE_MMIO64_SIZE - PCIE_MEM32_SIZE - PCIE_CFG_SIZE)
+#define PCIE_MEM64_BASE(Segment)  PCIE_MMIO64_BASE (Segment)
 
-#define PCIE_MEM64_SIZE  (PCIE_CFG_SIZE - PCIE_IO_SIZE - PCIE_MEM64_OFFSET)
+#define PCIE_IO_SIZE                  SIZE_64KB
+#define PCIE_IO_BASE(Segment)         (PCIE_MMIO32_BASE (Segment) + SIZE_1MB)
+#define PCIE_IO_BUS_BASE              0x0000
+#define PCIE_IO_TRANSLATION(Segment)  (PCIE_IO_BASE (Segment) - PCIE_IO_BUS_BASE)
 
-#define PCIE_BUS_LIMIT  252 // limited by CFG1 iATU window size
+//
+// All RCs share a single SMMU and two ITS blocks. To prevent overlapping
+// Requester IDs, we need to space segments by <PCIE_BUS_COUNT> bus numbers.
+// It doesn't seem possible to encode the segment number instead.
+//
+#define PCIE_BUS_COUNT                 (PCIE_CFG_SIZE / SIZE_1MB / NUM_PCIE_CONTROLLER)
+#define PCIE_BUS_BASE(Segment)         (Segment * PCIE_BUS_COUNT)
+#define PCIE_BUS_LIMIT(Segment)        (PCIE_BUS_BASE (Segment) + PCIE_BUS_COUNT - 1)
+#define PCIE_BUS_BASE_OFFSET(Segment)  (PCIE_BUS_BASE (Segment) * SIZE_1MB)
 
 #endif

edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h

@@ -65,11 +65,10 @@ typedef struct {
   UINT32    Mode;
 } CONFIG_TABLE_MODE_VARSTORE_DATA;
 
-#define ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV         0x00000001
-#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6             0x00000002
-#define ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON           0x00000004
-#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV  0x00000003
-#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON    0x00000006
+#define ACPI_PCIE_ECAM_COMPAT_MODE_AUTO        0x00000000
+#define ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV  0x00000001
+#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6      0x00000002
+#define ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON    0x00000004
 typedef struct {
   UINT32    Mode;
 } ACPI_PCIE_ECAM_COMPAT_MODE_VARSTORE_DATA;
@@ -89,6 +88,12 @@ typedef struct {
   UINT8    State;
 } FDT_SUPPORT_OVERRIDES_VARSTORE_DATA;
 
+#define FDT_OVERRIDE_PATH_MAX_LEN   254
+#define FDT_OVERRIDE_PATH_MAX_SIZE  255
+typedef struct {
+  CHAR16    Path[FDT_OVERRIDE_PATH_MAX_SIZE];
+} FDT_OVERRIDE_PATH_VARSTORE_DATA;
+
 #define COOLING_FAN_STATE_DISABLED  0
 #define COOLING_FAN_STATE_ENABLED   1
 typedef struct {

edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf

@@ -24,6 +24,7 @@
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
   Silicon/Rockchip/RK3588/RK3588.dec
+  UefiCpuPkg/UefiCpuPkg.dec
 
 [LibraryClasses]
   DebugLib

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c

@@ -5,6 +5,7 @@
  *  Copyright (c) 2023, David Gwynne <david@gwynne.id.au>
  *  Copyright (c) 2023, Jared McNeill <jmcneill@invisible.ca>
  *  Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
+ *  Copyright (c) 2025, Mario Bălănică <mariobalanica02@gmail.com>
  *
  *  SPDX-License-Identifier: BSD-2-Clause-Patent
  *
@@ -18,100 +19,85 @@
 #include <Library/CruLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 #include <Library/PcdLib.h>
+#include <VarStoreData.h>
 
-#define PCIE30_PHY_GRF  0xfd5b8000
-/* PCIEPHY_GRF */
-#define GRF_PCIE30_PHY_CON(n)       (PCIE30_PHY_GRF + 0x0000 + (n) * 0x4)         /* 0 .. 9 */
-#define GRF_PCIE30_PHY_STATUS(n)    (PCIE30_PHY_GRF + 0x0080 + (n) * 0x4)         /* 0 .. 2 */
-#define GRF_PCIE30_PHY_PRT0_CON(n)  (PCIE30_PHY_GRF + 0x0100 + (n) * 0x4)         /* 0 .. 39 */
-/* CON1 and CON9 */
-#define GRF_PCIE30PHY_DA_OCM_MASK  BIT15
-#define GRF_PCIE30PHY_DA_OCM       BIT15
-/* CON5 */
-#define GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT  0
-#define GRF_PCIE30PHY_LANE0_LINK_NUM_MASK   (0xfU << GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT)
-/* CON6 */
-#define GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT  0
-#define GRF_PCIE30PHY_LANE1_LINK_NUM_MASK   (0xfU << GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT)
+#define PHP_GRF_BASE       0xfd5b0000
+#define PCIE3PHY_GRF_BASE  0xfd5b8000
 
-/* STATUS0 */
-#define GRF_PCIE30PHY_SRAM_INIT_DONE  BIT14
+/* PHP_GRF */
+#define PHP_GRF_PCIESEL_CON  0x100
 
-#define SOFTRST_INDEX  27
-#define SOFTRST_BIT    14
+/* PCIE3PHY_GRF */
+#define PCIE3PHY_GRF_CMN_CON0      0x0
+#define PCIE3PHY_GRF_PHY0_STATUS1  0x904
+#define PCIE3PHY_GRF_PHY1_STATUS1  0xa04
+#define PCIE3PHY_SRAM_INIT_DONE(reg)  ((reg & BIT0) != 0)
 
-STATIC
-VOID
-GrfUpdateRegister (
-  IN EFI_PHYSICAL_ADDRESS  Reg,
-  IN UINT32                Mask,
-  IN UINT32                Val
-  )
-{
-  ASSERT ((Mask & ~0xFFFF) == 0);
-  ASSERT ((Val & ~0xFFFF) == 0);
-  ASSERT ((Mask & Val) == Val);
-
-  MmioWrite32 (Reg, (Mask << 16) | Val);
-}
+STATIC EFI_STATUS  mInitStatus = EFI_NOT_READY;
 
 EFI_STATUS
 Pcie30PhyInit (
   VOID
   )
 {
-  // UINTN Retry;
+  UINT8   Mode;
+  UINT32  Reg;
+  UINTN   Retry;
+
+  if (mInitStatus != EFI_NOT_READY) {
+    return mInitStatus;
+  }
+
+  Mode = PcdGet8 (PcdPcie30PhyMode);
 
   DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n"));
-  DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", PcdGet8 (PcdPcie30PhyMode)));
+  DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", Mode));
 
-  // MicroSecondDelay(100000);
-
-  /* Disable power domain */
+  /* Enable power domain */
   MmioWrite32 (0xFD8D8150, 0x1 << 23 | 0x1 << 21);  // PD_PCIE & PD_PHP
 
-  /* Phy mode: from pcd Pcie30PhyMode */
-  MmioWrite32 (GRF_PCIE30_PHY_CON (0), (0x7 << 16) | PcdGet8 (PcdPcie30PhyMode));
+  /* Phy mode */
+  Reg = Mode;
+  MmioWrite32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_CMN_CON0, (0x7 << 16) | Reg);
 
+  /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
+  Reg &= 0x3;
+  if (Reg) {
+    MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, (0x3 << 16) | Reg);
+  }
+
+  /* Assert PHY Reset */
   MmioWrite32 (0xFD7C8A00, (0x1 << 10) | (0x1 << 26));
+  MicroSecondDelay (1);
 
   /* Deassert PCIe PMA output clamp mode */
-  MmioWrite32 (GRF_PCIE30_PHY_CON (0), (0x1 << 8) | (0x1 << 24));
+  MmioWrite32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_CMN_CON0, (0x1 << 8) | (0x1 << 24));
 
   /* Deassert PHY Reset */
   MmioWrite32 (0xFD7C8A00, (0x1 << 26));
 
-  // /* Enable clocks */
-  // PmuCruEnableClock (2, 13);
-  // PmuCruEnableClock (2, 14);
-  // CruEnableClock (33, 8);
+  for (Retry = 500; Retry > 0; Retry--) {
+    Reg = MmioRead32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_PHY0_STATUS1);
+    if (Mode == PCIE30_PHY_MODE_AGGREGATION) {
+      Reg &= MmioRead32 (PCIE3PHY_GRF_BASE + PCIE3PHY_GRF_PHY1_STATUS1);
+    }
 
-  // /* Assert reset */
-  // CruAssertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
-  // gBS->Stall (1000);
+    if (PCIE3PHY_SRAM_INIT_DONE (Reg)) {
+      break;
+    }
 
-  // MicroSecondDelay (1);
+    MicroSecondDelay (100);
+  }
 
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (9), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (5), GRF_PCIE30PHY_LANE0_LINK_NUM_MASK, PCIE30PHY_LANE0_LINK_NUM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (6), GRF_PCIE30PHY_LANE1_LINK_NUM_MASK, PCIE30PHY_LANE1_LINK_NUM);
-  // GrfUpdateRegister (GRF_PCIE30_PHY_CON (1), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM);
-
-  // /* De-assert reset */
-  // CruDeassertSoftReset (SOFTRST_INDEX, SOFTRST_BIT);
-
-  // for (Retry = 500; Retry > 0; Retry--) {
-  //     MicroSecondDelay (100);
-
-  //     if ((MmioRead32 (GRF_PCIE30_PHY_STATUS (0)) & GRF_PCIE30PHY_SRAM_INIT_DONE) != 0) {
-  //         break;
-  //     }
-  // }
-  // if (Retry == 0) {
-  //     DEBUG ((DEBUG_WARN, "PCIe30: Failed to enable PCIe 3.0 PHY\n"));
-  //     return EFI_TIMEOUT;
-  // }
+  if (Retry == 0) {
+    DEBUG ((DEBUG_WARN, "PCIe30: PHY init failed\n"));
+    mInitStatus = EFI_TIMEOUT;
+    goto Exit;
+  }
 
   DEBUG ((DEBUG_INFO, "PCIe30: PHY init complete\n"));
-  return EFI_SUCCESS;
+  mInitStatus = EFI_SUCCESS;
+
+Exit:
+  return mInitStatus;
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf

@@ -26,11 +26,11 @@
   ArmPlatformPkg/ArmPlatformPkg.dec
   Silicon/Rockchip/RK3588/RK3588.dec
   Silicon/Rockchip/RockchipPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
 
 [LibraryClasses]
   ArmLib
   BaseVariableLib
-  FdtLib
   IoLib
   MemoryAllocationLib
   PcdLib

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c

@@ -3,7 +3,7 @@
   Copyright 2017, 2020 NXP
   Copyright 2021-2023, Jared McNeill <jmcneill@invisible.ca>
   Copyright 2023, Molly Sophia <mollysophia379@gmail.com>
-  Copyright (c) 2023-2024, Mario Bălănică <mariobalanica02@gmail.com>
+  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -574,18 +574,14 @@ InitializePciHost (
   UINT32  Segment
   )
 {
-  EFI_PHYSICAL_ADDRESS  ApbBase  = PCIE_APB_BASE (Segment);
-  EFI_PHYSICAL_ADDRESS  DbiBase  = PCIE_DBI_BASE (Segment);
-  EFI_PHYSICAL_ADDRESS  PcieBase = PCIE_CFG_BASE (Segment);
+  EFI_PHYSICAL_ADDRESS  ApbBase = PCIE_APB_BASE (Segment);
+  EFI_PHYSICAL_ADDRESS  DbiBase = PCIE_DBI_BASE (Segment);
+  EFI_PHYSICAL_ADDRESS  CfgBase;
+  EFI_PHYSICAL_ADDRESS  CfgSize;
+  EFI_STATUS            Status;
   UINTN                 Retry;
   UINT32                LinkSpeed;
   UINT32                LinkWidth;
-  UINT64                Cfg0Base;
-  UINT64                Cfg0Size;
-  UINT64                Cfg1Base;
-  UINT64                Cfg1Size;
-  UINT64                PciIoBase;
-  UINT64                PciIoSize;
   UINT8                 Pcie30PhyMode;
 
   Pcie30PhyMode = PcdGet8 (PcdPcie30PhyMode);
@@ -610,7 +606,6 @@ InitializePciHost (
 
   /* Log settings */
   DEBUG ((DEBUG_INIT, "\nPCIe: Segment %u\n", Segment));
-  DEBUG ((DEBUG_INIT, "PCIe: PciExpressBaseAddress 0x%lx\n", PcieBase));
   DEBUG ((DEBUG_INIT, "PCIe: ApbBase 0x%lx\n", ApbBase));
   DEBUG ((DEBUG_INIT, "PCIe: DbiBase 0x%lx\n", DbiBase));
   DEBUG ((DEBUG_INIT, "PCIe: NumLanes %u\n", LinkWidth));
@@ -622,7 +617,10 @@ InitializePciHost (
 
   if ((Segment == PCIE_SEGMENT_PCIE30X4) || (Segment == PCIE_SEGMENT_PCIE30X2)) {
     /* Configure PCIe 3.0 PHY */
-    Pcie30PhyInit ();
+    Status = Pcie30PhyInit ();
+    if (EFI_ERROR (Status)) {
+      return Status;
+    }
   }
 
   /* Combo PHY for PCIe 2.0 is configured earlier by RK3588Dxe */
@@ -641,16 +639,41 @@ InitializePciHost (
   PciSetupBars (DbiBase);
 
   DEBUG ((DEBUG_INIT, "PCIe: Setup iATU\n"));
-  Cfg0Base  = SIZE_1MB;
-  Cfg0Size  = SIZE_64KB;
-  Cfg1Base  = SIZE_2MB;
-  Cfg1Size  = 0x10000000UL - (SIZE_2MB + SIZE_64KB);
-  PciIoBase = 0x2FFF0000UL;
-  PciIoSize = SIZE_64KB;
+  CfgBase = PCIE_CFG_BASE (Segment) + PCIE_BUS_BASE_OFFSET (Segment);
+  CfgSize = PCIE_BUS_COUNT * SIZE_1MB;
 
-  PciSetupAtu (DbiBase, 0, IATU_TYPE_CFG0, PcieBase + Cfg0Base, Cfg0Base, Cfg0Size);
-  PciSetupAtu (DbiBase, 1, IATU_TYPE_CFG1, PcieBase + Cfg1Base, Cfg1Base, Cfg1Size);
-  PciSetupAtu (DbiBase, 2, IATU_TYPE_IO, PcieBase + PciIoBase, 0, PciIoSize);
+  PciSetupAtu (
+    DbiBase,
+    0,
+    IATU_TYPE_CFG0,
+    CfgBase + SIZE_1MB,   // Bus 1
+    SIZE_1MB,
+    SIZE_64KB             // Should be 32KB but granule is 64KB (see PciValidateCfg0())
+    );
+  PciSetupAtu (
+    DbiBase,
+    1,
+    IATU_TYPE_CFG1,
+    CfgBase + SIZE_2MB,   // Bus 2 and above
+    SIZE_2MB,
+    CfgSize - SIZE_2MB
+    );
+  PciSetupAtu (
+    DbiBase,
+    2,
+    IATU_TYPE_IO,
+    PCIE_IO_BASE (Segment),
+    PCIE_IO_BUS_BASE,
+    PCIE_IO_SIZE
+    );
+  PciSetupAtu (
+    DbiBase,
+    3,
+    IATU_TYPE_MEM,
+    PCIE_MEM32_BASE (Segment),
+    PCIE_MEM32_BUS_BASE,
+    PCIE_MEM32_SIZE
+    );
 
   DEBUG ((DEBUG_INIT, "PCIe: Set link speed\n"));
   PciSetupLinkSpeed (DbiBase, LinkSpeed, LinkWidth);
@@ -688,7 +711,7 @@ InitializePciHost (
   PciGetLinkSpeedWidth (DbiBase, &LinkSpeed, &LinkWidth);
   PciPrintLinkSpeedWidth (LinkSpeed, LinkWidth);
 
-  PciValidateCfg0 (Segment, PcieBase + Cfg0Base);
+  PciValidateCfg0 (Segment, CfgBase + SIZE_1MB);
 
   return EFI_SUCCESS;
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c

@@ -1,6 +1,7 @@
 /** @file
   PCI Host Bridge Library instance for Rockchip Rk3588
 
+  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
   Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
   Copyright (c) 2021, Jared McNeill <jmcneill@invisible.ca>
   Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
@@ -192,15 +193,16 @@ PciHostBridgeGetRootBridges (
     mPciRootBridges[Loop].AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
                                                   EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
 
-    mPciRootBridges[Loop].Bus.Base  = 0;
-    mPciRootBridges[Loop].Bus.Limit = PCIE_BUS_LIMIT;
+    mPciRootBridges[Loop].Bus.Base  = PCIE_BUS_BASE (Idx);
+    mPciRootBridges[Loop].Bus.Limit = PCIE_BUS_LIMIT (Idx);
 
-    mPciRootBridges[Loop].Io.Base        = PCIE_IO_BASE;
+    mPciRootBridges[Loop].Io.Base        = PCIE_IO_BUS_BASE;
     mPciRootBridges[Loop].Io.Limit       = mPciRootBridges[Loop].Io.Base + PCIE_IO_SIZE - 1;
-    mPciRootBridges[Loop].Io.Translation = MAX_UINT64 - PCIE_IO_XLATE (Idx) + 1;
+    mPciRootBridges[Loop].Io.Translation = MAX_UINT64 - PCIE_IO_TRANSLATION (Idx) + 1;
 
-    mPciRootBridges[Loop].Mem.Base  = PCIE_MEM_BASE (Idx);
-    mPciRootBridges[Loop].Mem.Limit = mPciRootBridges[Loop].Mem.Base + PCIE_MEM_SIZE - 1;
+    mPciRootBridges[Loop].Mem.Base        = PCIE_MEM32_BUS_BASE;
+    mPciRootBridges[Loop].Mem.Limit       = mPciRootBridges[Loop].Mem.Base + PCIE_MEM32_SIZE - 1;
+    mPciRootBridges[Loop].Mem.Translation = MAX_UINT64 - PCIE_MEM32_TRANSLATION (Idx) + 1;
 
     mPciRootBridges[Loop].MemAbove4G.Base  = PCIE_MEM64_BASE (Idx);
     mPciRootBridges[Loop].MemAbove4G.Limit = mPciRootBridges[Loop].MemAbove4G.Base + PCIE_MEM64_SIZE - 1;
@@ -211,7 +213,6 @@ PciHostBridgeGetRootBridges (
     mPciRootBridges[Loop].PMemAbove4G.Limit = 0;
     mPciRootBridges[Loop].DevicePath        = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Idx];
 
-    DEBUG ((DEBUG_INFO, "0x%llx 0x%llx 0x%llx\n", mPciRootBridges[Loop].Mem.Base, mPciRootBridges[Loop].MemAbove4G.Base, mPciRootBridges[Loop].Io.Translation));
     Loop++;
   }
 

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c

@@ -1,6 +1,7 @@
 /** @file
   PCI Segment Library for Rockchip RK356x
 
+  Copyright (c) 2023-2025, Mario Bălănică <mariobalanica02@gmail.com>
   Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
   Copyright (c) 2021, Jared McNeill <jmcneill@invisible.ca>
   Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
@@ -36,6 +37,8 @@ typedef enum {
 #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \
   ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
 
+#define INVALID_PCI_ADDRESS  0xffffffff
+
 #define GET_SEG_NUM(Address)   ((Address >> 32) & 0xFFFF)
 #define GET_BUS_NUM(Address)   ((Address >> 20) & 0xFF)
 #define GET_DEV_NUM(Address)   ((Address >> 15) & 0x1F)
@@ -48,31 +51,42 @@ PciSegmentLibGetConfigBase (
   IN  UINT64  Address
   )
 {
+  UINT64  Base;
   UINT16  Segment;
   UINT8   Bus;
-  UINT16  Device;
+  UINT8   Device;
+  UINT8   Function;
 
-  Segment = GET_SEG_NUM (Address);
-  Bus     = GET_BUS_NUM (Address);
-  Device  = GET_DEV_NUM (Address);
+  Segment  = GET_SEG_NUM (Address);
+  Bus      = GET_BUS_NUM (Address);
+  Device   = GET_DEV_NUM (Address);
+  Function = GET_FUNC_NUM (Address);
 
-  ASSERT (Segment < NUM_PCIE_CONTROLLER);
-
-  // DEBUG ((DEBUG_ERROR, "PciSegmentLibGetConfigBase: Address=0x%lX, Bus=%d, Segment=%d\n",
-  //         Address, Bus, Segment));
-
-  // Ignore more than one device on bus 0 and 1 to hide duplicates/ghosts.
-  if ((Device > 0) && ((Bus == 0) || (Bus == 1))) {
-    return 0xffffffff;
+  if (Segment >= NUM_PCIE_CONTROLLER) {
+    ASSERT (FALSE);
+    return INVALID_PCI_ADDRESS;
   }
 
-  // The root port is not part of the main config space.
-  if (Bus == 0) {
-    return PCIE_DBI_BASE (Segment);
+  //
+  // The primary bus can only contain a single function (the root port).
+  // The secondary bus can only contain a single device.
+  //
+  if (((Bus == PCIE_BUS_BASE (Segment)) && (Device + Function > 0)) ||
+      ((Bus == PCIE_BUS_BASE (Segment) + 1) && (Device > 0)))
+  {
+    return INVALID_PCI_ADDRESS;
   }
 
-  // Here starts the not-quite-compliant ECAM space.
-  return PCIE_CFG_BASE (Segment);
+  if (Bus == PCIE_BUS_BASE (Segment)) {
+    // The root port is not part of the main config space.
+    Base     = PCIE_DBI_BASE (Segment);
+    Address -= PCIE_BUS_BASE_OFFSET (Segment);
+  } else {
+    // Here starts the almost-compliant ECAM space.
+    Base = PCIE_CFG_BASE (Segment);
+  }
+
+  return Base + (UINT32)Address;
 }
 
 /**
@@ -95,21 +109,17 @@ PciSegmentLibReadWorker (
   UINT64  Base;
 
   Base = PciSegmentLibGetConfigBase (Address);
-
-  if (Base == 0xFFFFFFFF) {
+  if (Base == INVALID_PCI_ADDRESS) {
     return Base;
   }
 
-  // DEBUG ((DEBUG_ERROR, "PciSegmentLibReadWorker: Address=0x%lX, Base=0x%lX, Width=%u\n",
-  //         Address, Base, Width));
-
   switch (Width) {
     case PciCfgWidthUint8:
-      return MmioRead8 (Base + (UINT32)Address);
+      return MmioRead8 (Base);
     case PciCfgWidthUint16:
-      return MmioRead16 (Base + (UINT32)Address);
+      return MmioRead16 (Base);
     case PciCfgWidthUint32:
-      return MmioRead32 (Base + (UINT32)Address);
+      return MmioRead32 (Base);
     default:
       ASSERT (FALSE);
   }
@@ -139,23 +149,19 @@ PciSegmentLibWriteWorker (
   UINT64  Base;
 
   Base = PciSegmentLibGetConfigBase (Address);
-
-  if (Base == 0xFFFFFFFF) {
+  if (Base == INVALID_PCI_ADDRESS) {
     return Base;
   }
 
-  // DEBUG ((DEBUG_ERROR, "PciSegmentLibWriteWorker: Address=0x%lX, Base=0x%lX, Width=%u\n",
-  //       Address, Base, Width));
-
   switch (Width) {
     case PciCfgWidthUint8:
-      MmioWrite8 (Base + (UINT32)Address, Data);
+      MmioWrite8 (Base, Data);
       break;
     case PciCfgWidthUint16:
-      MmioWrite16 (Base + (UINT32)Address, Data);
+      MmioWrite16 (Base, Data);
       break;
     case PciCfgWidthUint32:
-      MmioWrite32 (Base + (UINT32)Address, Data);
+      MmioWrite32 (Base, Data);
       break;
     default:
       ASSERT (FALSE);

edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec

@@ -51,6 +51,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatModeDefault|0|UINT32|0x00010351
   gRK3588TokenSpaceGuid.PcdFdtForceGopDefault|0|UINT8|0x00010352
   gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault|0|UINT8|0x00010353
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault|0|UINT8|0x00010354
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePathDefault|L""|VOID*|0x00010355
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPathDefault|L""|VOID*|0x00010356
 
   gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|FALSE|BOOLEAN|0x10401
 
@@ -120,6 +123,19 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatMode|0|UINT32|0x00000351
   gRK3588TokenSpaceGuid.PcdFdtForceGop|0|UINT8|0x00000352
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|0|UINT8|0x00000353
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup|0|UINT8|0x00000354
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath|{ 0x0 }|FDT_OVERRIDE_PATH_VARSTORE_DATA|0x00000355 {
+    <Packages>
+      Silicon/Rockchip/RK3588/RK3588.dec
+    <HeaderFiles>
+      VarStoreData.h
+  }
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath|{ 0x0 }|FDT_OVERRIDE_PATH_VARSTORE_DATA|0x00000356 {
+    <Packages>
+      Silicon/Rockchip/RK3588/RK3588.dec
+    <HeaderFiles>
+      VarStoreData.h
+  }
 
   gRK3588TokenSpaceGuid.PcdCoolingFanState|0|UINT32|0x00000401
   gRK3588TokenSpaceGuid.PcdCoolingFanSpeed|0|UINT32|0x00000402

edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc

@@ -51,11 +51,10 @@
   DEFINE CONFIG_TABLE_MODE_FDT          =  0x00000002
   DEFINE CONFIG_TABLE_MODE_ACPI_FDT     =  0x00000003
 
-  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV            = 0x00000001
-  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6                = 0x00000002
-  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON              = 0x00000004
-  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV     = 0x00000003
-  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON       = 0x00000006
+  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_AUTO        = 0x00000000
+  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV  = 0x00000001
+  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6      = 0x00000002
+  DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON    = 0x00000004
 
   DEFINE FDT_COMPAT_MODE_UNSUPPORTED    = 0
   DEFINE FDT_COMPAT_MODE_VENDOR         = 1
@@ -282,10 +281,13 @@
   # ACPI / Device Tree support flags and default values
   #
   gRK3588TokenSpaceGuid.PcdConfigTableModeDefault|$(CONFIG_TABLE_MODE_ACPI_FDT)
-  gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault|$(ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV)
+  gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault|$(ACPI_PCIE_ECAM_COMPAT_MODE_AUTO)
   gRK3588TokenSpaceGuid.PcdFdtCompatModeDefault|$(FDT_COMPAT_MODE_MAINLINE)
   gRK3588TokenSpaceGuid.PcdFdtForceGopDefault|FALSE
   gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault|FALSE
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault|TRUE
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePathDefault|L""
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPathDefault|L""
 
   #
   # Display support flags and default values
@@ -373,6 +375,9 @@
   gRK3588TokenSpaceGuid.PcdFdtCompatMode|L"FdtCompatMode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtCompatModeDefault
   gRK3588TokenSpaceGuid.PcdFdtForceGop|L"FdtForceGop"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtForceGopDefault
   gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|L"FdtSupportOverrides"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtSupportOverridesDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideFixup|L"FdtOverrideFixup"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdFdtOverrideFixupDefault
+  gRK3588TokenSpaceGuid.PcdFdtOverrideBasePath|L"FdtOverrideBasePath"|gRK3588DxeFormSetGuid|0x0|{ 0x0 }
+  gRK3588TokenSpaceGuid.PcdFdtOverrideOverlayPath|L"FdtOverrideOverlayPath"|gRK3588DxeFormSetGuid|0x0|{ 0x0 }
 
   #
   # Cooling Fan

edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc

@@ -66,6 +66,16 @@
   DEFINE DEBUG_PROPERTY_MASK             = 0x0f
 !endif
 
+  #
+  # Default support flags
+  #
+!ifndef RK_X86_EMULATOR_ENABLE
+  DEFINE RK_X86_EMULATOR_ENABLE         = TRUE
+!endif
+!ifndef RK_AMD_GOP_ENABLE
+  DEFINE RK_AMD_GOP_ENABLE              = TRUE
+!endif
+
 ################################################################################
 #
 # Library Class section - list of all common Library Classes needed by Rockchip platforms.
@@ -127,11 +137,6 @@
   # SCMI Mailbox Transport Layer
   ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf
 
-  # SMC/HVC dependencies
-  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
-  ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
-  ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf
-
   #
   # Secure Boot dependencies
   #
@@ -168,9 +173,11 @@
   CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
   DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
   CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
-  ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
-  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+  ArmSmcLib|MdePkg/Library/ArmSmcLib/ArmSmcLib.inf
+  ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf
+  ArmMmuLib|UefiCpuPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
   ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmTransferListLib|ArmPkg/Library/ArmTransferListLib/ArmTransferListLib.inf
   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
 
   # UART libraries
@@ -196,7 +203,7 @@
   SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
 
   # Flattened Device Tree (FDT) access library
-  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+  FdtLib|MdePkg/Library/BaseFdtLib/BaseFdtLib.inf
 
   VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
   VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
@@ -284,10 +291,8 @@
 
   PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
 
-  ## Fixed compile error after upgrade to 14.10
   PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
-  ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
   BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
 
 [LibraryClasses.common.DXE_CORE]
@@ -434,7 +439,6 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
   # Set timer interrupt to be triggerred in 1ms to avoid missing
   # serial terminal input characters.
   gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
-  gArmTokenSpaceGuid.PcdVFPEnabled|1
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32
 
   #
@@ -478,6 +482,7 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
   ArmPlatformPkg/PeilessSec/PeilessSec.inf {
     <LibraryClasses>
       NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+      PeilessSecMeasureLib|SecurityPkg/Library/PeilessSecMeasureLib/PeilessSecMeasureLibNull.inf
   }
 
   #
@@ -629,6 +634,12 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
   Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf
   Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
 
+!if $(RK_AMD_GOP_ENABLE) == TRUE
+  Drivers/AMD/Gop/AmdGopOpRomOverrideDxe.inf
+  Drivers/AMD/Gop/AmdGopPreSoc15Dxe.inf
+  Drivers/AMD/Gop/AmdGopPostSoc15Dxe.inf
+!endif
+
   #
   # USB Support
   #
@@ -699,6 +710,7 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
 !endif
   }
   FatPkg/EnhancedFatDxe/Fat.inf
+!include Features/Ext4Pkg/Ext4.dsc.inc
   MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
 
   #
@@ -781,6 +793,13 @@ FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf
   #
   EmbeddedPkg/Drivers/MemoryAttributeManagerDxe/MemoryAttributeManagerDxe.inf
 
+  #
+  # x64 Binary Compatibility Support
+  #
+!if $(RK_X86_EMULATOR_ENABLE) == TRUE
+  Emulator/X86EmulatorDxe/X86EmulatorDxe.inf
+!endif
+
   #
   # Bds
   #

edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.h

@@ -18,7 +18,6 @@
 
 #include <Protocol/ComponentName.h>
 #include <Protocol/ComponentName2.h>
-#include <Protocol/DeviceIo.h>
 #include <Protocol/DriverBinding.h>
 #include <Protocol/SdMmcPassThru.h>
 

edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.c

@@ -991,11 +991,11 @@ DwMmcCreateTrb (
   IN EFI_EVENT                            Event
   )
 {
-  DW_MMC_HC_TRB          *Trb;
-  EFI_STATUS             Status;
-  EFI_TPL                OldTpl;
-  EFI_IO_OPERATION_TYPE  Flag;
-  UINTN                  MapLength;
+  DW_MMC_HC_TRB      *Trb;
+  EFI_STATUS         Status;
+  EFI_TPL            OldTpl;
+  DMA_MAP_OPERATION  MapOperation;
+  UINTN              MapLength;
 
   Trb = AllocateZeroPool (sizeof (DW_MMC_HC_TRB));
   if (Trb == NULL) {
@@ -1035,9 +1035,9 @@ DwMmcCreateTrb (
     Trb->Mode = SdMmcPioMode;
   } else {
     if (Trb->Read) {
-      Flag = EfiBusMasterWrite;
+      MapOperation = MapOperationBusMasterWrite;
     } else {
-      Flag = EfiBusMasterRead;
+      MapOperation = MapOperationBusMasterRead;
     }
 
     if (Private->Slot[Trb->Slot].CardType == SdCardType) {
@@ -1046,7 +1046,7 @@ DwMmcCreateTrb (
       Trb->UseFifo = FALSE;
       if (Trb->DataLen) {
         MapLength = Trb->DataLen;
-        Status    = DmaMap (Flag, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);
+        Status    = DmaMap (MapOperation, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);
 
         /*        Status = DevIo->Map (
                                   DevIo,