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optimize timing of 4.3inch 480x272 rgb-lcd

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wuxx
2020-12-20 19:20:53 +08:00
parent 9e3937bbcc
commit 201b354067
3 changed files with 2 additions and 2 deletions
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demo/rgblcd.bin
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4
src/basic/verilog/rgblcd/top.v
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@@ -15,11 +15,11 @@ module TOP
wire PCLK;
/* 24Mhz $icepll -o 24Mhz */
/* 18Mhz $icepll -o 18Mhz */
SB_PLL40_PAD #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0111111), // DIVF = 63
.DIVF(7'b0101111), // DIVF = 48
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) uut (