Merge pull request #10 from nalzok/master

Added example for the PmodOLED module

src/basic/verilog/pmodoled2/Makefile

@@ -0,0 +1,31 @@
+all: pmodoled2.bin
+
+ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$9}')
+${info iCELink path: $(ICELINK_DIR)}
+
+pmodoled2.bin: pmodoled2.v uart.v pmodoled2.pcf
+	yosys -p "synth_ice40 -top top -json $(@:.bin=).json" $(filter %.v,$^)
+	nextpnr-ice40 \
+        --up5k \
+        --package sg48 \
+        --json $(@:.bin=).json \
+        --pcf $(filter %.pcf,$^) \
+		--asc $(@:.bin=).asc
+	icepack $(@:.bin=).asc $(@:.bin=).bin
+
+clean:
+	rm -f pmodoled2.json pmodoled2.asc pmodoled2.bin
+
+prog_flash: pmodoled2.bin
+	@if [ -d '$(ICELINK_DIR)' ]; \
+        then \
+        cp -R pmodoled2.bin $(ICELINK_DIR); \
+        else \
+        echo "iCELink not found"; \
+        exit 1; \
+        fi
+
+.PHONY: subdirs
+.PHONY: subdirs $(SUBDIRS)
+.PHONY: clean
+.PHONY: prog_flash

src/basic/verilog/pmodoled2/README.md

@@ -0,0 +1,54 @@
+# Courtesy of https://github.com/laanwj/yosys-ice-experiments
+
+- Display: Digilent PmodOLED 128x32 grid SSD1306 module
+- Connected to iCEstick evaluation board
+- Using 4-wire SPI 10MHz max
+- iCE40HX-1k FPGA, programmed using open source FPGA toolchain Yosys + Arachne-pnr + IceStorm
+- Image generated using Python script, sent from PC through FTDI serial-over-USB 1000000 baud
+
+```
++------+         +------------+        +------+      +---------+
+| Host |<------->| FTDI 2232H |------->| FPGA |----->| Display |
++------+   USB   +------------+ Serial +------+ SPI  +---------+
+                                1M baud         (pmod conn)
+```
+
+PmodOLED
+------------
+
+Connector Pmod
+
+Pin   | Signal    | Description
+------|-----------|---------------------------------
+1     | CS        | SPI Chip Select (Slave Select)
+2     | SDIN      | SPI Data In (MOSI)
+3     | None      | Unused Pin
+4     | SCLK      | SPI Clock
+7     | D/C       | Data/Command Control
+8     | RES       | Power Reset
+9     | VBATC     | V BAT Battery Voltage Control
+10    | VDDC      | V DD Logic Voltage Control
+5, 11 | GND       |
+6, 12 | VCC       | Power Supply G
+
+Pins on FPGA
+--------------
+
+Connecting PMODoled: on module: when connector is to the left, pin 1 is at the top right.
+Pin 1 is clearly indicated on the iCEstick itself.
+
+Pin  | Signal  | Pkgpin
+-----|---------|---------
+1    | PIO1_02 | 78
+2    | PIO1_03 | 79
+3    | PIO1_04 | 80
+4    | PIO1_05 | 81
+5    | GND     |
+6    | VCC     |
+7    | PIO1_06 | 87
+8    | PIO1_07 | 88
+9    | PIO1_08 | 90
+10   | PIO1_09 | 91
+11   | GND     |
+12   | VCC     |
+

src/basic/verilog/pmodoled2/clear.py

@@ -0,0 +1,9 @@
+#!/usr/bin/env python3
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''Clear screen'''
+from __future__ import division,print_function
+from oleddisplay import OledDisplay
+
+disp = OledDisplay()

src/basic/verilog/pmodoled2/cursestest.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''Typing directly to display'''
+from __future__ import division,print_function
+import sys,time
+from imagefont import ImageFont
+from util import bin8,load_bw_image,tile_image
+from oleddisplay import OledDisplay,DC
+import time
+import curses
+
+font = ImageFont("fonts/oddball.png")
+disp = OledDisplay()
+
+stdscr = curses.initscr()
+curses.noecho()
+curses.cbreak()
+stdscr.keypad(1)
+
+try:
+    disp.update(on=DC) # send display data
+    ofs = 0
+    while True:
+        ch = stdscr.getch()
+        if ch == 27:
+            break
+        elif ch == 10:
+            n = 16 - (ofs % 16)
+            disp.spi(font.glyphs_bw[0x20] * n)
+            ofs += n
+        elif ch < len(font.glyphs_bw):
+            disp.spi(font.glyphs_bw[ch])
+            ofs += 1
+    disp.update(off=DC) # back to command mode
+finally:
+    curses.nocbreak()
+    stdscr.keypad(0)
+    curses.echo()
+    curses.endwin()
+

src/basic/verilog/pmodoled2/display.py

@@ -0,0 +1,46 @@
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''
+Base classes for Display, console-based emulation
+'''
+from __future__ import division,print_function
+import sys
+
+class BaseDisplay:
+    '''
+    Base class for external grid displays.
+    '''
+    width = None
+    height = None
+    def __init__(self):
+        pass
+
+    def set_image(self, data):
+        '''
+        Send image to display.
+        Input: width * height 2D array of 0,1 values.
+        '''
+        pass
+
+class ConsoleDisplay(BaseDisplay):
+    '''
+    Simple console based 'display'.
+    '''
+    def __init__(self):
+        sys.stdout.write('\x1b[H\x1b[J')
+        self.width = 128
+        self.height = 32
+
+    def set_image(self, data):
+        sys.stdout.write('\x1b[H')
+        for y in range(0,self.height):
+            s = []
+            for x in range(0,self.width):
+                if data[y][x]:
+                    s.append('x')
+                else:
+                    s.append(' ')
+            sys.stdout.write((''.join(s)) + '\n')
+
+

src/basic/verilog/pmodoled2/fonts/credits.md

@@ -0,0 +1,6 @@
+Font: oddball.png
+http://forums.tigsource.com/index.php?topic=8834.0
+Topic: Oddball's small offerings
+David Williamson
+This work is licensed under a Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported License.
+

src/basic/verilog/pmodoled2/imagefont.py

@@ -0,0 +1,56 @@
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''
+Simple image font
+'''
+# TODO: support different image formats than RGBA
+from __future__ import division,print_function
+from PIL import Image
+
+THRESHOLD=128 # pixel values >= this are considered hi, else lo
+ALPHA_COMP=3  # component to use for b/w extraction
+
+class ImageFont:
+    def __init__(self, imgname, glyph_w=8, glyph_h=8):
+        self.glyph_w = glyph_w
+        self.glyph_h = glyph_h
+
+        img = Image.open(imgname)
+
+        self.chars_w = img.size[0]//glyph_w
+        self.chars_h = img.size[1]//glyph_h
+        self.numchars = self.chars_w * self.chars_h
+
+        self._extract_glyphs(img)
+        self._convert_to_bw()
+
+    def _extract_glyphs(self,img):
+        '''Extract RGBA glyphs'''
+        data = list(img.getdata())
+        self.glyphs = []
+        for ch in range(self.numchars):
+            basex = (ch % self.chars_w) * self.glyph_w
+            basey = (ch // self.chars_w) * self.glyph_h
+            baseaddr = basey*img.size[0] + basex
+            glyph_data = []
+            for yy in range(self.glyph_h):
+                glyph_data.append(data[baseaddr:baseaddr+self.glyph_w])
+                baseaddr += img.size[0]
+            self.glyphs.append(glyph_data)
+
+    def _convert_to_bw(self):
+        '''Extract b/w binary glyphs'''
+        self.glyphs_bw = []
+        for ch in range(self.numchars):
+            glyph_in = self.glyphs[ch]
+            glyph_data = []
+            for xx in range(self.glyph_w):
+                glyph_col = 0
+                for yy in range(self.glyph_h):
+                    if glyph_in[yy][xx][ALPHA_COMP] >= THRESHOLD:
+                        glyph_col |= 1<<yy
+                glyph_data.append(glyph_col)
+            self.glyphs_bw.append(glyph_data)
+
+

src/basic/verilog/pmodoled2/images/cthulhu.svg

@@ -0,0 +1,105 @@
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src/basic/verilog/pmodoled2/images/source.md

@@ -0,0 +1,3 @@
+cthulhu.svg
+http://pcon.github.io/design/cthulhu/
+

src/basic/verilog/pmodoled2/mandelbrot.py

@@ -0,0 +1,90 @@
+#!/usr/bin/env python3
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''
+Smooth Mandelbrot rendering using numpy.
+'''
+from __future__ import division,print_function
+from display import ConsoleDisplay
+from oleddisplay import OledDisplay
+import numpy as np
+
+def mandelbrot(c, iterations=20):
+    '''
+    Compute mandelbrot set at coordinate c,
+    return True if inside or False if outside.
+    '''
+    z = 0+0j
+    i = 0
+    while abs(z) < 2 and i < iterations:
+        z = (z * z) + c
+        i += 1
+    return i >= iterations
+
+def find_edge(c1, c2, func):
+    '''
+    Find edge of mandelbrot set using bisection method.
+    Input: c1, a point on the set, c2 a point not on the set.
+    Returns: (c1',c2')
+    '''
+    midpoint = (c1 + c2) / 2
+    if func(midpoint):
+        return (midpoint, c2) # midpoint on set, c2 not on set
+    else:
+        return (c1, midpoint) # c1 on set, midpoint not on set
+
+def random_point():
+    '''Find random point on Mandelbrot set'''
+    import random
+    ofs1 = complex(0,0) # on mandelbrot set
+    ofs2 = (1j ** (random.random()*4)) * 2 # not on mandelbrot set
+    #ofs1 = complex(0.02996, 0.80386) # on mandelbrot set
+    #ofs2 = complex(0.02997, 0.80386) # not on mandelbrot set
+    for i in range(64):
+        (ofs1, ofs2) = find_edge(ofs1, ofs2, mandelbrot)
+    return ofs1
+    # what are interesting points?
+    # https://en.wikipedia.org/wiki/Misiurewicz_point
+
+#disp = ConsoleDisplay()
+disp = OledDisplay()
+
+WW = disp.width
+HH = disp.height
+fovy = HH/WW
+
+xx,yy = np.meshgrid(np.linspace(-1.0, 1.0, WW), np.linspace(-1.0, 1.0, HH))
+ii = xx + 1j*yy*fovy
+iterations_outer = 2
+iterations_inner = 20
+
+while True:
+    ofs = random_point()
+    #ofs = -0.77568377 + 0.13646737j   # M23,2
+    #ofs = -1.54368901269109  # M3,1
+    #ofs = -0.1010 + 0.9562j  # M4,1
+    #ofs = 0.3994999999988 + 0.195303j
+
+    frame = 0
+    while True:
+        zoom = 2.0**((frame-600)/200.0)
+
+        # Compute mandelbrot in parallel with numpy
+        c = ii / zoom + ofs
+        z = np.zeros((HH,WW),dtype=complex)
+        for i in range(iterations_inner):
+            if i == iterations_outer: # for showing outer boundary
+                zb = z
+            z = (z * z) + c
+        data = np.abs(z) < 2
+        boundary = np.abs(zb) < 2
+
+        # Boundary
+        disp.set_image(np.invert(data) & boundary)
+
+        if np.all(data) or not np.any(data):
+            # stop if there is nothing to see anymore
+            break
+        frame += 1
+

src/basic/verilog/pmodoled2/oleddisplay.py

@@ -0,0 +1,102 @@
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''
+Serial OLED display driving logic.
+'''
+from __future__ import division,print_function
+import serial,sys,time
+from imagefont import ImageFont
+from util import bin8,load_bw_image,tile_image,detect_serial
+from display import BaseDisplay
+
+# Flag bits
+CS   = (1<<4) # chip select if low
+DC   = (1<<3)  # command if low, data if high
+RES  = (1<<2)  # reset if low
+VBATC= (1<<1)  # power control display; active-low
+VDDC = (1<<0)  # power control logic; active-low
+
+class OledDisplay(BaseDisplay):
+    width = 128
+    height = 32
+    def __init__(self, port=None):
+        if port is None:
+            ports = detect_serial()
+            if len(ports) == 0:
+                raise IOError('No iCEStick devices detected')
+            if len(ports) > 1:
+                raise IOError('Multiple possible iCEStick devices detected. Need to specify which one to use')
+            port = ports[0]
+        self.conn = serial.serial_for_url(port, 1000000,
+             parity=serial.PARITY_NONE, rtscts=False, xonxoff=False, timeout=1)
+
+        self.value = 0
+
+        # Send 33 NOPs to reset and sync serial
+        self.conn.write(bytearray([0x00] * 33))
+
+        # Select chip, go to command mode, turn off reset and power
+        self.update(off=CS|DC,on=RES|VBATC|VDDC)
+        # 1. Apply power to VDD.
+        self.update(off=VDDC)
+        # 2. Send Display Off command (0xAE)
+        self.spi(0xAE)
+        # Reset
+        self.update(off=RES)
+        time.sleep(0.000003) # at least 3us
+        self.update(on=RES)
+        # 3. Initialize display to desired operating mode.
+        self.spi([0x8D,0x14]) # charge pump
+        self.spi([0xD9,0xF1]) # precharge
+        # 4. Clear screen.
+        self.spi([0x20,0x00]) # horizontal addressing mode
+        self.spi([0x22,0x00,0x03]) # page start and end address (create wraparound at line 32)
+        self.set_image([[0]*self.width for x in range(self.height)])
+        # 5. Apply power to VBAT.
+        self.update(off=VBATC)
+        # Misc configuration
+        self.spi([0x81,0x0F]) # contrast
+        self.spi([0xA1,0xC8]) # invert display
+        self.spi([0xDA,0x20]) # comconfig
+
+        # 6. Delay 100ms.
+        time.sleep(0.1)
+        # 7. Send Display On command (0xAF).
+        self.spi(0xAF)
+
+        # Debugging:
+        #spi(0xA5) # full display
+        #spi(0xA4) # display according to memory
+        #spi([0x20,0x01]) # vertical addressing mode
+
+    def update(self, off=0, on=0):
+        self.value &= ~off
+        self.value |= on
+        self.conn.write(bytearray([0b00100000 | self.value]))
+        #print('Write %s SCLK=%i SDIN=%i' % (bin8(value), bool(value&SCLK), bool(value&SDIN)))
+        #print('OUT %02x' % (0b00100000 | value))
+
+    def spi(self, data_values):
+        '''Clock 8-bit value(s) to SPI'''
+        import binascii
+        if not isinstance(data_values, list):
+            data_values = [data_values]
+        # Value of SDIN is sampled at SCLK's rising edge
+        # so put in new bit at falling edge
+        # Data is clocked from bit 7 (MSB) to bit 0 (LSB)
+        ptr = 0
+        while ptr < len(data_values):
+            n = min(len(data_values)-ptr, 16)
+            self.conn.write(bytearray([0b00010000 | (n-1)] + data_values[ptr:ptr+n]))
+            # print('SPI %02x %s' % (0b00010000 | (n-1), binascii.b2a_hex(bytearray(data_values[ptr:ptr+n]))))
+            ptr += n
+  
+    def set_image(self, data):
+        '''Send 128x32 image to display.
+        Input must be 128x32 array of booleans or 0/1.
+        '''
+        self.update(on=DC) # send display data
+        self.spi(tile_image(data))
+        self.update(off=DC) # back to command mode
+

src/basic/verilog/pmodoled2/pmodoled2.pcf

@@ -0,0 +1,21 @@
+set_io TXD          6
+set_io RXD          4
+set_io clk          35
+set_io resetq       18
+
+# LEDs (PMOD 3)
+set_io LED0         27
+set_io LED1         25
+set_io LED2         21
+set_io LED3         23
+set_io LED4         26
+
+# PMOD OLED module connected
+set_io PMOD_CS      46
+set_io PMOD_SDIN    44
+set_io PMOD_SCLK    37
+set_io PMOD_DC      45
+set_io PMOD_RES     43
+set_io PMOD_VBATC   38
+set_io PMOD_VDDC    36
+

src/basic/verilog/pmodoled2/pmodoled2.py

@@ -0,0 +1,73 @@
+#!/usr/bin/env python3
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''Implementation of pmodoled2a in terms of OledDisplay'''
+from __future__ import division,print_function
+import serial,sys,time
+from imagefont import ImageFont
+from util import bin8,load_bw_image,tile_image
+from oleddisplay import OledDisplay,DC
+
+font = ImageFont("fonts/oddball.png")
+disp = OledDisplay()
+
+screen = 0
+while True:
+    #disp.spi([0xB0,0x00,0x10]) # reset write location (alt: set end address appropriately)
+    disp.update(on=DC) # send display data
+    # Build image
+    #screen = 3
+    if screen == 0:
+        data = [0]*(128*32//8)
+        ptr = 0
+        for ch in u"\u0157 \u0158 \u0157 Ph'nglui Mglw'nafh Cthulhu R'lyeh wgah'nagl fhtagn \u0157 \u0158 \u0157":
+            for col in font.glyphs_bw[ord(ch)]:
+                data[ptr] = col
+                ptr += 1
+    elif screen == 1:
+        data = load_bw_image('images/cthulhu.png', ofsy=8)
+    elif screen == 2:
+        scratch = [[0] * 128 for y in range(32)]
+        for l in range(16):
+            for y in range(32):
+                scratch[y][l*8+4] = 1
+        for l in range(4):
+            for x in range(128):
+                scratch[l*8+4][x] = 1
+        data = tile_image(scratch)
+    elif screen == 3:
+        import random
+        shuffle = [x for x in range(64)]
+        '''
+        bs = [5,1,2,3,4,0]
+        for x in range(64):
+            bits = [((x>>b)&1) for b in range(6)]
+            shuffle[x] = sum(bits[bs[b]]<<b for b in range(6))
+        '''
+        for x in range(64):
+            if (x % 3)==0:
+                a = shuffle[x]
+                shuffle[x] = 63-x
+                shuffle[63-x] = a
+
+        data = [0]*(128*32//8)
+        ptr = 0
+        for x in range(64):
+            x_ = shuffle[x]
+            for l in range(8):
+                vv = 0
+                for i in range(8):
+                    bit = random.randint(0, 64) < x_
+                    vv |= bit << i
+                data[ptr] = vv
+                ptr += 1
+
+    # Send image
+    disp.spi(data)
+
+    disp.update(off=DC) # back to command mode
+
+    time.sleep(5)
+    screen = (screen + 1)% 4
+

src/basic/verilog/pmodoled2/pmodoled2.v

@@ -0,0 +1,114 @@
+// Copyright (c) 2015 Wladimir J. van der Laan
+// Distributed under the MIT software license, see the accompanying
+// file COPYING or http://www.opensource.org/licenses/mit-license.php.
+
+/* Very simple interface to PMOD SPI. Serial port accepts bytes in the
+* form:
+*    0001zzzz    Followed by z+1 bytes. Transfer data to SPI.
+*    001abcde    Set parallel control flags: a CS, b DC, c RES, e VBATC, f VDDC
+* */
+`timescale 1 ns / 1 ps
+
+`default_nettype none
+
+module top(input clk,
+
+           output TXD,        // UART TX
+           input RXD,         // UART RX
+
+           input resetq,
+
+           output LED0,  // Led
+           output LED1,  // Led
+           output LED2,  // Led
+           output LED4,  // Center led
+
+           output PMOD_CS,
+           output PMOD_SDIN,
+           output PMOD_SCLK,
+           output PMOD_DC,
+           output PMOD_RES,
+           output PMOD_VBATC,
+           output PMOD_VDDC,
+);
+    localparam MHZ = 12;
+
+    // ######   UART   ##########################################
+    //
+    reg uart0_valid, uart0_busy;
+    wire [7:0] uart0_data_in;
+    wire [7:0] uart0_data_out = 0;
+    wire uart0_wr = 0;
+    wire uart0_rd = 1;
+    wire [31:0] uart_baud = 1000000;
+    buart #(.CLKFREQ(MHZ * 1000000)) _uart0 (
+     .clk(clk),
+     .resetq(resetq),
+     .baud(uart_baud),
+     .rx(RXD),
+     .tx(TXD),
+     .rd(uart0_rd),
+     .wr(uart0_wr),
+     .valid(uart0_valid),
+     .busy(uart0_busy),
+     .tx_data(uart0_data_out),
+     .rx_data(uart0_data_in));
+
+    reg led0;
+    reg led4;
+    reg [4:0] outcount;
+    reg halfclk;
+    reg [3:0] spi_count; /* number of data bits */
+    reg [7:0] spi_data_out;
+    reg uart_processed; /* UART input byte processed */
+
+    always @(posedge clk) begin
+      // Acme clock divider 12MHz -> 6MHz (to get under max 10MHz)
+      halfclk <= ~halfclk;
+      // Handle SPI output
+      if (halfclk) begin
+          // rising edge
+          PMOD_SCLK <= 1;
+      end else begin
+          // falling edge
+          if (|spi_count) begin
+              // if active - load new data bit on falling edge
+              {PMOD_SDIN,spi_data_out} <= {spi_data_out[7:0],1'b1};
+              PMOD_SCLK <= 0;
+              spi_count <= spi_count - 1;
+          end
+          LED1 <= spi_count; // Just for fun
+      end
+      // Handle UART input, if not processed yet
+      if (uart0_valid && !uart_processed) begin
+          uart_processed <= 1;
+          if (|outcount) begin
+              // SPI transmission in progress
+              outcount <= outcount - 1;
+              spi_data_out <= uart0_data_in;
+              spi_count <= 8;
+              led0 <= ~led0; // Blinkenlights just for fun
+          end else begin
+              // Handle opcodes
+              casez (uart0_data_in)
+                  8'b0001zzzz: begin
+                      // Send next N+1 bytes to SPI
+                      outcount <= (uart0_data_in & 5'b01111) + 1;
+                  end
+                  8'b001zzzzz: begin
+                      // Set flags
+                      {PMOD_CS,PMOD_DC,PMOD_RES,PMOD_VBATC,PMOD_VDDC} <= uart0_data_in[4:0];
+                  end
+                  default: ;
+              endcase
+              led4 <= ~led4; // Blinkenlights
+          end
+      end
+      // New data word coming in, reset processed flag
+      if (~uart0_valid)
+          uart_processed <= 0;
+    end
+    assign LED0 = led0;
+    assign LED4 = led4;
+
+endmodule // top

src/basic/verilog/pmodoled2/rawbench.py

@@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+'''Benchmark rendering'''
+from __future__ import division,print_function
+import serial,sys,time
+from imagefont import ImageFont
+from util import bin8,load_bw_image,tile_image
+from oleddisplay import OledDisplay,DC
+import time
+
+font = ImageFont("fonts/oddball.png")
+disp = OledDisplay()
+
+time_start = time.time()
+frames = 0
+fps_str = ''
+while True:
+    data = [0]*(128*32//8)
+    ptr = 0
+    for ch in str(frames):
+        data[ptr:ptr+8] = font.glyphs_bw[ord(ch)]
+        ptr += 8
+    ptr = 16*8
+    for ch in fps_str:
+        data[ptr:ptr+8] = font.glyphs_bw[ord(ch)]
+        ptr += 8
+
+    disp.update(on=DC) # send display data
+    disp.spi(data)
+    disp.update(off=DC) # back to command mode
+    frames += 1
+    if (frames%1000)==0:
+        curtime = time.time()
+        fps_str = '%.1f FPS' % (frames/(curtime-time_start))
+        print(fps_str)
+

src/basic/verilog/pmodoled2/uart.v

@@ -0,0 +1,187 @@
+// Copyright (c) 2015 James Bowman
+// Distributed under the MIT software license, see the accompanying
+// file COPYING or http://www.opensource.org/licenses/mit-license.php.
+
+// Borrowed from https://github.com/jamesbowman/swapforth/blob/master/j1a/icestorm/uart.v
+
+`default_nettype none
+
+module baudgen(
+  input wire clk,
+  input wire resetq,
+  input wire [31:0] baud,
+  input wire restart,
+  output wire ser_clk);
+  parameter CLKFREQ = 1000000;
+  /* needs to be (CLKFREQ).bit_length() + 1 */
+  parameter RWIDTH = 25;
+
+  wire [RWIDTH-1:0] aclkfreq = CLKFREQ;
+  reg [RWIDTH-1:0] d;
+  wire [RWIDTH-1:0] dInc = d[RWIDTH-1] ? ({4'd0, baud}) : (({4'd0, baud}) - aclkfreq);
+  wire [RWIDTH-1:0] dN = restart ? 0 : (d + dInc);
+  wire fastclk = ~d[RWIDTH-1];
+  assign ser_clk = fastclk;
+
+  always @(negedge resetq or posedge clk)
+  begin
+    if (!resetq) begin
+      d <= 0;
+    end else begin
+      d <= dN;
+    end
+  end
+endmodule
+
+/*
+
+-----+     +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
+     |     |     |     |     |     |     |     |     |     |     |     |
+     |start|  1  |  2  |  3  |  4  |  5  |  6  |  7  |  8  |stop1|stop2|
+     |     |     |     |     |     |     |     |     |     |     |  ?  |
+     +-----+-----+-----+-----+-----+-----+-----+-----+-----+           +
+
+*/
+
+module uart(
+   input wire clk,
+   input wire resetq,
+
+   output wire uart_busy,       // High means UART is transmitting
+   output reg uart_tx,          // UART transmit wire
+
+   input wire [31:0] baud,
+   input wire uart_wr_i,        // Raise to transmit byte
+   input wire [7:0] uart_dat_i
+);
+  parameter CLKFREQ = 1000000;
+
+  reg [3:0] bitcount;           // 0 means idle, so this is a 1-based counter
+  reg [8:0] shifter;
+
+  assign uart_busy = |bitcount;
+  wire sending = |bitcount;
+
+  wire ser_clk;
+
+  wire starting = uart_wr_i & ~uart_busy;
+  baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
+    .clk(clk),
+    .resetq(resetq),
+    .baud(baud),
+    .restart(1'b0),
+    .ser_clk(ser_clk));
+
+  always @(negedge resetq or posedge clk)
+  begin
+    if (!resetq) begin
+      uart_tx <= 1;
+      bitcount <= 0;
+      shifter <= 0;
+    end else begin
+      if (starting) begin
+        shifter <= { uart_dat_i[7:0], 1'b0 };
+        bitcount <= 1 + 8 + 1;    // 1 start, 8 data, 1 stop
+      end
+
+      if (sending & ser_clk) begin
+        { shifter, uart_tx } <= { 1'b1, shifter };
+        bitcount <= bitcount - 4'd1;
+      end
+    end
+  end
+
+endmodule
+
+module rxuart(
+   input wire clk,
+   input wire resetq,
+   input wire [31:0] baud,
+   input wire uart_rx,      // UART recv wire
+   input wire rd,           // read strobe
+   output wire valid,       // has data 
+   output wire [7:0] data); // data
+  parameter CLKFREQ = 1000000;
+
+  reg [4:0] bitcount;
+  reg [7:0] shifter;
+
+  // On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
+
+  wire idle = &bitcount;
+  wire sample;
+  reg [2:0] hh = 3'b111;
+  wire [2:0] hhN = {hh[1:0], uart_rx};
+  wire startbit = idle & (hhN[2:1] == 2'b10);
+  wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
+
+  wire ser_clk;
+  baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
+    .clk(clk),
+    .baud({baud[30:0], 1'b0}),
+    .resetq(resetq),
+    .restart(startbit),
+    .ser_clk(ser_clk));
+
+  assign valid = (bitcount == 18);
+  reg [4:0] bitcountN;
+  always @*
+    if (startbit)
+      bitcountN = 0;
+    else if (!idle & !valid & ser_clk)
+      bitcountN = bitcount + 5'd1;
+    else if (valid & rd)
+      bitcountN = 5'b11111;
+    else
+      bitcountN = bitcount;
+
+  // 3,5,7,9,11,13,15,17
+  assign sample = (bitcount > 2) & bitcount[0] & !valid & ser_clk;
+  assign data = shifter;
+
+  always @(negedge resetq or posedge clk)
+  begin
+    if (!resetq) begin
+      hh <= 3'b111;
+      bitcount <= 5'b11111;
+      shifter <= 0;
+    end else begin
+      hh <= hhN;
+      bitcount <= bitcountN;
+      shifter <= shifterN;
+    end
+  end
+endmodule
+
+module buart(
+   input wire clk,
+   input wire resetq,
+   input wire [31:0] baud,
+   input wire rx,           // recv wire
+   output wire tx,          // xmit wire
+   input wire rd,           // read strobe
+   input wire wr,           // write strobe
+   output wire valid,       // has recv data 
+   output wire busy,        // is transmitting
+   input wire [7:0] tx_data,
+   output wire [7:0] rx_data // data
+);
+  parameter CLKFREQ = 1000000;
+
+  rxuart #(.CLKFREQ(CLKFREQ)) _rx (
+     .clk(clk),
+     .resetq(resetq),
+     .baud(baud),
+     .uart_rx(rx),
+     .rd(rd),
+     .valid(valid),
+     .data(rx_data));
+  uart #(.CLKFREQ(CLKFREQ)) _tx (
+     .clk(clk),
+     .resetq(resetq),
+     .baud(baud),
+     .uart_busy(busy),
+     .uart_tx(tx),
+     .uart_wr_i(wr),
+     .uart_dat_i(tx_data));
+endmodule

src/basic/verilog/pmodoled2/util.py

@@ -0,0 +1,58 @@
+# Copyright (c) 2015 Wladimir J. van der Laan
+# Distributed under the MIT software license, see the accompanying
+# file COPYING or http://www.opensource.org/licenses/mit-license.php.
+from __future__ import division,print_function
+from PIL import Image
+
+def bin8(value):
+    svalue = bin(value)[2:]
+    svalue = '0'*(8-len(svalue)) + svalue
+    return svalue
+
+def load_bw_image(filename, ofsx=0, ofsy=0):
+    data = [0]*(128*32//8)
+    i = Image.open(filename)
+    for y in range(32):
+        for x in range(128):
+            page = y // 8
+            bit = y % 8
+            ofs = x
+            if i.getpixel((ofsx+x,ofsy+y)):
+                data[page*128+ofs] |= 1<<bit
+    return data
+
+def tile_image(ingrid):
+    '''
+    Convert image to tiled SSD1306 representation
+    '''
+    data = [0]*(128*32//8)
+    for y in range(32):
+        for x in range(128):
+            page = y // 8
+            bit = y % 8
+            ofs = x
+            if ingrid[y][x]:
+                data[page*128+ofs] |= 1<<bit
+    return data
+
+def detect_serial():
+    '''Detect serial port for iCEStick.
+    Based on 'findserial' in swapforth.
+    '''
+    import glob, subprocess
+    return glob.glob('/dev/tty.usbmodem*')
+    # options = []
+    # for dev in glob.glob('/dev/ttyUSB*'):
+    #     info = subprocess.check_output(['/sbin/udevadm', 'info', '-a', '-n', dev])
+    #     info = info.split(b'\n')
+    #     vendor_matches = False
+    #     product_matches = False
+    #     for line in info:
+    #         if b'ATTRS{idVendor}=="0403"' in line:
+    #             vendor_matches = True
+    #         if b'ATTRS{idProduct}=="6010"' in line:
+    #             product_matches = True
+    #     if vendor_matches and product_matches:
+    #         options.append(dev)
+    # return options
+