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ARM64: zynqmp: Enable CLK framework

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ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michal Simek
2016-05-17 13:33:11 +02:00
parent e6a9ed04e7
commit 293271cbc3
6 changed files with 12 additions and 0 deletions
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2
configs/xilinx_zynqmp_ep_defconfig
View File

@@ -40,6 +40,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
View File

@@ -31,6 +31,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
View File

@@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_NAND_ARASAN=y

2
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
View File

@@ -26,6 +26,8 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y

2
configs/xilinx_zynqmp_zcu102_defconfig
View File

@@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y

2
configs/xilinx_zynqmp_zcu102_revB_defconfig
View File

@@ -30,6 +30,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_DM_MMC=y
CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y