Ley Foon Tan f62782fb29 cache: l2x0: Fix write to incorrect shared-override bit ...

The existing code write bit-0 for shared attribute override enable bit.
It should be bit-22 based on cache controller specification [1].

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

2020-04-24 16:40:09 -04:00

1.9 KiB

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