2017-12-21 07:45:38 +08:00
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/*
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2020-01-23 18:57:37 +08:00
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* Copyright (C) 2017-2020 Intel Corporation
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2017-12-21 07:45:38 +08:00
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*
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2018-09-18 15:11:08 +08:00
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* SPDX-License-Identifier: MIT
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2017-12-21 07:45:38 +08:00
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*
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*/
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2020-02-24 05:44:01 +08:00
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#include "shared/source/command_stream/csr_definitions.h"
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#include "shared/source/helpers/preamble_bdw_plus.inl"
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2017-12-21 07:45:38 +08:00
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2019-03-26 18:59:46 +08:00
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namespace NEO {
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2017-12-21 07:45:38 +08:00
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template <>
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uint32_t PreambleHelper<SKLFamily>::getL3Config(const HardwareInfo &hwInfo, bool useSLM) {
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uint32_t l3Config = 0;
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2019-05-08 22:00:24 +08:00
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switch (hwInfo.platform.eProductFamily) {
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2017-12-21 07:45:38 +08:00
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case IGFX_SKYLAKE:
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l3Config = getL3ConfigHelper<IGFX_SKYLAKE>(useSLM);
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break;
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case IGFX_BROXTON:
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l3Config = getL3ConfigHelper<IGFX_BROXTON>(useSLM);
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break;
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default:
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l3Config = getL3ConfigHelper<IGFX_SKYLAKE>(true);
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}
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return l3Config;
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}
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2019-08-06 05:57:15 +08:00
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template <>
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bool PreambleHelper<SKLFamily>::isL3Configurable(const HardwareInfo &hwInfo) {
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return getL3Config(hwInfo, true) != getL3Config(hwInfo, false);
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}
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2017-12-21 07:45:38 +08:00
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template <>
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2019-08-19 21:01:00 +08:00
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void PreambleHelper<SKLFamily>::programPipelineSelect(LinearStream *pCommandStream,
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2019-09-10 22:13:11 +08:00
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const PipelineSelectArgs &pipelineSelectArgs,
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2019-08-19 21:01:00 +08:00
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const HardwareInfo &hwInfo) {
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2017-12-21 07:45:38 +08:00
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typedef typename SKLFamily::PIPELINE_SELECT PIPELINE_SELECT;
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2020-04-09 00:33:03 +08:00
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auto pCmd = pCommandStream->getSpaceForCmd<PIPELINE_SELECT>();
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PIPELINE_SELECT cmd = SKLFamily::cmdInitPipelineSelect;
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2018-01-17 15:37:47 +08:00
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auto mask = pipelineSelectEnablePipelineSelectMaskBits | pipelineSelectMediaSamplerDopClockGateMaskBits;
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2020-04-09 00:33:03 +08:00
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cmd.setMaskBits(mask);
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cmd.setPipelineSelection(PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU);
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cmd.setMediaSamplerDopClockGateEnable(!pipelineSelectArgs.mediaSamplerRequired);
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*pCmd = cmd;
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2017-12-21 07:45:38 +08:00
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}
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template <>
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2020-02-06 23:06:00 +08:00
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void PreambleHelper<SKLFamily>::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo, aub_stream::EngineType engineType) {
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2018-02-23 21:01:12 +08:00
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auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
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2020-04-09 00:33:03 +08:00
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PIPE_CONTROL cmd = SKLFamily::cmdInitPipeControl;
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cmd.setCommandStreamerStallEnable(true);
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2019-05-08 22:00:24 +08:00
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if (hwInfo->workaroundTable.waSendMIFLUSHBeforeVFE) {
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2020-04-09 00:33:03 +08:00
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cmd.setRenderTargetCacheFlushEnable(true);
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cmd.setDepthCacheFlushEnable(true);
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cmd.setDcFlushEnable(true);
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2017-12-21 07:45:38 +08:00
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}
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2020-04-09 00:33:03 +08:00
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*pipeControl = cmd;
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2017-12-21 07:45:38 +08:00
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}
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2018-02-20 15:11:24 +08:00
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template <>
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void PreambleHelper<SKLFamily>::programThreadArbitration(LinearStream *pCommandStream, uint32_t requiredThreadArbitrationPolicy) {
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UNRECOVERABLE_IF(requiredThreadArbitrationPolicy == ThreadArbitrationPolicy::NotPresent);
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auto pipeControl = pCommandStream->getSpaceForCmd<PIPE_CONTROL>();
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2020-04-09 00:33:03 +08:00
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PIPE_CONTROL cmd = SKLFamily::cmdInitPipeControl;
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cmd.setCommandStreamerStallEnable(true);
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*pipeControl = cmd;
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2018-02-20 15:11:24 +08:00
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auto pCmd = pCommandStream->getSpaceForCmd<MI_LOAD_REGISTER_IMM>();
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2020-04-09 00:33:03 +08:00
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MI_LOAD_REGISTER_IMM lriCmd = SKLFamily::cmdInitLoadRegisterImm;
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lriCmd.setRegisterOffset(DebugControlReg2::address);
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lriCmd.setDataDword(DebugControlReg2::getRegData(requiredThreadArbitrationPolicy));
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*pCmd = lriCmd;
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2018-02-20 15:11:24 +08:00
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}
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2018-04-20 19:55:54 +08:00
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template <>
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size_t PreambleHelper<SKLFamily>::getThreadArbitrationCommandsSize() {
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return sizeof(MI_LOAD_REGISTER_IMM) + sizeof(PIPE_CONTROL);
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}
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2018-02-20 15:11:24 +08:00
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template struct PreambleHelper<SKLFamily>;
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2019-03-26 18:59:46 +08:00
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} // namespace NEO
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