2018-04-06 19:48:49 +08:00
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/*
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2019-02-27 18:39:32 +08:00
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* Copyright (C) 2017-2019 Intel Corporation
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2018-04-06 19:48:49 +08:00
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*
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2018-09-18 15:11:08 +08:00
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* SPDX-License-Identifier: MIT
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2018-04-06 19:48:49 +08:00
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*
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*/
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2019-05-16 15:52:28 +08:00
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#include "runtime/aub/aub_helper_bdw_plus.inl"
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2019-02-27 18:39:32 +08:00
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#include "runtime/helpers/flat_batch_buffer_helper_hw.inl"
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2019-05-16 15:52:28 +08:00
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#include "runtime/helpers/hw_helper_bdw_plus.inl"
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2018-04-06 19:48:49 +08:00
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2019-03-26 18:59:46 +08:00
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namespace NEO {
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2018-04-06 19:48:49 +08:00
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typedef CNLFamily Family;
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template <>
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void HwHelperHw<Family>::setCapabilityCoherencyFlag(const HardwareInfo *pHwInfo, bool &coherencyFlag) {
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2019-05-08 22:00:24 +08:00
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if (pHwInfo->platform.usRevId < 0x4) {
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2018-04-06 19:48:49 +08:00
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coherencyFlag = false;
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} else {
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coherencyFlag = true;
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}
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}
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template <>
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bool HwHelperHw<Family>::setupPreemptionRegisters(HardwareInfo *pHwInfo, bool enable) {
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pHwInfo->capabilityTable.whitelistedRegisters.csChicken1_0x2580 = enable;
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return pHwInfo->capabilityTable.whitelistedRegisters.csChicken1_0x2580;
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}
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2018-09-14 20:31:37 +08:00
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template class AubHelperHw<Family>;
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2018-04-06 19:48:49 +08:00
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template class HwHelperHw<Family>;
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2018-09-04 17:25:54 +08:00
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template class FlatBatchBufferHelperHw<Family>;
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2019-03-21 00:08:05 +08:00
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template struct PipeControlHelper<Family>;
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2019-03-26 18:59:46 +08:00
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} // namespace NEO
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