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Do not insert PipeControl WA or DC Flush when not needed

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Change-Id: I71030273708f243324a566232528bce00a0361df
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
This commit is contained in:
Maciej Dziuban
2019-03-20 17:08:05 +01:00
committed by sys_ocldev
parent ee9eb8df83
commit 33c07c875f
24 changed files with 94 additions and 102 deletions
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6
runtime/command_queue/gpgpu_walker.inl
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@ -112,7 +112,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchProfilingCommandsStart(
uint64_t TimeStampAddress = hwTimeStamps.getBaseGraphicsAllocation()->getGpuAddress() +
ptrDiff(&hwTimeStamps.tagForCpuAccess->GlobalStartTS, hwTimeStamps.getBaseGraphicsAllocation()->getUnderlyingBuffer());
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, TimeStampAddress, 0llu);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, TimeStampAddress, 0llu, false);
//MI_STORE_REGISTER_MEM for context local timestamp
TimeStampAddress = hwTimeStamps.getBaseGraphicsAllocation()->getGpuAddress() +
@ -316,7 +316,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsStart(
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWTimeStamp.GlobalStartTS));
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, 0llu);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, 0llu, false);
GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersUserCounterCommands(commandQueue, hwPerfCounter, commandStream, true);
@ -346,7 +346,7 @@ void GpgpuWalkerHelper<GfxFamily>::dispatchPerfCountersCommandsEnd(
//Timestamp: Global End
address = reinterpret_cast<uint64_t>(&(hwPerfCounter.HWTimeStamp.GlobalEndTS));
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, 0llu);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(commandStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, 0llu, false);
auto pReportPerfCount = (MI_REPORT_PERF_COUNT *)commandStream->getSpace(sizeof(MI_REPORT_PERF_COUNT));
*pReportPerfCount = GfxFamily::cmdInitReportPerfCount;

2
runtime/command_queue/gpgpu_walker_base.inl
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@ -177,7 +177,7 @@ void GpgpuWalkerHelper<GfxFamily>::setupTimestampPacket(
if (TimestampPacket::WriteOperationType::AfterWalker == writeOperationType) {
uint64_t address = TimestampPacketHelper::getGpuAddressForDataWrite(*timestampPacketNode, TimestampPacket::DataIndex::ContextEnd);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(cmdStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, address, 0);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(cmdStream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, address, 0, false);
}
}

2
runtime/command_stream/command_stream_receiver_hw.h
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@ -85,7 +85,7 @@ class CommandStreamReceiverHw : public CommandStreamReceiver {
void programVFEState(LinearStream &csr, DispatchFlags &dispatchFlags);
virtual void initPageTableManagerRegisters(LinearStream &csr){};
void addPipeControlWA(LinearStream &commandStream, bool flushDC);
void addPipeControlWA(LinearStream &commandStream);
void addDcFlushToPipeControl(typename GfxFamily::PIPE_CONTROL *pCmd, bool flushDC);
void addClearSLMWorkAround(typename GfxFamily::PIPE_CONTROL *pCmd);
PIPE_CONTROL *addPipeControlCmd(LinearStream &commandStream);

23
runtime/command_stream/command_stream_receiver_hw.inl
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@ -189,13 +189,10 @@ CompletionStamp CommandStreamReceiverHw<GfxFamily>::flushTask(
}
//Some architectures (SKL) requires to have pipe control prior to pipe control with tag write, add it here
addPipeControlWA(commandStreamTask, dispatchFlags.dcFlush);
addPipeControlWA(commandStreamTask);
auto address = getTagAllocation()->getGpuAddress();
auto pCmd = PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&commandStreamTask, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, address, taskCount + 1);
//Some architectures (BDW) requires to have at least one flush bit set
addDcFlushToPipeControl(pCmd, dispatchFlags.dcFlush);
auto pCmd = PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&commandStreamTask, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, address, taskCount + 1, dispatchFlags.dcFlush);
if (DebugManager.flags.FlushAllCaches.get()) {
pCmd->setDcFlushEnable(true);
@ -590,7 +587,7 @@ template <typename GfxFamily>
void CommandStreamReceiverHw<GfxFamily>::addPipeControl(LinearStream &commandStream, bool dcFlush) {
typedef typename GfxFamily::PIPE_CONTROL PIPE_CONTROL;
addPipeControlWA(commandStream, dcFlush);
addPipeControlWA(commandStream);
// Add a PIPE_CONTROL w/ CS_stall
auto pCmd = reinterpret_cast<PIPE_CONTROL *>(commandStream.getSpace(sizeof(PIPE_CONTROL)));
@ -802,4 +799,18 @@ template <typename GfxFamily>
bool CommandStreamReceiverHw<GfxFamily>::detectInitProgrammingFlagsRequired(const DispatchFlags &dispatchFlags) const {
return DebugManager.flags.ForceCsrReprogramming.get();
}
template <typename GfxFamily>
void CommandStreamReceiverHw<GfxFamily>::addPipeControlWA(LinearStream &commandStream) {
}
template <typename GfxFamily>
void CommandStreamReceiverHw<GfxFamily>::addDcFlushToPipeControl(typename GfxFamily::PIPE_CONTROL *pCmd, bool flushDC) {
}
template <typename GfxFamily>
int CommandStreamReceiverHw<GfxFamily>::getRequiredPipeControlSize() const {
const auto pipeControlCount = KernelCommandsHelper<GfxFamily>::isPipeControlWArequired() ? 2u : 1u;
return pipeControlCount * sizeof(typename GfxFamily::PIPE_CONTROL);
}
} // namespace OCLRT

2
runtime/command_stream/experimental_command_buffer.inl
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@ -76,7 +76,7 @@ void ExperimentalCommandBuffer::addTimeStampPipeControl() {
uint64_t timeStampAddress = timestamps->getGpuAddress() + timestampsOffset;
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(currentStream.get(), PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, timeStampAddress, 0llu);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(currentStream.get(), PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, timeStampAddress, 0llu, false);
//moving to next chunk
timestampsOffset += sizeof(uint64_t);

4
runtime/device_queue/device_queue_hw.inl
View File

@ -231,13 +231,13 @@ void DeviceQueueHw<GfxFamily>::addExecutionModelCleanUpSection(Kernel *parentKer
addPipeControlCmdWa();
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&slbCS, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, criticalSectionAddress, ExecutionModelCriticalSection::Free);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&slbCS, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, criticalSectionAddress, ExecutionModelCriticalSection::Free, false);
uint64_t tagAddress = reinterpret_cast<uint64_t>(device->getDefaultEngine().commandStreamReceiver->getTagAddress());
addPipeControlCmdWa();
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&slbCS, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, tagAddress, taskCount);
PipeControlHelper<GfxFamily>::obtainPipeControlAndProgramPostSyncOperation(&slbCS, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, tagAddress, taskCount, false);
addMediaStateClearCmds();

18
runtime/gen10/command_stream_receiver_hw_gen10.cpp
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@ -32,24 +32,6 @@ void CommandStreamReceiverHw<Family>::programComputeMode(LinearStream &stream, D
}
}
template <>
void CommandStreamReceiverHw<Family>::addPipeControlWA(LinearStream &commandStream, bool flushDC) {
auto pCmd = (Family::PIPE_CONTROL *)commandStream.getSpace(sizeof(Family::PIPE_CONTROL));
*pCmd = Family::cmdInitPipeControl;
pCmd->setDcFlushEnable(flushDC);
pCmd->setCommandStreamerStallEnable(true);
}
template <>
int CommandStreamReceiverHw<Family>::getRequiredPipeControlSize() const {
return 2 * sizeof(Family::PIPE_CONTROL);
}
template <>
void CommandStreamReceiverHw<Family>::addDcFlushToPipeControl(Family::PIPE_CONTROL *pCmd, bool flushDC) {
}
template <>
void populateFactoryTable<CommandStreamReceiverHw<Family>>() {
extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE];

1
runtime/gen10/hw_helper_gen10.cpp
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@ -32,4 +32,5 @@ bool HwHelperHw<Family>::setupPreemptionRegisters(HardwareInfo *pHwInfo, bool en
template class AubHelperHw<Family>;
template class HwHelperHw<Family>;
template class FlatBatchBufferHelperHw<Family>;
template struct PipeControlHelper<Family>;
} // namespace OCLRT

2
runtime/gen10/kernel_commands_gen10.cpp
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@ -14,6 +14,4 @@
namespace OCLRT {
template struct KernelCommandsHelper<CNLFamily>;
template <>
bool KernelCommandsHelper<CNLFamily>::isPipeControlWArequired() { return true; }
} // namespace OCLRT

9
runtime/gen8/command_stream_receiver_hw_gen8.cpp
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@ -24,15 +24,6 @@ template <>
void CommandStreamReceiverHw<Family>::programComputeMode(LinearStream &stream, DispatchFlags &dispatchFlags) {
}
template <>
void CommandStreamReceiverHw<Family>::addPipeControlWA(LinearStream &commandStream, bool flushDC) {
}
template <>
int CommandStreamReceiverHw<Family>::getRequiredPipeControlSize() const {
return 1 * sizeof(Family::PIPE_CONTROL);
}
template <>
void CommandStreamReceiverHw<Family>::addDcFlushToPipeControl(Family::PIPE_CONTROL *pCmd, bool flushDC) {
pCmd->setDcFlushEnable(flushDC);

1
runtime/gen8/hw_helper_gen8.cpp
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@ -31,4 +31,5 @@ void HwHelperHw<Family>::setupHardwareCapabilities(HardwareCapabilities *caps, c
template class AubHelperHw<Family>;
template class HwHelperHw<Family>;
template class FlatBatchBufferHelperHw<Family>;
template struct PipeControlHelper<Family>;
} // namespace OCLRT

3
runtime/gen8/kernel_commands_gen8.cpp
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@ -16,9 +16,6 @@
namespace OCLRT {
template <>
bool KernelCommandsHelper<BDWFamily>::isPipeControlWArequired() { return false; }
static uint32_t slmSizeId[] = {0, 1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16};
template <>

13
runtime/gen9/command_stream_receiver_hw_gen9.cpp
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@ -25,23 +25,12 @@ void CommandStreamReceiverHw<Family>::programComputeMode(LinearStream &stream, D
}
template <>
void CommandStreamReceiverHw<Family>::addPipeControlWA(LinearStream &commandStream, bool flushDC) {
void CommandStreamReceiverHw<Family>::addPipeControlWA(LinearStream &commandStream) {
auto pCmd = (Family::PIPE_CONTROL *)commandStream.getSpace(sizeof(Family::PIPE_CONTROL));
*pCmd = Family::cmdInitPipeControl;
pCmd->setDcFlushEnable(flushDC);
pCmd->setCommandStreamerStallEnable(true);
}
template <>
int CommandStreamReceiverHw<Family>::getRequiredPipeControlSize() const {
return 2 * sizeof(Family::PIPE_CONTROL);
}
template <>
void CommandStreamReceiverHw<Family>::addDcFlushToPipeControl(Family::PIPE_CONTROL *pCmd, bool flushDC) {
}
template <>
void populateFactoryTable<CommandStreamReceiverHw<Family>>() {
extern CommandStreamReceiverCreateFunc commandStreamReceiverFactory[2 * IGFX_MAX_CORE];

1
runtime/gen9/hw_helper_gen9.cpp
View File

@ -31,4 +31,5 @@ SipKernelType HwHelperHw<Family>::getSipKernelType(bool debuggingActive) {
template class AubHelperHw<Family>;
template class HwHelperHw<Family>;
template class FlatBatchBufferHelperHw<Family>;
template struct PipeControlHelper<Family>;
} // namespace OCLRT

14
runtime/helpers/hw_helper.h
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@ -181,18 +181,8 @@ struct PipeControlHelper {
static PIPE_CONTROL *obtainPipeControlAndProgramPostSyncOperation(LinearStream *commandStream,
POST_SYNC_OPERATION operation,
uint64_t gpuAddress,
uint64_t immediateData) {
auto pipeControl = reinterpret_cast<PIPE_CONTROL *>(commandStream->getSpace(sizeof(PIPE_CONTROL)));
*pipeControl = GfxFamily::cmdInitPipeControl;
pipeControl->setCommandStreamerStallEnable(true);
pipeControl->setPostSyncOperation(operation);
pipeControl->setAddress(static_cast<uint32_t>(gpuAddress & 0x0000FFFFFFFFULL));
pipeControl->setAddressHigh(static_cast<uint32_t>(gpuAddress >> 32));
if (operation == POST_SYNC_OPERATION::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA) {
pipeControl->setImmediateData(immediateData);
}
return pipeControl;
}
uint64_t immediateData,
bool dcFlush);
};
union SURFACE_STATE_BUFFER_LENGTH {

19
runtime/helpers/hw_helper_common.inl
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@ -185,4 +185,23 @@ bool HwHelperHw<Family>::getEnableLocalMemory(const HardwareInfo &hwInfo) const
return OSInterface::osEnableLocalMemory && isLocalMemoryEnabled(hwInfo);
}
template <typename Family>
typename Family::PIPE_CONTROL *PipeControlHelper<Family>::obtainPipeControlAndProgramPostSyncOperation(LinearStream *commandStream,
POST_SYNC_OPERATION operation,
uint64_t gpuAddress,
uint64_t immediateData,
bool dcFlush) {
auto pipeControl = reinterpret_cast<PIPE_CONTROL *>(commandStream->getSpace(sizeof(PIPE_CONTROL)));
*pipeControl = Family::cmdInitPipeControl;
pipeControl->setCommandStreamerStallEnable(true);
pipeControl->setPostSyncOperation(operation);
pipeControl->setAddress(static_cast<uint32_t>(gpuAddress & 0x0000FFFFFFFFULL));
pipeControl->setAddressHigh(static_cast<uint32_t>(gpuAddress >> 32));
pipeControl->setDcFlushEnable(dcFlush);
if (operation == POST_SYNC_OPERATION::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA) {
pipeControl->setImmediateData(immediateData);
}
return pipeControl;
}
} // namespace OCLRT

3
runtime/helpers/kernel_commands.inl
View File

@ -22,6 +22,9 @@
namespace OCLRT {
template <typename GfxFamily>
bool KernelCommandsHelper<GfxFamily>::isPipeControlWArequired() { return false; }
template <typename GfxFamily>
uint32_t KernelCommandsHelper<GfxFamily>::computeSlmValues(uint32_t valueIn) {
auto value = std::max(valueIn, 1024u);

12
unit_tests/command_queue/enqueue_map_image_tests.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2017-2018 Intel Corporation
* Copyright (C) 2017-2019 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -1001,17 +1001,17 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueMapImageTypeTest, blockingEnqueueRequiresPCWi
auto *cmd = (PIPE_CONTROL *)*itorCmd;
EXPECT_NE(cmdList.end(), itorCmd);
if (::renderCoreFamily != IGFX_GEN8_CORE) {
// SKL+: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());
if (::renderCoreFamily == IGFX_GEN9_CORE) {
// SKL: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_FALSE(cmd->getDcFlushEnable());
// Move to next PPC
auto itorCmdP = ++((GenCmdList::iterator)itorCmd);
EXPECT_NE(cmdList.end(), itorCmdP);
auto itorCmd2 = find<PIPE_CONTROL *>(itorCmdP, cmdList.end());
cmd = (PIPE_CONTROL *)*itorCmd2;
EXPECT_FALSE(cmd->getDcFlushEnable());
EXPECT_TRUE(cmd->getDcFlushEnable());
} else {
// BDW: single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
// single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());
}
}

10
unit_tests/command_queue/enqueue_read_buffer_rect_tests.cpp
View File

@ -297,17 +297,17 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueReadBufferRectTest, blockingRequiresPipeContr
auto *cmd = (PIPE_CONTROL *)*itorCmd;
EXPECT_NE(cmdList.end(), itorCmd);
if (::renderCoreFamily != IGFX_GEN8_CORE) {
// SKL+: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());
if (::renderCoreFamily == IGFX_GEN9_CORE) {
// SKL: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_FALSE(cmd->getDcFlushEnable());
// Move to next PPC
auto itorCmdP = ++((GenCmdList::iterator)itorCmd);
EXPECT_NE(cmdList.end(), itorCmdP);
auto itorCmd2 = find<PIPE_CONTROL *>(itorCmdP, cmdList.end());
cmd = (PIPE_CONTROL *)*itorCmd2;
EXPECT_FALSE(cmd->getDcFlushEnable());
EXPECT_TRUE(cmd->getDcFlushEnable());
} else {
// BDW: single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
// single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());
}
}

8
unit_tests/command_queue/enqueue_read_buffer_tests.cpp
View File

@ -263,15 +263,15 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueReadBufferTypeTest, blockingRequiresPipeContr
auto *cmd = (PIPE_CONTROL *)*itorCmd;
EXPECT_NE(cmdList.end(), itorCmd);
if (::renderCoreFamily != IGFX_GEN8_CORE) {
// SKL+: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());
if (::renderCoreFamily == IGFX_GEN9_CORE) {
// SKL: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_FALSE(cmd->getDcFlushEnable());
// Move to next PPC
auto itorCmdP = ++((GenCmdList::iterator)itorCmd);
EXPECT_NE(cmdList.end(), itorCmdP);
auto itorCmd2 = find<PIPE_CONTROL *>(itorCmdP, cmdList.end());
cmd = (PIPE_CONTROL *)*itorCmd2;
EXPECT_FALSE(cmd->getDcFlushEnable());
EXPECT_TRUE(cmd->getDcFlushEnable());
} else {
// BDW: single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());

8
unit_tests/command_queue/enqueue_read_image_tests.cpp
View File

@ -204,15 +204,15 @@ HWCMDTEST_F(IGFX_GEN8_CORE, EnqueueReadImageTest, blockingEnqueueRequiresPCWithD
auto *cmd = (PIPE_CONTROL *)*itorCmd;
EXPECT_NE(cmdList.end(), itorCmd);
if (::renderCoreFamily != IGFX_GEN8_CORE) {
// SKL+: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());
if (::renderCoreFamily == IGFX_GEN9_CORE) {
// SKL: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_FALSE(cmd->getDcFlushEnable());
// Move to next PPC
auto itorCmdP = ++((GenCmdList::iterator)itorCmd);
EXPECT_NE(cmdList.end(), itorCmdP);
auto itorCmd2 = find<PIPE_CONTROL *>(itorCmdP, cmdList.end());
cmd = (PIPE_CONTROL *)*itorCmd2;
EXPECT_FALSE(cmd->getDcFlushEnable());
EXPECT_TRUE(cmd->getDcFlushEnable());
} else {
// BDW: single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
EXPECT_TRUE(cmd->getDcFlushEnable());

16
unit_tests/command_stream/command_stream_receiver_flush_task_1_tests.cpp
View File

@ -919,10 +919,10 @@ HWTEST_F(CommandStreamReceiverFlushTaskTests, FlushTaskBlockingHasPipeControlWit
auto itorPC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
EXPECT_NE(cmdList.end(), itorPC);
if (::renderCoreFamily != IGFX_GEN8_CORE) {
if (::renderCoreFamily == IGFX_GEN9_CORE) {
// Verify that the dcFlushEnabled bit is set in PC
auto pCmdWA = reinterpret_cast<PIPE_CONTROL *>(*itorPC);
EXPECT_EQ(true, pCmdWA->getDcFlushEnable());
EXPECT_FALSE(pCmdWA->getDcFlushEnable());
if (pipeControlCount > 1) {
// Search taskCS for PC to analyze
@ -932,12 +932,11 @@ HWTEST_F(CommandStreamReceiverFlushTaskTests, FlushTaskBlockingHasPipeControlWit
// Verify that the dcFlushEnabled bit is not set in PC
auto pCmd = reinterpret_cast<PIPE_CONTROL *>(pipeControlTask);
EXPECT_EQ(false, pCmd->getDcFlushEnable());
EXPECT_TRUE(pCmd->getDcFlushEnable());
}
} else {
// Verify that the dcFlushEnabled bit is not set in PC
auto pCmd = reinterpret_cast<PIPE_CONTROL *>(*itorPC);
EXPECT_EQ(true, pCmd->getDcFlushEnable());
EXPECT_TRUE(pCmd->getDcFlushEnable());
}
}
@ -973,10 +972,15 @@ HWTEST_F(CommandStreamReceiverFlushTaskTests, GivenBlockedKernelRequiringDCFlush
auto itorPC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
EXPECT_NE(cmdList.end(), itorPC);
if (::renderCoreFamily == IGFX_GEN9_CORE) {
itorPC++;
itorPC = find<PIPE_CONTROL *>(itorPC, cmdList.end());
EXPECT_NE(cmdList.end(), itorPC);
}
// Verify that the dcFlushEnabled bit is set in PC
auto pCmdWA = reinterpret_cast<PIPE_CONTROL *>(*itorPC);
EXPECT_EQ(true, pCmdWA->getDcFlushEnable());
EXPECT_TRUE(pCmdWA->getDcFlushEnable());
buffer->release();
}

15
unit_tests/command_stream/command_stream_receiver_flush_task_2_tests.cpp
View File

@ -59,6 +59,11 @@ HWTEST_F(CommandStreamReceiverFlushTaskTests, GivenBlockedKernelNotRequiringDCFl
auto itorPC = find<PIPE_CONTROL *>(cmdList.begin(), cmdList.end());
EXPECT_NE(cmdList.end(), itorPC);
if (::renderCoreFamily == IGFX_GEN9_CORE) {
itorPC++;
itorPC = find<PIPE_CONTROL *>(itorPC, cmdList.end());
EXPECT_NE(cmdList.end(), itorPC);
}
// Verify that the dcFlushEnabled bit is set in PC
auto pCmdWA = reinterpret_cast<PIPE_CONTROL *>(*itorPC);
@ -331,16 +336,16 @@ HWCMDTEST_F(IGFX_GEN8_CORE, CommandStreamReceiverFlushTaskTests,
auto cmdPC = genCmdCast<PIPE_CONTROL *>(*itorCmd);
ASSERT_NE(nullptr, cmdPC);
if (::renderCoreFamily != IGFX_GEN8_CORE) {
// SKL+: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_TRUE(cmdPC->getDcFlushEnable());
if (::renderCoreFamily == IGFX_GEN9_CORE) {
// SKL: two PIPE_CONTROLs following GPGPU_WALKER: first has DcFlush and second has Write HwTag
EXPECT_FALSE(cmdPC->getDcFlushEnable());
auto itorCmdP = ++((GenCmdList::iterator)itorCmd);
EXPECT_NE(cmdList.end(), itorCmdP);
auto itorCmd2 = find<PIPE_CONTROL *>(itorCmdP, cmdList.end());
cmdPC = (PIPE_CONTROL *)*itorCmd2;
EXPECT_FALSE(cmdPC->getDcFlushEnable());
EXPECT_TRUE(cmdPC->getDcFlushEnable());
} else {
// BDW: single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
// single PIPE_CONTROL following GPGPU_WALKER has DcFlush and Write HwTag
EXPECT_TRUE(cmdPC->getDcFlushEnable());
}

4
unit_tests/helpers/hw_helper_tests.cpp
View File

@ -201,7 +201,7 @@ HWTEST_F(PipeControlHelperTests, givenPostSyncWriteTimestampModeWhenHelperIsUsed
expectedPipeControl.setAddress(static_cast<uint32_t>(address & 0x0000FFFFFFFFULL));
expectedPipeControl.setAddressHigh(static_cast<uint32_t>(address >> 32));
auto pipeControl = PipeControlHelper<FamilyType>::obtainPipeControlAndProgramPostSyncOperation(&stream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, immediateData);
auto pipeControl = PipeControlHelper<FamilyType>::obtainPipeControlAndProgramPostSyncOperation(&stream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_TIMESTAMP, address, immediateData, false);
EXPECT_EQ(sizeof(PIPE_CONTROL), stream.getUsed());
EXPECT_EQ(pipeControl, stream.getCpuBase());
@ -223,7 +223,7 @@ HWTEST_F(PipeControlHelperTests, givenPostSyncWriteImmediateDataModeWhenHelperIs
expectedPipeControl.setAddressHigh(static_cast<uint32_t>(address >> 32));
expectedPipeControl.setImmediateData(immediateData);
auto pipeControl = PipeControlHelper<FamilyType>::obtainPipeControlAndProgramPostSyncOperation(&stream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, address, immediateData);
auto pipeControl = PipeControlHelper<FamilyType>::obtainPipeControlAndProgramPostSyncOperation(&stream, PIPE_CONTROL::POST_SYNC_OPERATION_WRITE_IMMEDIATE_DATA, address, immediateData, false);
EXPECT_EQ(sizeof(PIPE_CONTROL), stream.getUsed());
EXPECT_EQ(pipeControl, stream.getCpuBase());