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build: Updated the UAPI headers to v2.0-rc27
Signed-off-by: Pratik Bari <pratik.bari@intel.com>
This commit is contained in:

committed by
Compute-Runtime-Automation

parent
c9a3b9afd4
commit
90ef587aa8
@ -1,2 +1,2 @@
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git_revision: v2.0-rc24
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git_revision: v2.0-rc27
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git_url: https://github.com/intel-gpu/drm-uapi-helper
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@ -641,12 +641,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
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#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
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#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
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/*
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* BUSY_STATS is deprecated on platforms with GuC based submission and will not
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* be available at all on newer platforms. It has accuracy issues due to the
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* conversions from tick counts to wall time.
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* BUSY_TICKS_STATS should be used instead.
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*/
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#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
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/*
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* Indicates the 2k user priority levels are statically mapped into 3 buckets as
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@ -2355,7 +2350,7 @@ struct i915_context_param_engines {
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#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
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#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
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#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
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struct i915_engine_class_instance engines[0];
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struct i915_engine_class_instance engines[];
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} __attribute__((packed));
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#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
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@ -134,13 +134,14 @@ struct prelim_i915_user_extension {
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* Note that I915_PMU_SAMPLE_BITS is 4 so a max of 16 events can be sampled for
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* an engine. For the PRELIM version start at half of that value.
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*/
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#define PRELIM_I915_SAMPLE_BUSY_TICKS 8
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#define PRELIM_I915_SAMPLE_BUSY_TICKS 8
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#define PRELIM_I915_SAMPLE_TOTAL_TICKS 9
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#define PRELIM_I915_PMU_ENGINE_BUSY_TICKS(class, instance) \
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__I915_PMU_ENGINE(class, instance, PRELIM_I915_SAMPLE_BUSY_TICKS)
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#define PRELIM_I915_SCHEDULER_CAP_ENGINE_BUSY_TICKS_STATS (1ul << 16)
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#define PRELIM_I915_PMU_ENGINE_TOTAL_TICKS(class, instance) \
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__I915_PMU_ENGINE(class, instance, PRELIM_I915_SAMPLE_TOTAL_TICKS)
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/*
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* HW error counters.
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*/
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@ -211,6 +212,16 @@ struct prelim_i915_user_extension {
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_NONFATAL_CD0_MDFI (125)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_NONFATAL_MDFI_EAST (126)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_NONFATAL_MDFI_SOUTH (127)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_IOSF_PCIAER (128)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_IOSF_PCIEER (129)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_UR_RESPONSE (130)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_SERR_SPI (131)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_HBM_PUNIT_MCA (132)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_PCIAER (133)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_PCIEER (134)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_UR (135)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_SERR_SRCS (136)
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#define PRELIM_I915_PVC_PMU_SOC_ERROR_FATAL_HBM_MCA (137)
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#define PRELIM_I915_PMU_HW_ERROR(gt, id) \
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((__PRELIM_I915_PMU_HW_ERROR_EVENT_ID_OFFSET + (id)) | \
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@ -966,7 +977,7 @@ struct prelim_drm_i915_debug_event_vm_bind {
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__u64 va_length;
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__u32 num_uuids;
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__u32 flags;
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__u64 uuids[0];
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__u64 uuids[];
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} __attribute__((packed));
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struct prelim_drm_i915_debug_event_eu_attention {
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@ -993,7 +1004,7 @@ struct prelim_drm_i915_debug_event_eu_attention {
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* 'pair' instead of individual EUs.
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*/
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__u8 bitmask[0];
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__u8 bitmask[];
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} __attribute__((packed));
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struct prelim_drm_i915_debug_event_page_fault {
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@ -1021,7 +1032,7 @@ struct prelim_drm_i915_debug_event_page_fault {
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* The order of the bitmask array is before, after, resolved.
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*/
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__u8 bitmask[0];
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__u8 bitmask[];
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} __attribute__((packed));
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struct prelim_drm_i915_debug_read_uuid {
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@ -1050,7 +1061,7 @@ struct prelim_drm_i915_debug_event_engines {
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__u64 client_handle;
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__u64 ctx_handle;
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__u64 num_engines;
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struct prelim_drm_i915_debug_engine_info engines[0];
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struct prelim_drm_i915_debug_engine_info engines[];
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} __attribute__((packed));
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struct prelim_drm_i915_debug_vm_open {
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