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refactor: group same instantiations of level zero helper 

Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
This commit is contained in:
Zbigniew Zdanowicz 2024-04-11 09:44:15 +00:00 committed by Compute-Runtime-Automation
parent b24ad6a1b0
commit 93ddf34c11
8 changed files with 59 additions and 22 deletions
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16
level_zero/core/source/gfx_core_helpers/CMakeLists.txt
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@ -1,5 +1,5 @@
#
# Copyright (C) 2023 Intel Corporation
# Copyright (C) 2023-2024 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
@ -40,6 +40,13 @@ if(SUPPORT_GEN12LP OR SUPPORT_XE_HP_CORE OR SUPPORT_XE_HPG_CORE)
)
endif()
if(SUPPORT_XE_HPC_CORE OR SUPPORT_XE_HPG_CORE)
target_sources(${L0_STATIC_LIB_NAME}
PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl
)
endif()
if(SUPPORT_PVC_AND_LATER)
target_sources(${L0_STATIC_LIB_NAME}
PRIVATE
@ -53,3 +60,10 @@ if(SUPPORT_GEN9 OR SUPPORT_GEN11 OR SUPPORT_GEN12LP OR SUPPORT_XE_HPG_CORE OR SU
${CMAKE_CURRENT_SOURCE_DIR}/l0_gfx_core_helper_skl_to_pvc.inl
)
endif()
if(SUPPORT_XE_HP_CORE OR SUPPORT_XE_HPG_CORE OR SUPPORT_XE2_HPG_CORE)
target_sources(${L0_STATIC_LIB_NAME}
PRIVATE
${CMAKE_CURRENT_SOURCE_DIR}/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl
)
endif()

5
level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl
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@ -40,11 +40,6 @@ bool L0GfxCoreHelperHw<Family>::multiTileCapablePlatform() const {
return false;
}
template <typename Family>
zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
return ZET_DEBUG_REGSET_TYPE_INVALID_INTEL_GPU;
}
template <typename Family>
uint32_t L0GfxCoreHelperHw<Family>::getCmdListWaitOnMemoryDataSize() const {
if constexpr (Family::isQwordInOrderCounter) {

5
level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_tgllp.inl
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@ -74,4 +74,9 @@ ze_mutable_command_exp_flags_t L0GfxCoreHelperHw<Family>::getPlatformCmdListUpda
return 0;
}
template <typename Family>
zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
return ZET_DEBUG_REGSET_TYPE_INVALID_INTEL_GPU;
}
} // namespace L0

17
level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (C) 2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper.h"
namespace L0 {
template <typename Family>
zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
return ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU;
}
} // namespace L0

17
level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl Normal file
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@ -0,0 +1,17 @@
/*
* Copyright (C) 2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper.h"
namespace L0 {
template <typename Family>
ze_rtas_format_exp_t L0GfxCoreHelperHw<Family>::getSupportedRTASFormat() const {
return static_cast<ze_rtas_format_exp_t>(RTASDeviceFormatInternal::version1);
}
} // namespace L0

5
level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl
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@ -67,11 +67,6 @@ NEO::HeapAddressModel L0GfxCoreHelperHw<Family>::getPlatformHeapAddressModel(con
return NEO::HeapAddressModel::privateHeaps;
}
template <typename Family>
ze_rtas_format_exp_t L0GfxCoreHelperHw<Family>::getSupportedRTASFormat() const {
return static_cast<ze_rtas_format_exp_t>(RTASDeviceFormatInternal::version1);
}
template <typename Family>
bool L0GfxCoreHelperHw<Family>::platformSupportsPrimaryBatchBufferCmdList() const {
return true;

7
level_zero/core/source/xe_hpc_core/l0_gfx_core_helper_xe_hpc_core.cpp
View File

@ -10,6 +10,8 @@
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_pvc_and_later.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_pvc.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl"
#include "level_zero/core/source/helpers/l0_populate_factory.h"
@ -35,11 +37,6 @@ bool L0GfxCoreHelperHw<Family>::platformSupportsStateBaseAddressTracking(const N
return true;
}
template <>
zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
return ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU;
}
template class L0GfxCoreHelperHw<Family>;
} // namespace L0

9
level_zero/core/source/xe_hpg_core/l0_gfx_core_helper_xe_hpg_core.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2021-2023 Intel Corporation
* Copyright (C) 2021-2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
@ -10,6 +10,8 @@
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_base.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_skl_to_pvc.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_tgllp_to_dg2.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_and_xe_hpc.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xe_hpg_to_xe2_hpg.inl"
#include "level_zero/core/source/gfx_core_helpers/l0_gfx_core_helper_xehp_and_later.inl"
#include "level_zero/core/source/helpers/l0_populate_factory.h"
@ -18,11 +20,6 @@ namespace L0 {
using Family = NEO::XeHpgCoreFamily;
static auto gfxCore = IGFX_XE_HPG_CORE;
template <>
zet_debug_regset_type_intel_gpu_t L0GfxCoreHelperHw<Family>::getRegsetTypeForLargeGrfDetection() const {
return ZET_DEBUG_REGSET_TYPE_CR_INTEL_GPU;
}
#include "level_zero/core/source/helpers/l0_gfx_core_helper_factory_init.inl"
template class L0GfxCoreHelperHw<Family>;