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Change default GPR offsets

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Related-To: NEO-7458

Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
This commit is contained in:
Dunajski, Bartosz
2022-11-22 16:25:19 +00:00
committed by Compute-Runtime-Automation
parent 51f8fe0131
commit acb8186744
4 changed files with 24 additions and 24 deletions
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12
level_zero/core/test/unit_tests/fixtures/cmdlist_fixture.inl
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@ -36,14 +36,14 @@ void validateTimestampRegisters(GenCmdList &cmdList,
ASSERT_NE(cmdList.end(), itor);
auto cmdLoadReg = genCmdCast<MI_LOAD_REGISTER_REG *>(*itor);
EXPECT_EQ(firstLoadRegisterRegSrcAddress, cmdLoadReg->getSourceRegisterAddress());
EXPECT_EQ(CS_GPR_R0, cmdLoadReg->getDestinationRegisterAddress());
EXPECT_EQ(CS_GPR_R13, cmdLoadReg->getDestinationRegisterAddress());
}
itor++;
{
ASSERT_NE(cmdList.end(), itor);
auto cmdLoadImm = genCmdCast<MI_LOAD_REGISTER_IMM *>(*itor);
EXPECT_EQ(CS_GPR_R1, cmdLoadImm->getRegisterOffset());
EXPECT_EQ(CS_GPR_R14, cmdLoadImm->getRegisterOffset());
EXPECT_EQ(mask, cmdLoadImm->getDataDword());
}
@ -58,7 +58,7 @@ void validateTimestampRegisters(GenCmdList &cmdList,
{
ASSERT_NE(cmdList.end(), itor);
auto cmdMem = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
EXPECT_EQ(CS_GPR_R2, cmdMem->getRegisterAddress());
EXPECT_EQ(CS_GPR_R15, cmdMem->getRegisterAddress());
EXPECT_EQ(firstStoreRegMemAddress, cmdMem->getMemoryAddress());
if (workloadPartition) {
EXPECT_TRUE(UnitTestHelper<FamilyType>::getWorkloadPartitionForStoreRegisterMemCmd(*cmdMem));
@ -72,14 +72,14 @@ void validateTimestampRegisters(GenCmdList &cmdList,
ASSERT_NE(cmdList.end(), itor);
auto cmdLoadReg = genCmdCast<MI_LOAD_REGISTER_REG *>(*itor);
EXPECT_EQ(secondLoadRegisterRegSrcAddress, cmdLoadReg->getSourceRegisterAddress());
EXPECT_EQ(CS_GPR_R0, cmdLoadReg->getDestinationRegisterAddress());
EXPECT_EQ(CS_GPR_R13, cmdLoadReg->getDestinationRegisterAddress());
}
itor++;
{
ASSERT_NE(cmdList.end(), itor);
auto cmdLoadImm = genCmdCast<MI_LOAD_REGISTER_IMM *>(*itor);
EXPECT_EQ(CS_GPR_R1, cmdLoadImm->getRegisterOffset());
EXPECT_EQ(CS_GPR_R14, cmdLoadImm->getRegisterOffset());
EXPECT_EQ(mask, cmdLoadImm->getDataDword());
}
@ -94,7 +94,7 @@ void validateTimestampRegisters(GenCmdList &cmdList,
{
ASSERT_NE(cmdList.end(), itor);
auto cmdMem = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
EXPECT_EQ(CS_GPR_R2, cmdMem->getRegisterAddress());
EXPECT_EQ(CS_GPR_R15, cmdMem->getRegisterAddress());
EXPECT_EQ(secondStoreRegMemAddress, cmdMem->getMemoryAddress());
if (workloadPartition) {
EXPECT_TRUE(UnitTestHelper<FamilyType>::getWorkloadPartitionForStoreRegisterMemCmd(*cmdMem));

12
shared/source/command_container/command_encoder.inl
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@ -147,13 +147,13 @@ void EncodeMathMMIO<Family>::encodeGreaterThanPredicate(CommandContainer &contai
template <typename Family>
void EncodeMathMMIO<Family>::encodeBitwiseAndVal(CommandContainer &container, uint32_t regOffset, uint32_t immVal, uint64_t dstAddress,
bool workloadPartition) {
EncodeSetMMIO<Family>::encodeREG(container, CS_GPR_R0, regOffset);
EncodeSetMMIO<Family>::encodeIMM(container, CS_GPR_R1, immVal, true);
EncodeMath<Family>::bitwiseAnd(container, AluRegisters::R_0,
AluRegisters::R_1,
AluRegisters::R_2);
EncodeSetMMIO<Family>::encodeREG(container, CS_GPR_R13, regOffset);
EncodeSetMMIO<Family>::encodeIMM(container, CS_GPR_R14, immVal, true);
EncodeMath<Family>::bitwiseAnd(container, AluRegisters::R_13,
AluRegisters::R_14,
AluRegisters::R_15);
EncodeStoreMMIO<Family>::encode(*container.getCommandStream(),
CS_GPR_R2, dstAddress, workloadPartition);
CS_GPR_R15, dstAddress, workloadPartition);
}
/*

12
shared/test/unit_test/encoders/command_encoder_tests_xehp_and_later.cpp
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@ -171,17 +171,17 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterCommandEncoderTest, givenOffsetAndValue
auto itor = find<MI_LOAD_REGISTER_REG *>(commands.begin(), commands.end());
// load regOffset to R0
// load regOffset to R13
ASSERT_NE(commands.end(), itor);
auto cmdLoadReg = genCmdCast<MI_LOAD_REGISTER_REG *>(*itor);
EXPECT_EQ(regOffset, cmdLoadReg->getSourceRegisterAddress());
EXPECT_EQ(CS_GPR_R0, cmdLoadReg->getDestinationRegisterAddress());
EXPECT_EQ(CS_GPR_R13, cmdLoadReg->getDestinationRegisterAddress());
// load immVal to R1
// load immVal to R14
itor++;
ASSERT_NE(commands.end(), itor);
auto cmdLoadImm = genCmdCast<MI_LOAD_REGISTER_IMM *>(*itor);
EXPECT_EQ(CS_GPR_R1, cmdLoadImm->getRegisterOffset());
EXPECT_EQ(CS_GPR_R14, cmdLoadImm->getRegisterOffset());
EXPECT_EQ(immVal, cmdLoadImm->getDataDword());
// encodeAluAnd should have its own unit tests, so we only check
@ -191,11 +191,11 @@ HWCMDTEST_F(IGFX_XE_HP_CORE, XeHPAndLaterCommandEncoderTest, givenOffsetAndValue
auto cmdMath = genCmdCast<MI_MATH *>(*itor);
EXPECT_EQ(3u, cmdMath->DW0.BitField.DwordLength);
// store R2 to address
// store R15 to address
itor++;
ASSERT_NE(commands.end(), itor);
auto cmdMem = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
EXPECT_EQ(CS_GPR_R2, cmdMem->getRegisterAddress());
EXPECT_EQ(CS_GPR_R15, cmdMem->getRegisterAddress());
EXPECT_EQ(dstAddress, cmdMem->getMemoryAddress());
EXPECT_TRUE(cmdMem->getWorkloadPartitionIdOffsetEnable());
}

12
shared/test/unit_test/encoders/test_encode_math.cpp
View File

@ -188,17 +188,17 @@ HWTEST_F(CommandEncoderMathTest, givenOffsetAndValueWhenEncodeBitwiseAndValIsCal
auto itor = find<MI_LOAD_REGISTER_REG *>(commands.begin(), commands.end());
// load regOffset to R0
// load regOffset to R13
EXPECT_NE(commands.end(), itor);
auto cmdLoadReg = genCmdCast<MI_LOAD_REGISTER_REG *>(*itor);
EXPECT_EQ(cmdLoadReg->getSourceRegisterAddress(), regOffset);
EXPECT_EQ(cmdLoadReg->getDestinationRegisterAddress(), CS_GPR_R0);
EXPECT_EQ(cmdLoadReg->getDestinationRegisterAddress(), CS_GPR_R13);
// load immVal to R1
// load immVal to R14
itor++;
EXPECT_NE(commands.end(), itor);
auto cmdLoadImm = genCmdCast<MI_LOAD_REGISTER_IMM *>(*itor);
EXPECT_EQ(cmdLoadImm->getRegisterOffset(), CS_GPR_R1);
EXPECT_EQ(cmdLoadImm->getRegisterOffset(), CS_GPR_R14);
EXPECT_EQ(cmdLoadImm->getDataDword(), immVal);
// encodeAluAnd should have its own unit tests, so we only check
@ -208,11 +208,11 @@ HWTEST_F(CommandEncoderMathTest, givenOffsetAndValueWhenEncodeBitwiseAndValIsCal
auto cmdMath = genCmdCast<MI_MATH *>(*itor);
EXPECT_EQ(cmdMath->DW0.BitField.DwordLength, 3u);
// store R2 to address
// store R15 to address
itor++;
EXPECT_NE(commands.end(), itor);
auto cmdMem = genCmdCast<MI_STORE_REGISTER_MEM *>(*itor);
EXPECT_EQ(cmdMem->getRegisterAddress(), CS_GPR_R2);
EXPECT_EQ(cmdMem->getRegisterAddress(), CS_GPR_R15);
EXPECT_EQ(cmdMem->getMemoryAddress(), dstAddress);
}