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test: correct expectations in level zero tests if heapless enabled 4/4 

Related-To: NEO-10641
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
This commit is contained in:
Kamil Kopryk 2024-09-06 06:50:15 +00:00 committed by Compute-Runtime-Automation
parent 5159e57db9
commit b73d956285
1 changed files with 14 additions and 4 deletions
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18
level_zero/core/test/unit_tests/sources/cmdlist/test_in_order_cmdlist.cpp
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@ -1520,8 +1520,14 @@ HWTEST2_F(InOrderCmdListTests, givenImmediateCmdListWhenDispatchingWithRegularEv
EXPECT_EQ(Event::CounterBasedMode::implicitlyEnabled, events[0]->counterBasedMode);
}
auto hostAddress = static_cast<uint64_t *>(immCmdList->inOrderExecInfo->getDeviceCounterAllocation()->getUnderlyingBuffer());
*hostAddress = immCmdList->inOrderExecInfo->getCounterValue();
if (immCmdList->inOrderExecInfo->isHostStorageDuplicated()) {
auto hostAddress = immCmdList->inOrderExecInfo->getBaseHostAddress();
*hostAddress = immCmdList->inOrderExecInfo->getCounterValue();
} else {
auto hostAddress = static_cast<uint64_t *>(immCmdList->inOrderExecInfo->getDeviceCounterAllocation()->getUnderlyingBuffer());
*hostAddress = immCmdList->inOrderExecInfo->getCounterValue();
}
immCmdList->copyThroughLockedPtrEnabled = true;
events[0]->makeCounterBasedInitiallyDisabled();
@ -5141,8 +5147,12 @@ HWTEST2_F(MultiTileInOrderCmdListTests, givenMultiTileInOrderModeWhenProgramming
auto gpuAddress = immCmdList->inOrderExecInfo->getBaseDeviceAddress();
ASSERT_TRUE(verifyInOrderDependency<FamilyType>(itor, 1, gpuAddress, immCmdList->isQwordInOrderCounter(), false));
ASSERT_TRUE(verifyInOrderDependency<FamilyType>(itor, 1, gpuAddress + device->getL0GfxCoreHelper().getImmediateWritePostSyncOffset(), immCmdList->isQwordInOrderCounter(), false));
if (immCmdList->inOrderExecInfo->isHostStorageDuplicated()) {
ASSERT_TRUE(verifyInOrderDependency<FamilyType>(itor, 2, gpuAddress, immCmdList->isQwordInOrderCounter(), false));
} else {
ASSERT_TRUE(verifyInOrderDependency<FamilyType>(itor, 1, gpuAddress, immCmdList->isQwordInOrderCounter(), false));
ASSERT_TRUE(verifyInOrderDependency<FamilyType>(itor, 1, gpuAddress + device->getL0GfxCoreHelper().getImmediateWritePostSyncOffset(), immCmdList->isQwordInOrderCounter(), false));
}
}
}
}