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Enable xe_hp_sdv i915 config 

Related-To: NEO-6149

Source location of Linux kernel DRM/i915 interface headers:
9641c49adb


Signed-off-by: Szymon Morek <szymon.morek@intel.com>
This commit is contained in:
Szymon Morek 2021-09-06 11:12:39 +00:00 committed by Compute-Runtime-Automation
parent 90bf2b29cc
commit d1e38d2370
35 changed files with 6771 additions and 250 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
CMakeLists.txt
View File

@ -339,9 +339,15 @@ else()
message(FATAL_ERROR "Metrics Discovery headers not available!")
endif()
if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "")
get_filename_component(I915_INCLUDES_DIR "${NEO_SOURCE_DIR}/third_party/uapi/dg1" ABSOLUTE)
if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "")
set(I915_LOCAL_MEM_EXP TRUE)
endif()
if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "")
set(I915_LOCAL_MEM_EXP TRUE)
endif()
if(I915_LOCAL_MEM_EXP)
get_filename_component(I915_INCLUDES_DIR "${NEO_SOURCE_DIR}/third_party/uapi/drm_tip" ABSOLUTE)
else()
get_filename_component(I915_INCLUDES_DIR "${NEO_SOURCE_DIR}/third_party${BRANCH_DIR_SUFFIX}uapi" ABSOLUTE)
endif()

15
opencl/test/unit_test/os_interface/linux/CMakeLists.txt
View File

@ -49,7 +49,6 @@ if(I915_LOCAL_MEM_EXP)
list(APPEND IGDRCL_SRCS_tests_os_interface_linux
${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_info_tests_exp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_memory_manager_localmem_tests.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_mock_drm_tip.cpp
)
else()
list(APPEND IGDRCL_SRCS_tests_os_interface_linux
@ -61,6 +60,20 @@ if(NEO__LIBVA_FOUND)
${CMAKE_CURRENT_SOURCE_DIR}/drm_va_sharing_tests.cpp
)
endif()
if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "")
list(APPEND IGDRCL_SRCS_tests_os_interface_linux
${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_tests_dg1.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_mock_dg1_internal.h
)
endif()
if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "")
list(APPEND IGDRCL_SRCS_tests_os_interface_linux
${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_tests_xe_hp_sdv.cpp
)
endif()
if(UNIX)
target_sources(igdrcl_tests PRIVATE ${IGDRCL_SRCS_tests_os_interface_linux})
endif()

9
opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h
View File

@ -68,18 +68,13 @@ class DrmMockCustomExp : public DrmMockCustom {
}
} break;
default: {
auto ret = ioctlGemCreateExt(request, arg);
if (ret != 0) {
std::cout << "unexpected IOCTL: " << std::hex << request << std::endl;
UNRECOVERABLE_IF(true);
}
std::cout << "unexpected IOCTL: " << std::hex << request << std::endl;
UNRECOVERABLE_IF(true);
} break;
}
return 0;
}
int ioctlGemCreateExt(unsigned long request, void *arg);
DrmMockCustomExp() : DrmMockCustom() {
ioctlExp_cnt.reset();
ioctlExp_expected.reset();

23
opencl/test/unit_test/os_interface/linux/drm_memory_info_tests_exp.cpp
View File

@ -21,20 +21,15 @@ TEST(MemoryInfo, givenMemoryRegionQuerySupportedWhenQueryingMemoryInfoThenMemory
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
for (auto onDrmTip : {false, true}) {
auto drm = std::make_unique<DrmMockExp>(*executionEnvironment->rootDeviceEnvironments[0]);
ASSERT_NE(nullptr, drm);
auto drm = std::make_unique<DrmMockExp>(*executionEnvironment->rootDeviceEnvironments[0]);
ASSERT_NE(nullptr, drm);
drm->queryMemoryRegionOnDrmTip = onDrmTip;
drm->queryMemoryInfo();
drm->queryMemoryInfo();
EXPECT_EQ(2u, drm->ioctlCallsCount);
auto memoryInfo = static_cast<MemoryInfoImpl *>(drm->getMemoryInfo());
ASSERT_NE(nullptr, memoryInfo);
EXPECT_EQ(2u, memoryInfo->getDrmRegionInfos().size());
}
EXPECT_EQ(2u, drm->ioctlCallsCount);
auto memoryInfo = static_cast<MemoryInfoImpl *>(drm->getMemoryInfo());
ASSERT_NE(nullptr, memoryInfo);
EXPECT_EQ(2u, memoryInfo->getDrmRegionInfos().size());
}
TEST(MemoryInfo, givenMemoryRegionQueryNotSupportedWhenQueryingMemoryInfoThenMemoryInfoIsNotCreated) {
@ -244,7 +239,7 @@ TEST(MemoryInfo, givenMemoryInfoWithRegionsWhenCreatingGemWithExtensionsThenRetu
auto ret = memoryInfo->createGemExt(drm.get(), &regionInfo, 2, 1024, handle);
EXPECT_EQ(1u, handle);
EXPECT_EQ(0u, ret);
EXPECT_EQ(2u, drm->ioctlCallsCount);
EXPECT_EQ(1u, drm->ioctlCallsCount);
EXPECT_EQ(1024u, drm->createExt.size);
}
@ -267,7 +262,7 @@ TEST(MemoryInfo, givenMemoryInfoWithRegionsWhenCreatingGemExtWithSingleRegionThe
auto ret = memoryInfo->createGemExtWithSingleRegion(drm.get(), 1, 1024, handle);
EXPECT_EQ(1u, handle);
EXPECT_EQ(0u, ret);
EXPECT_EQ(2u, drm->ioctlCallsCount);
EXPECT_EQ(1u, drm->ioctlCallsCount);
EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class);
EXPECT_EQ(1024u, drm->createExt.size);
}

34
opencl/test/unit_test/os_interface/linux/drm_memory_manager_localmem_tests.cpp
View File

@ -148,19 +148,11 @@ TEST_F(DrmMemoryManagerLocalMemoryTest, givenDrmMemoryManagerWhenCreateBufferObj
(1 << (MemoryBanks::getBankForLocalMemory(0) - 1)),
1));
ASSERT_NE(nullptr, bo);
EXPECT_EQ(2u, mock->ioctlCallsCount);
EXPECT_EQ(1u, mock->ioctlCallsCount);
EXPECT_EQ(1u, mock->createExt.handle);
EXPECT_EQ(size, mock->createExt.size);
EXPECT_EQ(I915_GEM_CREATE_EXT_SETPARAM, mock->setparamRegion.base.name);
auto regionParam = mock->setparamRegion.param;
EXPECT_EQ(0u, regionParam.handle);
EXPECT_EQ(1u, regionParam.size);
EXPECT_EQ(I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS, regionParam.param);
EXPECT_EQ(1u, mock->numRegions);
auto memRegions = mock->memRegions;
EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, memRegions.memory_class);
EXPECT_EQ(0u, memRegions.memory_instance);
@ -1084,28 +1076,6 @@ TEST_F(DrmMemoryManagerLocalMemoryTest, givenAllocationWithUnifiedMemoryAllocati
memoryManager->freeGraphicsMemory(allocation);
}
TEST_F(DrmMemoryManagerLocalMemoryTest, whenPrintBOCreateDestroyResultFlagIsSetWhileCreatingBufferObjectInMemoryRegionThenDebugInformationIsPrinted) {
DebugManagerStateRestore stateRestore;
DebugManager.flags.PrintBOCreateDestroyResult.set(true);
DebugManager.flags.EnableLocalMemory.set(1);
drm_i915_memory_region_info regionInfo[2] = {};
regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0};
regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0};
mock->memoryInfo.reset(new MemoryInfoImpl(regionInfo, 2));
auto gpuAddress = 0x1234u;
auto size = MemoryConstants::pageSize64k;
testing::internal::CaptureStdout();
auto bo = std::unique_ptr<BufferObject>(memoryManager->createBufferObjectInMemoryRegion(&memoryManager->getDrm(0), gpuAddress, size, (1 << (MemoryBanks::getBankForLocalMemory(0) - 1)), 1));
ASSERT_NE(nullptr, bo);
std::string output = testing::internal::GetCapturedStdout();
std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 65536, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_SETPARAM has returned: 0 BO-1 with size: 65536\n");
EXPECT_EQ(expectedOutput, output);
}
TEST(ResidencyTests, whenBuffersIsCreatedWithMakeResidentFlagThenItSuccessfulyCreates) {
VariableBackup<UltHwConfig> backup(&ultHwConfig);
ultHwConfig.useMockedPrepareDeviceEnvironmentsFunc = false;

78
opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h Normal file
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@ -0,0 +1,78 @@
/*
* Copyright (C) 2020-2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h"
namespace DG1_INTERNAL {
#undef DRM_IOCTL_I915_GEM_CREATE_EXT
#undef __I915_EXEC_UNKNOWN_FLAGS
#include "third_party/uapi/dg1/drm/i915_drm.h"
} // namespace DG1_INTERNAL
using namespace NEO;
class DrmMockDg1Internal : public DrmMockExp {
public:
DrmMockDg1Internal(RootDeviceEnvironment &rootDeviceEnvironment) : DrmMockDg1Internal(rootDeviceEnvironment, defaultHwInfo.get()) {}
DrmMockDg1Internal(RootDeviceEnvironment &rootDeviceEnvironment, const HardwareInfo *inputHwInfo) : DrmMockExp(rootDeviceEnvironment) {
rootDeviceEnvironment.setHwInfo(inputHwInfo);
}
void handleQueryItem(drm_i915_query_item *queryItem) override {
switch (queryItem->query_id) {
case DRM_I915_QUERY_MEMORY_REGIONS:
if (queryMemoryRegionInfoSuccessCount == 0) {
queryItem->length = -EINVAL;
} else {
queryMemoryRegionInfoSuccessCount--;
auto numberOfLocalMemories = 1u;
auto numberOfRegions = 1u + numberOfLocalMemories;
int regionInfoSize = sizeof(DG1_INTERNAL::drm_i915_query_memory_regions) + numberOfRegions * sizeof(DG1_INTERNAL::drm_i915_memory_region_info);
if (queryItem->length == 0) {
queryItem->length = regionInfoSize;
} else {
EXPECT_EQ(regionInfoSize, queryItem->length);
auto queryMemoryRegionInfo = reinterpret_cast<DG1_INTERNAL::drm_i915_query_memory_regions *>(queryItem->data_ptr);
EXPECT_EQ(0u, queryMemoryRegionInfo->num_regions);
queryMemoryRegionInfo->num_regions = numberOfRegions;
queryMemoryRegionInfo->regions[0].region.memory_class = I915_MEMORY_CLASS_SYSTEM;
queryMemoryRegionInfo->regions[0].region.memory_instance = 1;
queryMemoryRegionInfo->regions[0].probed_size = 2 * MemoryConstants::gigaByte;
queryMemoryRegionInfo->regions[1].region.memory_class = I915_MEMORY_CLASS_DEVICE;
queryMemoryRegionInfo->regions[1].region.memory_instance = 1;
queryMemoryRegionInfo->regions[1].probed_size = 2 * MemoryConstants::gigaByte;
}
}
break;
}
}
int handleKernelSpecificRequests(unsigned long request, void *arg) override {
if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) {
auto createExtParams = static_cast<drm_i915_gem_create_ext *>(arg);
if (createExtParams->size == 0) {
return EINVAL;
}
createExtParams->handle = 1u;
this->createExt = *createExtParams;
auto setparamRegion = reinterpret_cast<DG1_INTERNAL::drm_i915_gem_create_ext_setparam *>(createExtParams->extensions);
if (setparamRegion->base.name != I915_GEM_CREATE_EXT_SETPARAM) {
return EINVAL;
}
auto regionParam = reinterpret_cast<DG1_INTERNAL::drm_i915_gem_object_param *>(&setparamRegion->param);
if (regionParam->param != (I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS)) {
return EINVAL;
}
numRegions = regionParam->size;
memRegions = *reinterpret_cast<drm_i915_gem_memory_class_instance *>(regionParam->data);
return gemCreateExtRetVal;
}
return -1;
}
};

54
opencl/test/unit_test/os_interface/linux/drm_mock_drm_tip.cpp
View File

@ -1,54 +0,0 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "opencl/test/unit_test/os_interface/linux/device_command_stream_fixture_exp.h"
#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h"
// clang-format off
#include "shared/source/os_interface/linux/drm_tip.h"
// clang-format on
void DrmMockExp::handleQueryItemOnDrmTip(drm_i915_query_item *queryItem) {
switch (queryItem->query_id) {
case DRM_I915_QUERY_MEMORY_REGIONS:
if (queryMemoryRegionInfoSuccessCount == 0) {
queryItem->length = -EINVAL;
} else {
queryMemoryRegionInfoSuccessCount--;
auto numberOfLocalMemories = 1u;
auto numberOfRegions = 1u + numberOfLocalMemories;
int regionInfoSize = sizeof(DRM_TIP::drm_i915_query_memory_regions) + numberOfRegions * sizeof(DRM_TIP::drm_i915_memory_region_info);
if (queryItem->length == 0) {
queryItem->length = regionInfoSize;
} else {
EXPECT_EQ(regionInfoSize, queryItem->length);
auto queryMemoryRegionInfo = reinterpret_cast<DRM_TIP::drm_i915_query_memory_regions *>(queryItem->data_ptr);
EXPECT_EQ(0u, queryMemoryRegionInfo->num_regions);
queryMemoryRegionInfo->num_regions = numberOfRegions;
queryMemoryRegionInfo->regions[0].region.memory_class = I915_MEMORY_CLASS_SYSTEM;
queryMemoryRegionInfo->regions[0].region.memory_instance = 1;
queryMemoryRegionInfo->regions[0].probed_size = 2 * MemoryConstants::gigaByte;
queryMemoryRegionInfo->regions[1].region.memory_class = I915_MEMORY_CLASS_DEVICE;
queryMemoryRegionInfo->regions[1].region.memory_instance = 1;
queryMemoryRegionInfo->regions[1].probed_size = 2 * MemoryConstants::gigaByte;
}
}
break;
}
}
int DrmMockCustomExp::ioctlGemCreateExt(unsigned long request, void *arg) {
if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) {
auto createExtParams = reinterpret_cast<DRM_TIP::drm_i915_gem_create_ext *>(arg);
createExtSize = createExtParams->size;
createExtHandle = createExtParams->handle;
createExtExtensions = createExtParams->extensions;
ioctlExp_cnt.gemCreateExt++;
return 0;
}
return -1;
}

67
opencl/test/unit_test/os_interface/linux/drm_mock_exp.h
View File

@ -23,12 +23,11 @@ class DrmMockExp : public DrmMock {
uint32_t i915QuerySuccessCount = std::numeric_limits<uint32_t>::max();
uint32_t queryMemoryRegionInfoSuccessCount = std::numeric_limits<uint32_t>::max();
bool queryMemoryRegionOnDrmTip = false;
//DRM_IOCTL_I915_GEM_CREATE_EXT
drm_i915_gem_create_ext createExt{};
drm_i915_gem_create_ext_setparam setparamRegion{};
drm_i915_gem_memory_class_instance memRegions{};
uint32_t numRegions = 0;
int gemCreateExtRetVal = 0;
//DRM_IOCTL_I915_GEM_MMAP_OFFSET
@ -47,52 +46,19 @@ class DrmMockExp : public DrmMock {
return EINVAL;
}
for (auto i = 0u; i < query->num_items; i++) {
if (queryMemoryRegionOnDrmTip) {
handleQueryItemOnDrmTip(reinterpret_cast<drm_i915_query_item *>(query->items_ptr) + i);
} else {
handleQueryItem(reinterpret_cast<drm_i915_query_item *>(query->items_ptr) + i);
}
handleQueryItem(reinterpret_cast<drm_i915_query_item *>(query->items_ptr) + i);
}
return 0;
} else if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) {
auto createExtParams = static_cast<drm_i915_gem_create_ext *>(arg);
if (createExtParams->size == 0) {
return EINVAL;
}
this->createExt.size = createExtParams->size;
this->createExt.handle = createExtParams->handle = 1u;
auto extensions = reinterpret_cast<drm_i915_gem_create_ext_setparam *>(createExtParams->extensions);
if (extensions == nullptr) {
return EINVAL;
}
this->setparamRegion = *extensions;
if (this->setparamRegion.base.name != I915_GEM_CREATE_EXT_SETPARAM) {
return EINVAL;
}
if ((this->setparamRegion.param.size == 0) ||
(this->setparamRegion.param.param != (I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS))) {
return EINVAL;
}
auto data = reinterpret_cast<drm_i915_gem_memory_class_instance *>(this->setparamRegion.param.data);
if (data == nullptr) {
return EINVAL;
}
this->memRegions = *data;
if ((this->memRegions.memory_class != I915_MEMORY_CLASS_SYSTEM) && (this->memRegions.memory_class != I915_MEMORY_CLASS_DEVICE)) {
return EINVAL;
}
return gemCreateExtRetVal;
} else if (request == DRM_IOCTL_I915_GEM_MMAP_OFFSET) {
auto mmap_arg = static_cast<drm_i915_gem_mmap_offset *>(arg);
mmapOffsetFlagsReceived = mmap_arg->flags;
mmap_arg->offset = offset;
return mmapOffsetRetVal;
}
return -1;
return handleKernelSpecificRequests(request, arg);
}
void handleQueryItem(drm_i915_query_item *queryItem) {
virtual void handleQueryItem(drm_i915_query_item *queryItem) {
switch (queryItem->query_id) {
case DRM_I915_QUERY_MEMORY_REGIONS:
if (queryMemoryRegionInfoSuccessCount == 0) {
@ -121,5 +87,28 @@ class DrmMockExp : public DrmMock {
}
}
void handleQueryItemOnDrmTip(drm_i915_query_item *queryItem);
virtual int handleKernelSpecificRequests(unsigned long request, void *arg) {
if (request == DRM_IOCTL_I915_GEM_CREATE_EXT) {
auto createExtParams = static_cast<drm_i915_gem_create_ext *>(arg);
if (createExtParams->size == 0) {
return EINVAL;
}
createExtParams->handle = 1u;
this->createExt = *createExtParams;
auto extMemRegions = reinterpret_cast<drm_i915_gem_create_ext_memory_regions *>(createExt.extensions);
if (extMemRegions->base.name != I915_GEM_CREATE_EXT_MEMORY_REGIONS) {
return EINVAL;
}
this->numRegions = extMemRegions->num_regions;
this->memRegions = *reinterpret_cast<drm_i915_gem_memory_class_instance *>(extMemRegions->regions);
if (this->numRegions == 0) {
return EINVAL;
}
if ((this->memRegions.memory_class != I915_MEMORY_CLASS_SYSTEM) && (this->memRegions.memory_class != I915_MEMORY_CLASS_DEVICE)) {
return EINVAL;
}
return gemCreateExtRetVal;
}
return -1;
}
};

106
opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_dg1.cpp Normal file
View File

@ -0,0 +1,106 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/execution_environment/execution_environment.h"
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "shared/source/os_interface/linux/memory_info_impl.h"
#include "shared/test/common/helpers/debug_manager_state_restore.h"
#include "shared/test/common/helpers/default_hw_info.h"
#include "opencl/test/unit_test/os_interface/linux/drm_mock_dg1_internal.h"
#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h"
#include "test.h"
using namespace NEO;
using LocalMemoryHelperTestsDg1 = ::testing::Test;
DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1WhenCreateGemExtThenReturnCorrectValue) {
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
auto drm = std::make_unique<DrmMockExp>(*executionEnvironment->rootDeviceEnvironments[0]);
drm_i915_memory_region_info regionInfo[2] = {};
regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0};
regionInfo[0].probed_size = 8 * GB;
regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0};
regionInfo[1].probed_size = 16 * GB;
auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily);
uint32_t handle = 0;
auto ret = localMemHelper->createGemExt(drm.get(), &regionInfo[1], 1, 1024, handle);
EXPECT_EQ(0u, ret);
EXPECT_EQ(1u, handle);
EXPECT_EQ(1u, drm->numRegions);
EXPECT_EQ(1024u, drm->createExt.size);
EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class);
}
DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1WithDrmTipWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) {
DebugManagerStateRestore stateRestore;
DebugManager.flags.PrintBOCreateDestroyResult.set(true);
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
auto drm = std::make_unique<DrmMockExp>(*executionEnvironment->rootDeviceEnvironments[0]);
drm_i915_memory_region_info regionInfo[2] = {};
regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0};
regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0};
testing::internal::CaptureStdout();
auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily);
uint32_t handle = 0;
auto ret = localMemHelper->createGemExt(drm.get(), &regionInfo[1], 1, 1024, handle);
std::string output = testing::internal::GetCapturedStdout();
std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: 0 BO-1 with size: 1024\n");
EXPECT_EQ(expectedOutput, output);
EXPECT_EQ(1u, drm->ioctlCallsCount);
EXPECT_EQ(0u, ret);
}
DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1WhenCreateGemExtWithDebugFlagThenPrintDebugInfo) {
DebugManagerStateRestore stateRestore;
DebugManager.flags.PrintBOCreateDestroyResult.set(true);
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
auto drm = std::make_unique<DrmMockDg1Internal>(*executionEnvironment->rootDeviceEnvironments[0]);
drm_i915_memory_region_info regionInfo[2] = {};
regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0};
regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0};
testing::internal::CaptureStdout();
auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily);
uint32_t handle = 0;
auto ret = localMemHelper->createGemExt(drm.get(), &regionInfo[1], 1, 1024, handle);
std::string output = testing::internal::GetCapturedStdout();
std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_SETPARAM has returned: 0 BO-1 with size: 1024\n");
EXPECT_EQ(expectedOutput, output);
EXPECT_EQ(2u, drm->ioctlCallsCount);
EXPECT_EQ(0u, ret);
}
DG1TEST_F(LocalMemoryHelperTestsDg1, givenDg1AndMemoryRegionQuerySupportedWhenQueryingMemoryInfoThenMemoryInfoIsCreatedWithRegions) {
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
auto drm = std::make_unique<DrmMockDg1Internal>(*executionEnvironment->rootDeviceEnvironments[0]);
ASSERT_NE(nullptr, drm);
drm->queryMemoryInfo();
EXPECT_EQ(2u, drm->ioctlCallsCount);
auto memoryInfo = static_cast<MemoryInfoImpl *>(drm->getMemoryInfo());
ASSERT_NE(nullptr, memoryInfo);
EXPECT_EQ(2u, memoryInfo->getDrmRegionInfos().size());
}

62
opencl/test/unit_test/os_interface/linux/local_memory_helper_tests_xe_hp_sdv.cpp Normal file
View File

@ -0,0 +1,62 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/execution_environment/execution_environment.h"
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "shared/test/common/helpers/debug_manager_state_restore.h"
#include "shared/test/common/helpers/default_hw_info.h"
#include "opencl/test/unit_test/os_interface/linux/drm_mock_exp.h"
#include "test.h"
using namespace NEO;
using LocalMemoryHelperTestsXeHpSdv = ::testing::Test;
XEHPTEST_F(LocalMemoryHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtThenReturnCorrectValue) {
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
auto drm = std::make_unique<DrmMockExp>(*executionEnvironment->rootDeviceEnvironments[0]);
drm_i915_memory_region_info regionInfo[2] = {};
regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0};
regionInfo[0].probed_size = 8 * GB;
regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0};
regionInfo[1].probed_size = 16 * GB;
auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily);
uint32_t handle = 0;
auto ret = localMemHelper->createGemExt(drm.get(), &regionInfo[1], 1, 1024, handle);
EXPECT_EQ(0u, ret);
EXPECT_EQ(1u, handle);
EXPECT_EQ(1u, drm->numRegions);
EXPECT_EQ(1024u, drm->createExt.size);
EXPECT_EQ(I915_MEMORY_CLASS_DEVICE, drm->memRegions.memory_class);
}
XEHPTEST_F(LocalMemoryHelperTestsXeHpSdv, givenXeHpSdvWhenCreateGemExtWithDebugFlagThenPrintDebugInfo) {
DebugManagerStateRestore stateRestore;
DebugManager.flags.PrintBOCreateDestroyResult.set(true);
auto executionEnvironment = std::make_unique<ExecutionEnvironment>();
executionEnvironment->prepareRootDeviceEnvironments(1);
auto drm = std::make_unique<DrmMockExp>(*executionEnvironment->rootDeviceEnvironments[0]);
drm_i915_memory_region_info regionInfo[2] = {};
regionInfo[0].region = {I915_MEMORY_CLASS_SYSTEM, 0};
regionInfo[1].region = {I915_MEMORY_CLASS_DEVICE, 0};
testing::internal::CaptureStdout();
auto localMemHelper = LocalMemoryHelper::get(defaultHwInfo->platform.eProductFamily);
uint32_t handle = 0;
localMemHelper->createGemExt(drm.get(), &regionInfo[1], 1, 1024, handle);
std::string output = testing::internal::GetCapturedStdout();
std::string expectedOutput("Performing GEM_CREATE_EXT with { size: 1024, memory class: 1, memory instance: 0 }\nGEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: 0 BO-1 with size: 1024\n");
EXPECT_EQ(expectedOutput, output);
}

3
shared/source/os_interface/linux/CMakeLists.txt
View File

@ -100,7 +100,8 @@ if(I915_LOCAL_MEM_EXP)
${CMAKE_CURRENT_SOURCE_DIR}/drm_query_exp.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_tip.h
${CMAKE_CURRENT_SOURCE_DIR}/memory_info_impl.cpp
${CMAKE_CURRENT_SOURCE_DIR}/gem_create_ext_memory_regions.cpp
${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper.h
${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper.cpp
)
else()
list(APPEND NEO_CORE_OS_INTERFACE_LINUX

34
shared/source/os_interface/linux/drm_query_exp.cpp
View File

@ -9,12 +9,12 @@
#include "shared/source/helpers/string.h"
#include "shared/source/os_interface/linux/drm_engine_mapper.h"
#include "shared/source/os_interface/linux/engine_info_impl.h"
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "shared/source/os_interface/linux/memory_info_impl.h"
#include "shared/source/os_interface/linux/sys_calls.h"
#include "drm_neo.h"
#include "drm_query_flags.h"
#include "drm_tip.h"
#include <fstream>
@ -30,25 +30,6 @@ std::string getIoctlParamStringRemaining(int param) {
return std::to_string(param);
}
std::unique_ptr<uint8_t[]> translateDataQueryOnDrmTip(uint8_t *dataQuery, int32_t &length) {
auto dataOnDrmTip = reinterpret_cast<DRM_TIP::drm_i915_query_memory_regions *>(dataQuery);
auto lengthOnDrmTrip = static_cast<int32_t>(sizeof(DRM_TIP::drm_i915_query_memory_regions) + dataOnDrmTip->num_regions * sizeof(DRM_TIP::drm_i915_memory_region_info));
if (length == lengthOnDrmTrip) {
auto lengthTranslated = static_cast<int32_t>(sizeof(drm_i915_query_memory_regions) + dataOnDrmTip->num_regions * sizeof(drm_i915_memory_region_info));
auto dataQueryTranslated = std::make_unique<uint8_t[]>(lengthTranslated);
auto dataTranslated = reinterpret_cast<drm_i915_query_memory_regions *>(dataQueryTranslated.get());
dataTranslated->num_regions = dataOnDrmTip->num_regions;
for (uint32_t i = 0; i < dataTranslated->num_regions; i++) {
dataTranslated->regions[i].region.memory_class = dataOnDrmTip->regions[i].region.memory_class;
dataTranslated->regions[i].region.memory_instance = dataOnDrmTip->regions[i].region.memory_instance;
dataTranslated->regions[i].probed_size = dataOnDrmTip->regions[i].probed_size;
dataTranslated->regions[i].unallocated_size = dataOnDrmTip->regions[i].unallocated_size;
}
length = lengthTranslated;
return dataQueryTranslated;
}
return nullptr;
}
} // namespace IoctlHelper
bool Drm::queryEngineInfo(bool isSysmanEnabled) {
@ -66,13 +47,12 @@ bool Drm::queryMemoryInfo() {
auto length = 0;
auto dataQuery = this->query(DRM_I915_QUERY_MEMORY_REGIONS, DrmQueryItemFlags::empty, length);
if (dataQuery) {
auto dataQueryTranslated = IoctlHelper::translateDataQueryOnDrmTip(dataQuery.get(), length);
if (dataQueryTranslated) {
dataQuery.reset(dataQueryTranslated.release());
}
auto data = reinterpret_cast<drm_i915_query_memory_regions *>(dataQuery.get());
DEBUG_BREAK_IF(static_cast<size_t>(length) != sizeof(drm_i915_query_memory_regions) + data->num_regions * sizeof(drm_i915_memory_region_info));
this->memoryInfo.reset(new MemoryInfoImpl(data->regions, data->num_regions));
auto pHwInfo = getRootDeviceEnvironment().getHardwareInfo();
auto localMemHelper = LocalMemoryHelper::get(pHwInfo->platform.eProductFamily);
auto data = localMemHelper->translateIfRequired(dataQuery.release(), length);
auto memRegions = reinterpret_cast<drm_i915_query_memory_regions *>(data.get());
DEBUG_BREAK_IF(static_cast<size_t>(length) != sizeof(drm_i915_query_memory_regions) + memRegions->num_regions * sizeof(drm_i915_memory_region_info));
this->memoryInfo.reset(new MemoryInfoImpl(memRegions->regions, memRegions->num_regions));
return true;
}
return false;

2
shared/source/os_interface/linux/drm_tip.h
View File

@ -10,5 +10,5 @@
namespace DRM_TIP {
#undef DRM_IOCTL_I915_GEM_CREATE_EXT
#undef __I915_EXEC_UNKNOWN_FLAGS
#include "third_party/uapi/drm_tip/i915_drm.h"
#include "third_party/uapi/drm_tip/drm/i915_drm.h"
} // namespace DRM_TIP

31
shared/source/os_interface/linux/gem_create_ext_memory_regions.cpp
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@ -1,31 +0,0 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/helpers/debug_helpers.h"
#include "shared/source/os_interface/linux/memory_info_impl.h"
#include "drm_tip.h"
namespace NEO {
uint32_t MemoryInfoImpl::createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) {
DRM_TIP::drm_i915_gem_create_ext_memory_regions extRegions{};
extRegions.base.name = I915_GEM_CREATE_EXT_MEMORY_REGIONS;
extRegions.num_regions = dataSize;
extRegions.regions = reinterpret_cast<uintptr_t>(data);
drm_i915_gem_create_ext createExt{};
createExt.size = allocSize;
createExt.extensions = reinterpret_cast<uintptr_t>(&extRegions);
auto ret = drm->ioctl(DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt);
handle = createExt.handle;
return ret;
}
} // namespace NEO

7
shared/source/os_interface/linux/local/CMakeLists.txt Normal file
View File

@ -0,0 +1,7 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
add_subdirectories()

18
shared/source/os_interface/linux/local/dg1/CMakeLists.txt Normal file
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@ -0,0 +1,18 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_DG1 AND "${BRANCH_TYPE}" STREQUAL "")
set(NEO_CORE_OS_INTERFACE_LINUX_LOCAL_DG1
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_dg1.cpp
${CMAKE_CURRENT_SOURCE_DIR}/drm_tip_helper.cpp
)
set(CORE_SRCS_LINK_LINUX_LOCAL_DG1
${CMAKE_CURRENT_SOURCE_DIR}/enable_local_memory_helper_dg1.cpp
)
set_property(GLOBAL APPEND PROPERTY NEO_CORE_OS_INTERFACE_LINUX ${NEO_CORE_OS_INTERFACE_LINUX_LOCAL_DG1})
set_property(GLOBAL APPEND PROPERTY NEO_CORE_SRCS_LINK ${CORE_SRCS_LINK_LINUX_LOCAL_DG1})
endif()

60
shared/source/os_interface/linux/local/dg1/drm_tip_helper.cpp Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "third_party/uapi/drm_tip/drm/i915_drm.h"
#include <memory>
namespace NEO {
uint32_t createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) {
drm_i915_gem_create_ext_memory_regions extRegions{};
extRegions.base.name = I915_GEM_CREATE_EXT_MEMORY_REGIONS;
extRegions.num_regions = dataSize;
extRegions.regions = reinterpret_cast<uintptr_t>(data);
drm_i915_gem_create_ext createExt{};
createExt.size = allocSize;
createExt.extensions = reinterpret_cast<uintptr_t>(&extRegions);
auto ret = LocalMemoryHelper::ioctl(drm, DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt);
handle = createExt.handle;
return ret;
}
bool isQueryDrmTip(uint8_t *dataQuery, int32_t length) {
auto dataOnDrmTip = reinterpret_cast<drm_i915_query_memory_regions *>(dataQuery);
auto lengthOnDrmTip = static_cast<int32_t>(sizeof(drm_i915_query_memory_regions) + dataOnDrmTip->num_regions * sizeof(drm_i915_memory_region_info));
return length == lengthOnDrmTip;
}
namespace DG1_INTERNAL {
#undef DRM_IOCTL_I915_GEM_CREATE_EXT
#undef __I915_EXEC_UNKNOWN_FLAGS
#include "third_party/uapi/dg1/drm/i915_drm.h"
} // namespace DG1_INTERNAL
std::unique_ptr<uint8_t[]> translateToDrmTip(uint8_t *dataQuery, int32_t &length) {
auto dataOnInternalDrm = reinterpret_cast<DG1_INTERNAL::drm_i915_query_memory_regions *>(dataQuery);
auto lengthTranslated = static_cast<int32_t>(sizeof(drm_i915_query_memory_regions) + dataOnInternalDrm->num_regions * sizeof(drm_i915_memory_region_info));
auto dataQueryTranslated = std::make_unique<uint8_t[]>(lengthTranslated);
auto dataTranslated = reinterpret_cast<drm_i915_query_memory_regions *>(dataQueryTranslated.get());
dataTranslated->num_regions = dataOnInternalDrm->num_regions;
for (uint32_t i = 0; i < dataTranslated->num_regions; i++) {
dataTranslated->regions[i].region.memory_class = dataOnInternalDrm->regions[i].region.memory_class;
dataTranslated->regions[i].region.memory_instance = dataOnInternalDrm->regions[i].region.memory_instance;
dataTranslated->regions[i].probed_size = dataOnInternalDrm->regions[i].probed_size;
dataTranslated->regions[i].unallocated_size = dataOnInternalDrm->regions[i].unallocated_size;
}
length = lengthTranslated;
return dataQueryTranslated;
}
} // namespace NEO

14
shared/source/os_interface/linux/local/dg1/enable_local_memory_helper_dg1.cpp Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/os_interface/linux/local_memory_helper.h"
namespace NEO {
static EnableProductLocalMemoryHelper<IGFX_DG1> enableLocalMemHelperDG1;
} // namespace NEO

68
shared/source/os_interface/linux/local/dg1/local_memory_helper_dg1.cpp Normal file
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@ -0,0 +1,68 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "third_party/uapi/dg1/drm/i915_drm.h"
namespace NEO {
constexpr static auto gfxProduct = IGFX_DG1;
extern uint32_t createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle);
extern bool isQueryDrmTip(uint8_t *dataQuery, int32_t length);
extern std::unique_ptr<uint8_t[]> translateToDrmTip(uint8_t *dataQuery, int32_t &length);
template <>
uint32_t LocalMemoryHelperImpl<gfxProduct>::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) {
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu", allocSize);
if (DebugManager.flags.PrintBOCreateDestroyResult.get()) {
for (uint32_t i = 0; i < dataSize; i++) {
auto region = reinterpret_cast<drm_i915_gem_memory_class_instance *>(data)[i];
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d",
region.memory_class, region.memory_instance);
}
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n");
}
if (createGemExtMemoryRegions(drm, data, dataSize, allocSize, handle) == 0) {
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: %d BO-%u with size: %lu\n", 0, handle, allocSize);
return 0;
}
handle = 0u;
drm_i915_gem_object_param regionParam{};
regionParam.size = dataSize;
regionParam.data = reinterpret_cast<uintptr_t>(data);
regionParam.param = I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS;
drm_i915_gem_create_ext_setparam setparamRegion{};
setparamRegion.base.name = I915_GEM_CREATE_EXT_SETPARAM;
setparamRegion.param = regionParam;
drm_i915_gem_create_ext createExt{};
createExt.size = allocSize;
createExt.extensions = reinterpret_cast<uintptr_t>(&setparamRegion);
auto ret = LocalMemoryHelper::ioctl(drm, DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt);
handle = createExt.handle;
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_SETPARAM has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size);
return ret;
}
template <>
std::unique_ptr<uint8_t[]> LocalMemoryHelperImpl<gfxProduct>::translateIfRequired(uint8_t *dataQuery, int32_t length) {
if (isQueryDrmTip(dataQuery, length)) {
return std::unique_ptr<uint8_t[]>(dataQuery);
}
auto data = std::unique_ptr<uint8_t[]>(dataQuery);
return translateToDrmTip(data.get(), length);
}
} // namespace NEO

17
shared/source/os_interface/linux/local/xe_hp_sdv/CMakeLists.txt Normal file
View File

@ -0,0 +1,17 @@
#
# Copyright (C) 2021 Intel Corporation
#
# SPDX-License-Identifier: MIT
#
if(SUPPORT_XE_HP_SDV AND "${BRANCH_TYPE}" STREQUAL "")
set(NEO_CORE_OS_INTERFACE_LINUX_LOCAL_XE_HP_SDV
${CMAKE_CURRENT_SOURCE_DIR}/CMakeLists.txt
${CMAKE_CURRENT_SOURCE_DIR}/local_memory_helper_xe_hp_sdv.cpp
)
set(CORE_SRCS_LINK_LINUX_LOCAL_XE_HP_SDV
${CMAKE_CURRENT_SOURCE_DIR}/enable_local_memory_helper_xe_hp_sdv.cpp
)
set_property(GLOBAL APPEND PROPERTY NEO_CORE_OS_INTERFACE_LINUX ${NEO_CORE_OS_INTERFACE_LINUX_LOCAL_XE_HP_SDV})
set_property(GLOBAL APPEND PROPERTY NEO_CORE_SRCS_LINK ${CORE_SRCS_LINK_LINUX_LOCAL_XE_HP_SDV})
endif()

14
shared/source/os_interface/linux/local/xe_hp_sdv/enable_local_memory_helper_xe_hp_sdv.cpp Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/os_interface/linux/local_memory_helper.h"
namespace NEO {
static EnableProductLocalMemoryHelper<IGFX_XE_HP_SDV> enableLocalMemHelperXeHpSdv;
} // namespace NEO

53
shared/source/os_interface/linux/local/xe_hp_sdv/local_memory_helper_xe_hp_sdv.cpp Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/debug_settings/debug_settings_manager.h"
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "third_party/uapi/xe_hp_sdv/drm/i915_drm.h"
namespace NEO {
constexpr static auto gfxProduct = IGFX_XE_HP_SDV;
template <>
uint32_t LocalMemoryHelperImpl<gfxProduct>::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) {
drm_i915_gem_create_ext_memory_regions memRegions;
memRegions.num_regions = dataSize;
memRegions.regions = reinterpret_cast<uintptr_t>(data);
memRegions.base.name = I915_GEM_CREATE_EXT_MEMORY_REGIONS;
drm_i915_gem_create_ext createExt{};
createExt.size = allocSize;
createExt.extensions = reinterpret_cast<uintptr_t>(&memRegions);
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu",
allocSize);
if (DebugManager.flags.PrintBOCreateDestroyResult.get()) {
for (uint32_t i = 0; i < dataSize; i++) {
auto region = reinterpret_cast<drm_i915_gem_memory_class_instance *>(data)[i];
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d",
region.memory_class, region.memory_instance);
}
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n");
}
auto ret = ioctl(drm, DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt);
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size);
handle = createExt.handle;
return ret;
}
template <>
std::unique_ptr<uint8_t[]> LocalMemoryHelperImpl<gfxProduct>::translateIfRequired(uint8_t *dataQuery, int32_t length) {
return std::unique_ptr<uint8_t[]>(dataQuery);
}
template class LocalMemoryHelperImpl<gfxProduct>;
} // namespace NEO

20
shared/source/os_interface/linux/local_memory_helper.cpp Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "shared/source/os_interface/linux/drm_neo.h"
namespace NEO {
LocalMemoryHelper *localMemoryHelperFactory[IGFX_MAX_PRODUCT] = {};
uint32_t LocalMemoryHelper::ioctl(Drm *drm, unsigned long request, void *arg) {
return drm->ioctl(request, arg);
}
} // namespace NEO

56
shared/source/os_interface/linux/local_memory_helper.h Normal file
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@ -0,0 +1,56 @@
/*
* Copyright (C) 2021 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include "igfxfmid.h"
#include <cstddef>
#include <cstdint>
#include <memory>
struct drm_i915_gem_create_ext;
struct drm_i915_gem_memory_class_instance;
namespace NEO {
class Drm;
class LocalMemoryHelper;
extern LocalMemoryHelper *localMemoryHelperFactory[IGFX_MAX_PRODUCT];
class LocalMemoryHelper {
public:
static LocalMemoryHelper *get(PRODUCT_FAMILY product) {
auto localMemHelper = localMemoryHelperFactory[product];
if (!localMemHelper) {
return localMemoryHelperFactory[IGFX_DG1];
}
return localMemHelper;
}
static uint32_t ioctl(Drm *drm, unsigned long request, void *arg);
virtual uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) = 0;
virtual std::unique_ptr<uint8_t[]> translateIfRequired(uint8_t *dataQuery, int32_t length) = 0;
};
template <PRODUCT_FAMILY gfxProduct>
class LocalMemoryHelperImpl : public LocalMemoryHelper {
public:
static LocalMemoryHelper *get() {
static LocalMemoryHelperImpl<gfxProduct> instance;
return &instance;
}
uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) override;
std::unique_ptr<uint8_t[]> translateIfRequired(uint8_t *dataQuery, int32_t length);
};
template <PRODUCT_FAMILY gfxProduct>
struct EnableProductLocalMemoryHelper {
EnableProductLocalMemoryHelper() {
LocalMemoryHelper *plocalMemHelper = LocalMemoryHelperImpl<gfxProduct>::get();
localMemoryHelperFactory[gfxProduct] = plocalMemHelper;
}
};
} // namespace NEO

44
shared/source/os_interface/linux/memory_info_impl.cpp
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@ -7,15 +7,11 @@
#include "shared/source/os_interface/linux/memory_info_impl.h"
#include "shared/source/helpers/basic_math.h"
#include "shared/source/helpers/debug_helpers.h"
#include "shared/source/os_interface/linux/drm_neo.h"
#include "shared/source/helpers/hw_info.h"
#include "shared/source/os_interface/linux/local_memory_helper.h"
#include "drm/i915_drm.h"
#include <cstddef>
#include <vector>
namespace NEO {
MemoryInfoImpl::MemoryInfoImpl(const drm_i915_memory_region_info *regionInfo, size_t count)
@ -28,40 +24,8 @@ MemoryInfoImpl::MemoryInfoImpl(const drm_i915_memory_region_info *regionInfo, si
}
uint32_t MemoryInfoImpl::createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) {
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "Performing GEM_CREATE_EXT with { size: %lu", allocSize);
if (DebugManager.flags.PrintBOCreateDestroyResult.get()) {
for (uint32_t i = 0; i < dataSize; i++) {
auto region = reinterpret_cast<drm_i915_gem_memory_class_instance *>(data)[i];
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, ", memory class: %d, memory instance: %d",
region.memory_class, region.memory_instance);
}
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "%s", " }\n");
}
if (createGemExtMemoryRegions(drm, data, dataSize, allocSize, handle) == 0) {
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_MEMORY_REGIONS has returned: %d BO-%u with size: %lu\n", 0, handle, allocSize);
return 0;
}
drm_i915_gem_object_param regionParam{};
regionParam.size = dataSize;
regionParam.data = reinterpret_cast<uintptr_t>(data);
regionParam.param = I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS;
drm_i915_gem_create_ext_setparam setparamRegion{};
setparamRegion.base.name = I915_GEM_CREATE_EXT_SETPARAM;
setparamRegion.param = regionParam;
drm_i915_gem_create_ext createExt{};
createExt.size = allocSize;
createExt.extensions = reinterpret_cast<uintptr_t>(&setparamRegion);
auto ret = drm->ioctl(DRM_IOCTL_I915_GEM_CREATE_EXT, &createExt);
printDebugString(DebugManager.flags.PrintBOCreateDestroyResult.get(), stdout, "GEM_CREATE_EXT with EXT_SETPARAM has returned: %d BO-%u with size: %lu\n", ret, createExt.handle, createExt.size);
handle = createExt.handle;
return ret;
auto pHwInfo = drm->getRootDeviceEnvironment().getHardwareInfo();
return LocalMemoryHelper::get(pHwInfo->platform.eProductFamily)->createGemExt(drm, data, dataSize, allocSize, handle);
}
void MemoryInfoImpl::assignRegionsFromDistances(const void *distanceInfosPtr, size_t size) {

1
shared/source/os_interface/linux/memory_info_impl.h
View File

@ -31,7 +31,6 @@ class MemoryInfoImpl : public MemoryInfo {
void assignRegionsFromDistances(const void *distanceInfosPtr, size_t size);
uint32_t createGemExt(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle) override;
uint32_t createGemExtMemoryRegions(Drm *drm, void *data, uint32_t dataSize, size_t allocSize, uint32_t &handle);
drm_i915_gem_memory_class_instance getMemoryRegionClassAndInstance(uint32_t memoryBank, const HardwareInfo &hwInfo) {
auto &hwHelper = HwHelper::get(hwInfo.platform.eRenderCoreFamily);

4
shared/test/common/libult/CMakeLists.txt
View File

@ -13,6 +13,10 @@ macro(macro_for_each_platform)
if(EXISTS ${SRC_FILE})
list(APPEND igdrcl_libult_common_SRCS_ENABLE_TESTED_HW ${SRC_FILE})
endif()
set(SRC_FILE ${NEO_SHARED_DIRECTORY}/os_interface/linux/local${BRANCH_DIR_SUFFIX}${PLATFORM_IT_LOWER}/enable_local_memory_helper_${PLATFORM_IT_LOWER}.cpp)
if(EXISTS ${SRC_FILE})
list(APPEND igdrcl_libult_common_SRCS_ENABLE_TESTED_HW ${SRC_FILE})
endif()
set(SRC_FILE ${NEO_SHARED_DIRECTORY}/ail${BRANCH_DIR}${GEN_TYPE_LOWER}${BRANCH}${PLATFORM_IT_LOWER}/ail_configuration_${PLATFORM_IT_LOWER}.cpp)
if(EXISTS ${SRC_FILE})
list(APPEND igdrcl_libult_common_SRCS_ENABLE_TESTED_HW ${SRC_FILE})

0
third_party/uapi/drm_tip/drm.h → third_party/uapi/drm_tip/drm/drm.h vendored
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1
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#ifndef DRM_FOURCC_H
#define DRM_FOURCC_H
#define __user
#include "drm.h"
#if defined(__cplusplus)

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/*
* Copyright 2011 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef DRM_FOURCC_H
#define DRM_FOURCC_H
#define __user
#include "drm.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* DOC: overview
*
* In the DRM subsystem, framebuffer pixel formats are described using the
* fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
* fourcc code, a Format Modifier may optionally be provided, in order to
* further describe the buffer's format - for example tiling or compression.
*
* Format Modifiers
* ----------------
*
* Format modifiers are used in conjunction with a fourcc code, forming a
* unique fourcc:modifier pair. This format:modifier pair must fully define the
* format and data layout of the buffer, and should be the only way to describe
* that particular buffer.
*
* Having multiple fourcc:modifier pairs which describe the same layout should
* be avoided, as such aliases run the risk of different drivers exposing
* different names for the same data format, forcing userspace to understand
* that they are aliases.
*
* Format modifiers may change any property of the buffer, including the number
* of planes and/or the required allocation size. Format modifiers are
* vendor-namespaced, and as such the relationship between a fourcc code and a
* modifier is specific to the modifer being used. For example, some modifiers
* may preserve meaning - such as number of planes - from the fourcc code,
* whereas others may not.
*
* Vendors should document their modifier usage in as much detail as
* possible, to ensure maximum compatibility across devices, drivers and
* applications.
*
* The authoritative list of format modifier codes is found in
* `include/uapi/drm/drm_fourcc.h`
*/
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
((__u32)(c) << 16) | ((__u32)(d) << 24))
#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
/* Reserve 0 for the invalid format specifier */
#define DRM_FORMAT_INVALID 0
/* color index */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
/* 8 bpp Red */
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
/* 16 bpp Red */
#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
/* 16 bpp RG */
#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
/* 32 bpp RG */
#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
/* 8 bpp RGB */
#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
/* 16 bpp RGB */
#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
/* 24 bpp RGB */
#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
/* 32 bpp RGB */
#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
/*
* Floating point 64bpp RGB
* IEEE 754-2008 binary16 half-precision float
* [15:0] sign:exponent:mantissa 1:5:10
*/
#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
/* packed YCbCr */
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
/*
* packed Y2xx indicate for each component, xx valid data occupy msb
* 16-xx padding occupy lsb
*/
#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
/*
* packed Y4xx indicate for each component, xx valid data occupy msb
* 16-xx padding occupy lsb except Y410
*/
#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
/*
* packed YCbCr420 2x2 tiled formats
* first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
*/
/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
/*
* 1-plane YUV 4:2:0
* In these formats, the component ordering is specified (Y, followed by U
* then V), but the exact Linear layout is undefined.
* These formats can only be used with a non-Linear modifier.
*/
#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
/*
* 2 plane RGB + A
* index 0 = RGB plane, same format as the corresponding non _A8 format has
* index 1 = A plane, [7:0] A
*/
#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
/*
* 2 plane YCbCr
* index 0 = Y plane, [7:0] Y
* index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
* or
* index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
*/
#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y:x [10:6] little endian
* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
*/
#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y:x [10:6] little endian
* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
*/
#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y:x [12:4] little endian
* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
*/
#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
/*
* 2 plane YCbCr MSB aligned
* index 0 = Y plane, [15:0] Y little endian
* index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
*/
#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
* index 2: Cr plane, [7:0] Cr
* or
* index 1: Cr plane, [7:0] Cr
* index 2: Cb plane, [7:0] Cb
*/
#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
/*
* Format Modifiers:
*
* Format modifiers describe, typically, a re-ordering or modification
* of the data in a plane of an FB. This can be used to express tiled/
* swizzled formats, or compression, or a combination of the two.
*
* The upper 8 bits of the format modifier are a vendor-id as assigned
* below. The lower 56 bits are assigned as vendor sees fit.
*/
/* Vendor Ids: */
#define DRM_FORMAT_MOD_NONE 0
#define DRM_FORMAT_MOD_VENDOR_NONE 0
#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
/* add more to the end as needed */
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
#define fourcc_mod_code(vendor, val) \
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
/*
* Format Modifier tokens:
*
* When adding a new token please document the layout with a code comment,
* similar to the fourcc codes above. drm_fourcc.h is considered the
* authoritative source for all of these.
*/
/*
* Invalid Modifier
*
* This modifier can be used as a sentinel to terminate the format modifiers
* list, or to initialize a variable with an invalid modifier. It might also be
* used to report an error back to userspace for certain APIs.
*/
#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
/*
* Linear Layout
*
* Just plain linear layout. Note that this is different from no specifying any
* modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
* which tells the driver to also take driver-internal information into account
* and so might actually result in a tiled framebuffer.
*/
#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
/* Intel framebuffer modifiers */
/*
* Intel X-tiling layout
*
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
* in row-major layout. Within the tile bytes are laid out row-major, with
* a platform-dependent stride. On top of that the memory can apply
* platform-depending swizzling of some higher address bits into bit6.
*
* This format is highly platforms specific and not useful for cross-driver
* sharing. It exists since on a given platform it does uniquely identify the
* layout in a simple way for i915-specific userspace.
*/
#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
/*
* Intel Y-tiling layout
*
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
* chunks column-major, with a platform-dependent height. On top of that the
* memory can apply platform-depending swizzling of some higher address bits
* into bit6.
*
* This format is highly platforms specific and not useful for cross-driver
* sharing. It exists since on a given platform it does uniquely identify the
* layout in a simple way for i915-specific userspace.
*/
#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
/*
* Intel Yf-tiling layout
*
* This is a tiled layout using 4Kb tiles in row-major layout.
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
* are arranged in four groups (two wide, two high) with column-major layout.
* Each group therefore consits out of four 256 byte units, which are also laid
* out as 2x2 column-major.
* 256 byte units are made out of four 64 byte blocks of pixels, producing
* either a square block or a 2:1 unit.
* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
* in pixel depends on the pixel depth.
*/
#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
/*
* Intel color control surface (CCS) for render compression
*
* The framebuffer format must be one of the 8:8:8:8 RGB formats.
* The main surface will be plane index 0 and must be Y/Yf-tiled,
* the CCS will be plane index 1.
*
* Each CCS tile matches a 1024x512 pixel area of the main surface.
* To match certain aspects of the 3D hardware the CCS is
* considered to be made up of normal 128Bx32 Y tiles, Thus
* the CCS pitch must be specified in multiples of 128 bytes.
*
* In reality the CCS tile appears to be a 64Bx64 Y tile, composed
* of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
* But that fact is not relevant unless the memory is accessed
* directly.
*/
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
/*
* Intel color control surfaces (CCS) for Gen-12 render compression.
*
* The main surface is Y-tiled and at plane index 0, the CCS is linear and
* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
* main surface. In other words, 4 bits in CCS map to a main surface cache
* line pair. The main surface pitch is required to be a multiple of four
* Y-tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
/*
* Intel color control surfaces (CCS) for Gen-12 media compression
*
* The main surface is Y-tiled and at plane index 0, the CCS is linear and
* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
* main surface. In other words, 4 bits in CCS map to a main surface cache
* line pair. The main surface pitch is required to be a multiple of four
* Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
* Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
* planes 2 and 3 for the respective CCS.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
/* ID #8 is reserved for TGL CCS_CC */
/*
* Intel color control surfaces (CCS) for DG1 render compression.
*
* The layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, but since
* DG1 may have a different hashing/compression algorithm, the actual contents
* of compressed buffers may not be safely shareable between TGL and DG1, hence
* the new modifier assignment.
*/
#define I915_FORMAT_MOD_Y_TILED_DG1_RC_CCS fourcc_mod_code(INTEL, 9)
/*
* Intel color control surfaces (CCS) for Gen-12 media compression
*
* The layout is the same as I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, but since
* DG1 may have a different hashing/compression algorithm, the actual contents
* of compressed buffers may not be safely shareable between TGL and DG1, hence
* the new modifier assignment.
*/
#define I915_FORMAT_MOD_Y_TILED_DG1_MC_CCS fourcc_mod_code(INTEL, 10)
/* ID #11 is reserved for DG1 CCS_CC */
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
* Macroblocks are laid in a Z-shape, and each pixel data is following the
* standard NV12 style.
* As for NV12, an image is the result of two frame buffers: one for Y,
* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
* Alignment requirements are (for each buffer):
* - multiple of 128 pixels for the width
* - multiple of 32 pixels for the height
*
* For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
/*
* Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
*
* This is a simple tiled layout using tiles of 16x16 pixels in a row-major
* layout. For YCbCr formats Cb/Cr components are taken in such a way that
* they correspond to their 16x16 luma block.
*/
#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
/*
* Qualcomm Compressed Format
*
* Refers to a compressed variant of the base format that is compressed.
* Implementation may be platform and base-format specific.
*
* Each macrotile consists of m x n (mostly 4 x 4) tiles.
* Pixel data pitch/stride is aligned with macrotile width.
* Pixel data height is aligned with macrotile height.
* Entire pixel data buffer is aligned with 4k(bytes).
*/
#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
/* Vivante framebuffer modifiers */
/*
* Vivante 4x4 tiling layout
*
* This is a simple tiled layout using tiles of 4x4 pixels in a row-major
* layout.
*/
#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
/*
* Vivante 64x64 super-tiling layout
*
* This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
* contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
* major layout.
*
* For more information: see
* https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
*/
#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
/*
* Vivante 4x4 tiling layout for dual-pipe
*
* Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
* different base address. Offsets from the base addresses are therefore halved
* compared to the non-split tiled layout.
*/
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
/*
* Vivante 64x64 super-tiling layout for dual-pipe
*
* Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
* starts at a different base address. Offsets from the base addresses are
* therefore halved compared to the non-split super-tiled layout.
*/
#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
/* NVIDIA frame buffer modifiers */
/*
* Tegra Tiled Layout, used by Tegra 2, 3 and 4.
*
* Pixels are arranged in simple tiles of 16 x 16 bytes.
*/
#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
/*
* 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
*
* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
* vertically by a power of 2 (1 to 32 GOBs) to form a block.
*
* Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
*
* Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
* Valid values are:
*
* 0 == ONE_GOB
* 1 == TWO_GOBS
* 2 == FOUR_GOBS
* 3 == EIGHT_GOBS
* 4 == SIXTEEN_GOBS
* 5 == THIRTYTWO_GOBS
*
* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
* in full detail.
*/
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
fourcc_mod_code(NVIDIA, 0x10)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
fourcc_mod_code(NVIDIA, 0x11)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
fourcc_mod_code(NVIDIA, 0x12)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
fourcc_mod_code(NVIDIA, 0x13)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
fourcc_mod_code(NVIDIA, 0x14)
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
fourcc_mod_code(NVIDIA, 0x15)
/*
* Some Broadcom modifiers take parameters, for example the number of
* vertical lines in the image. Reserve the lower 32 bits for modifier
* type, and the next 24 bits for parameters. Top 8 bits are the
* vendor code.
*/
#define __fourcc_mod_broadcom_param_shift 8
#define __fourcc_mod_broadcom_param_bits 48
#define fourcc_mod_broadcom_code(val, params) \
fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
#define fourcc_mod_broadcom_param(m) \
((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
#define fourcc_mod_broadcom_mod(m) \
((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
__fourcc_mod_broadcom_param_shift))
/*
* Broadcom VC4 "T" format
*
* This is the primary layout that the V3D GPU can texture from (it
* can't do linear). The T format has:
*
* - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
* pixels at 32 bit depth.
*
* - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
* 16x16 pixels).
*
* - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
* even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
* they're (TR, BR, BL, TL), where bottom left is start of memory.
*
* - an image made of 4k tiles in rows either left-to-right (even rows of 4k
* tiles) or right-to-left (odd rows of 4k tiles).
*/
#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
/*
* Broadcom SAND format
*
* This is the native format that the H.264 codec block uses. For VC4
* HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
*
* The image can be considered to be split into columns, and the
* columns are placed consecutively into memory. The width of those
* columns can be either 32, 64, 128, or 256 pixels, but in practice
* only 128 pixel columns are used.
*
* The pitch between the start of each column is set to optimally
* switch between SDRAM banks. This is passed as the number of lines
* of column width in the modifier (we can't use the stride value due
* to various core checks that look at it , so you should set the
* stride to width*cpp).
*
* Note that the column height for this format modifier is the same
* for all of the planes, assuming that each column contains both Y
* and UV. Some SAND-using hardware stores UV in a separate tiled
* image from Y to reduce the column height, which is not supported
* with these modifiers.
*/
#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
fourcc_mod_broadcom_code(2, v)
#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
fourcc_mod_broadcom_code(3, v)
#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
fourcc_mod_broadcom_code(4, v)
#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
fourcc_mod_broadcom_code(5, v)
#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
/* Broadcom UIF format
*
* This is the common format for the current Broadcom multimedia
* blocks, including V3D 3.x and newer, newer video codecs, and
* displays.
*
* The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
* and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
* stored in columns, with padding between the columns to ensure that
* moving from one column to the next doesn't hit the same SDRAM page
* bank.
*
* To calculate the padding, it is assumed that each hardware block
* and the software driving it knows the platform's SDRAM page size,
* number of banks, and XOR address, and that it's identical between
* all blocks using the format. This tiling modifier will use XOR as
* necessary to reduce the padding. If a hardware block can't do XOR,
* the assumption is that a no-XOR tiling modifier will be created.
*/
#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
/*
* Arm Framebuffer Compression (AFBC) modifiers
*
* AFBC is a proprietary lossless image compression protocol and format.
* It provides fine-grained random access and minimizes the amount of data
* transferred between IP blocks.
*
* AFBC has several features which may be supported and/or used, which are
* represented using bits in the modifier. Not all combinations are valid,
* and different devices or use-cases may support different combinations.
*
* Further information on the use of AFBC modifiers can be found in
* Documentation/gpu/afbc.rst
*/
/*
* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
* modifiers) denote the category for modifiers. Currently we have only two
* categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
* different categories.
*/
#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
/*
* AFBC superblock size
*
* Indicates the superblock size(s) used for the AFBC buffer. The buffer
* size (in pixels) must be aligned to a multiple of the superblock size.
* Four lowest significant bits(LSBs) are reserved for block size.
*
* Where one superblock size is specified, it applies to all planes of the
* buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
* the first applies to the Luma plane and the second applies to the Chroma
* plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
* Multiple superblock sizes are only valid for multi-plane YCbCr formats.
*/
#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
/*
* AFBC lossless colorspace transform
*
* Indicates that the buffer makes use of the AFBC lossless colorspace
* transform.
*/
#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
/*
* AFBC block-split
*
* Indicates that the payload of each superblock is split. The second
* half of the payload is positioned at a predefined offset from the start
* of the superblock payload.
*/
#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
/*
* AFBC sparse layout
*
* This flag indicates that the payload of each superblock must be stored at a
* predefined position relative to the other superblocks in the same AFBC
* buffer. This order is the same order used by the header buffer. In this mode
* each superblock is given the same amount of space as an uncompressed
* superblock of the particular format would require, rounding up to the next
* multiple of 128 bytes in size.
*/
#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
/*
* AFBC copy-block restrict
*
* Buffers with this flag must obey the copy-block restriction. The restriction
* is such that there are no copy-blocks referring across the border of 8x8
* blocks. For the subsampled data the 8x8 limitation is also subsampled.
*/
#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
/*
* AFBC tiled layout
*
* The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
* superblocks inside a tile are stored together in memory. 8x8 tiles are used
* for pixel formats up to and including 32 bpp while 4x4 tiles are used for
* larger bpp formats. The order between the tiles is scan line.
* When the tiled layout is used, the buffer size (in pixels) must be aligned
* to the tile size.
*/
#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
/*
* AFBC solid color blocks
*
* Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
* can be reduced if a whole superblock is a single color.
*/
#define AFBC_FORMAT_MOD_SC (1ULL << 9)
/*
* AFBC double-buffer
*
* Indicates that the buffer is allocated in a layout safe for front-buffer
* rendering.
*/
#define AFBC_FORMAT_MOD_DB (1ULL << 10)
/*
* AFBC buffer content hints
*
* Indicates that the buffer includes per-superblock content hints.
*/
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
/*
* Arm 16x16 Block U-Interleaved modifier
*
* This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
* into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
* in the block are reordered.
*/
#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
/*
* Allwinner tiled modifier
*
* This tiling mode is implemented by the VPU found on all Allwinner platforms,
* codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
* planes.
*
* With this tiling, the luminance samples are disposed in tiles representing
* 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
* The pixel order in each tile is linear and the tiles are disposed linearly,
* both in row-major order.
*/
#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
#if defined(__cplusplus)
}
#endif
#endif /* DRM_FOURCC_H */

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