9cd47ffeaf
Add ownership management when ensuring space for shared heaps
...
Related-To: NEO-7142
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-04 12:27:11 +02:00
3d92186362
Add heap sharing to immediate command lists
...
This change is intended to be used in immediate command lists that are
using flush task functionality.
With this change all immediate command list using the same csr will consume
shared allocations for dsh and ssh heaps. This will decrease number of SBA
commands dispatched when multiple command lists coexists and dispatch kernels.
With this change new SBA command should be dispatched only when current heap
allocation is exhausted.
Functionality is currently disabled and available under debug key.
Functionality will be enabled by default for all immediate command lists
with flush task functionality enabled.
Related-To: NEO-7142
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-10-03 18:50:10 +02:00
48824acab2
Improve SBA programming
...
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-09-30 12:07:16 +02:00
1c446ff213
Remove wait on user fence during cmdlist destroy/reset
...
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-7158
2022-09-28 16:46:10 +02:00
f0888fece2
Rename command list tracking debug flag and variables
...
This change reflects exact nature of debug variable and what is code
actually doing
Related-To: NEO-7187
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-26 18:59:39 +02:00
56cb1f757b
programStateBaseAddress: improve code reuse
...
Another step towards cleaner callers of
StateBaseAddressHelper<>::programStateBaseAddress.
Export programming state base address into a separate function to
improve code reuse and reduce copy-pasted fragments, which make code
modifications or maintenance more and more difficult over time. Use
specialization for gen-specific variations.
Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-21 11:54:57 +02:00
17d87a4c69
Add RemoveUserFenceInCmdlistResetAndDestroy debug flag
...
Related-To: NEO-7156
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-09-19 22:35:53 +02:00
218a98f7f7
Refactor of pipeline select programming
...
Adding new interface to cooperate with hw context state
Simplify programming removing unnecessary functions
Code optimization that stop using expensive call and instead
stores configuration parameter
Related-To: NEO-5019
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-15 15:38:10 +02:00
307b74869c
Add OverrideCmdListCmdBufferSize debug flag
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-7156
2022-09-14 13:09:54 +02:00
c99fe2ae23
Reduce surface state indirect heap size
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-09-14 10:25:06 +02:00
0d0d6a300e
Debugger: simplify captureStateBaseAddress()
...
So far captureStateBaseAddress() was a wrapper around
programSbaTrackingCommands(), doing an additional checking before
calling the latter. The checking is apparently no longer relevant, so
unify the distinction and remove part of the code which is no longer
needed.
In practice, keep the captureStateBaseAddress() while moving the body of
programSbaTrackingCommands() into it. This imposes lower diff-impact
onto the class hierarchy. Remove the second function. Simplify the
caller which had to distinct these two functions previously.
Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-13 17:08:31 +02:00
410fd7d909
Correct binding table prefetch
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-6075
Binding table entry count was zeroed even when
ForceBtpPrefetchMode debug flag was enabled
2022-09-13 14:34:30 +02:00
e1b80ba1a8
Cleanup: updateStreamProperties(), SBA tracking
...
Fixes found out while working on the StateBaseAddress adaptation to
StreamProperties. Removing unused parameters, improving code reuse
(further improvements come with following commits).
Related-To: NEO-6774
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-09-12 17:56:28 +02:00
f7332fc30b
Change order of EncodeDispatchKernelArgs members
...
Order members by their size
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-09-06 16:49:48 +02:00
22fb71a268
Walker partition: Improve barrier programming
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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-09-02 18:09:38 +02:00
a4b9b3b837
Extend encode class for start and end hw commands
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Related-To: NEO-5019
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-09-02 16:29:36 +02:00
c3f7e40a8d
Rename special pipeline select mode to systolic
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-31 22:16:26 +02:00
8cc0177f1c
Change DG2 l1 cache policy to WB
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With compiler LSC WAs this gives better performance.
If debugger is active, policy will not be changed ie.
will be WBP.
Related-To: NEO-7003
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-31 14:31:23 +02:00
2621460e80
Revert "Change DG2 l1 cache policy to WB"
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This reverts commit a820e73dd7
2022-08-27 08:04:19 +02:00
54042a191e
Implement PauseOnEnqueue for L0
...
Allow pausing execution before and after enqueuing kernel
using the PauseOnEnqueue and PauseOnGpuMode debug flags.
Related-To: NEO-6570
Signed-off-by: Naklicki, Mateusz <mateusz.naklicki@intel.com>
2022-08-26 14:48:58 +02:00
a820e73dd7
Change DG2 l1 cache policy to WB
...
With compiler LSC WAs this gives better performance.
If debugger is active, policy will not be changed ie.
will be WBP.
Related-To: NEO-7003
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-26 12:58:45 +02:00
9763d42379
Fix type redefinition
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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-24 09:45:13 +02:00
9974d95dc3
Restore wait on user fence during cmdlist destoy/reset
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-7156
2022-08-23 16:51:56 +02:00
595cfebaef
Refactor PIPE_CONTROL programming
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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-23 13:55:25 +02:00
18adbed233
feat(zebin): add thread scheduling mode support
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Resolves: NEO-7197
Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2022-08-18 16:10:18 +02:00
0011368775
Add parameter to set surface state base address value
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This change introduces capability to set surface state base address
when surface state heap or global base address are not available
Related-To: NEO-7187
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-18 15:36:43 +02:00
aa3a4765b9
Respect ForceAllResourcesUncached flag
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Respect debug flag ForceAllResourcesUncached even when
Override L1 Policy flags are also set
Related-To: NEO-7003
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-08-18 11:46:33 +02:00
acac5ea0d5
Use correct engine group type when programming state base address
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Command lists and their helper classes should use engine group type
assigned to the particular command list to check if it is RCS group
and not use default CSR class assigned to the device, since default
and current in command list might be different.
Related-To: NEO-5019
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 20:38:23 +02:00
6c38b36251
Unify getting state base address command space from command buffer
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Related-To: NEO-5019
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 11:49:02 +02:00
ceb9d81f87
Add struct argument for input/output in StateBaseAddressHelper
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This refactor makes future interface changes easier
Related-To: NEO-5019
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-17 10:28:49 +02:00
1b9d50660a
Unify programming of binding table base address command
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-08-10 14:35:02 +02:00
ed0c36117e
Apply heuristics when setting TG dispatch size on XE_HPC_CORE
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The default TG dispatch size can be changed
to a better value based on number of threads in TG or
currently available amount of threads on GPU.
Decision on what TG dispatch size should be are based on
implemented heuristics.
Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
Related-To: NEO-6989
2022-08-08 16:43:10 +02:00
8b5c567bea
Remove wait on user fence during cmdlist destroy/reset
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
Related-To: NEO-7156
2022-08-05 09:24:04 +02:00
98d776867f
Add initial support for KernelArgsBuffer allocation
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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-08-03 20:28:21 +02:00
c200c6e2dd
Pass LSH to EncodeDispatchKernel
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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-26 15:37:28 +02:00
a3903c385e
Remove HW types from synchronization interface
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Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2022-07-25 13:59:26 +02:00
d4d54f5093
Cleanup includes
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-07-25 09:58:38 +02:00
f4879f064f
Allocate per-tile RTDispatchGlobals, handle ray tracing patch tokens.
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Related-to: NEO-6711
Signed-off-by: Raiyan Latif <raiyan.latif@intel.com>
2022-07-22 06:29:29 +02:00
82a6f9e7b2
Use compute walker system fence for system memory or events in use
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Related-To: NEO-6959
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-07-13 11:55:32 +02:00
0b26ee3664
Add surface state programming for kernels with images and stateless buffers
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2022-07-04 12:24:11 +02:00
76d905b1f2
Pass LogicalStateHelper to SBA helper
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-07-01 14:52:20 +02:00
a8e2bd3f98
hw_cmds.h usage cleanup
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Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-06-29 11:15:45 +02:00
3ed8b4319f
Use primary buffer start when immediate command list using flush task
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Related-To: NEO-7091
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-29 10:52:43 +02:00
2c853adac3
Use LogicalStateHelper to program ComputeMode
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-27 15:25:55 +02:00
5236b34629
Set L1 policy globally
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Related-To: NEO-7003
Add function to control l1 policy for both
stateless and surface state cache.
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2022-06-27 14:57:31 +02:00
5bce1eceb1
Remove self cleanup section when using immediate command list
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-27 13:29:52 +02:00
4673a98074
includes simplification
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use HW specific header instead generic one
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-06-24 22:07:18 +02:00
61b2ee45cd
Use LogicalStateHelper to encode SystemMemoryFence
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-06-24 13:29:58 +02:00
615fd4c37a
Add programming of Dispatch Walk Order in COMPUTE_WALKER for xe_hpg
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- update xe_hpg generated commands
- add method isAdjustWalkOrderAvailable
Related-To: NEO-7065
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-06-17 10:42:15 +02:00
f5b1a0e45b
Use internal event object in command lists methods
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-06-14 21:23:43 +02:00
8de043b71f
Stop redundant SBA programming due to global atomics
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For all platforms different than XE_HP_SDV (ATS) stop considering the
`useGlobalAtomics` flag as a decisive factor for trigerring the SBA
(StateBaseAddress) programming on the HW. Only XE_HP_SDV supports such
flag.
For consistency of the implementation, keep the related logic in one
place only, that is a helper in `command_encoder` and then just reuse it
in different places (`command_stream_receiver`).
Related-To: NEO-6953
Signed-off-by: Maciej Bielski <maciej.bielski@intel.com>
2022-06-08 10:39:56 +02:00
e07bf76f8c
Move adjustWalkOrder in encodeThreadData
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-include case when localIdsGenarationByRuntime
Related-To: NEO-6964
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-06-07 16:57:02 +02:00
dc1fe7d59a
Change MemoryPool to enum class
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Use enum class for MemoryPool in GraphicsAllocation
This change will ensure that GA is constructed in the proper way
- Rename namespace for isSystemMemoryPool method
- Add method getMemoryPoolString for logging actual pool which is in used
- Remove wrong pattern in GraphicsAllocation constructor
Related-To: NEO-6523
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2022-06-02 12:46:15 +02:00
afceaa6e19
Use system fence only when using system allocations or system scope event
...
Related-To: NEO-6959
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-05-31 12:55:30 +02:00
b2021498e2
Create method adjustWalkOrder
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Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-27 16:05:31 +02:00
35d1f2e341
Add debug flag to control programming of thread arbitration policy with SCM
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Related-To: NEO-6801
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-05-27 11:35:41 +02:00
8431234845
Change interface to method programing additional fields of command
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Related-To: NEO-6959
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-05-26 21:32:59 +02:00
7463e1970b
Cleanup headers
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Make TUs and headers self-contained, remove unused headers
Signed-off-by: Daniel Chabrowski <daniel.chabrowski@intel.com>
2022-05-18 11:42:06 +02:00
96e1eb7467
Move variables baseDieRev and baseDieA0Masked from xe_hpc to pvc
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Pvc specific variables should be located in pvc struct
Related-To: NEO-6738
Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-05-17 12:19:16 +02:00
52a3bfcfde
Unify programming of pipe control command
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-05-16 18:42:04 +02:00
7eafb1e877
remove unused code
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Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-05-16 18:15:03 +02:00
d643c587b9
style: correct variable naming
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Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-05-16 15:02:15 +02:00
2fcda0a528
Refactor: Change decanonize method accessing point
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Accessing decanonize method as a member of GmmHelper class object
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2022-05-11 12:57:02 +02:00
d18e89e439
Create getGmmHelper function in Gmm
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Add get function in order to provide access on GmmHelper object
Related-To: NEO-6523
Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2022-05-10 11:34:19 +02:00
a6490062a9
fix code issues reported by clang 14
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Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2022-04-29 10:43:34 +02:00
3900c9d24a
Report to StreamProperties whether large grf should be programmed with SCM
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Add helper method to UnitTestHelper to query programmed grf values.
Related-To: NEO-6659
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-04-27 13:20:14 +02:00
31b2433b2f
Avoid implicit sync for async mode immediate copy queue
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Related-To: LOCI-1988
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@intel.com>
2022-04-27 08:50:18 +02:00
944319b3d9
Correct media compression format for blitter operations on planar images
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Set most significant bit for chroma planes.
Move common logic to helper function.
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-04-22 17:02:16 +02:00
5911515ed0
Refactor debugger code
...
- helper sets all SbaAddresses for debugger in
EncodeStateBaseAddress<GfxFamily>::setSbaAddressesForDebugger()
- change DebuggerL0::captureStateBaseAddress() to take
LinearStream
- move getSbaTrackingCommandsSize() to Debugger class
Related-To: NEO-6845
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-04-21 13:04:34 +02:00
db9c0d1103
Refactor and enable MI_MEM_FENCE programming for DirectSubmission dispatch
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-04-07 12:53:56 +02:00
fd45ac133d
Unify append calls
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Related-To: NEO-6242
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-04-07 10:18:55 +02:00
4044320301
Limit allocations in execute command list
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Reserve space in ResidencyContainer
Related-To: NEO-6837
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-04-06 15:00:34 +02:00
f4407064a4
Refactor store register mem encoder to include partition parameter
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Related-To: NEO-6811
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-04-06 14:00:56 +02:00
beff0019d1
SBA tracking for single address space
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Related-To: NEO-6539
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-04-01 15:24:11 +02:00
4374197c9d
Fixes for bindless configuration
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- enhance ults code, do not inject memory manager
- fix some issues related to bindless global heap
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2022-04-01 15:08:43 +02:00
308f9ccfff
Do not allocate dynamic state heap if not needed
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Dynamic state heap is only used for sampler data.
Related-To: NEO-6821
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2022-03-31 12:13:13 +02:00
fccda460d6
Optimize zeCommandListCreate
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Do not allocate heap if command list is copy only.
Related-To: NEO-6821
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
Co-authored-by: Michal Mrozek <michal.mrozek@intel.com>
2022-03-28 16:31:10 +02:00
3123ab5bf9
Correct media compression format for planar images
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Set most significant bit for chroma planes.
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-26 21:54:08 +01:00
e11eb46bff
Unify logic for programming mocs in post sync struct
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-03-25 17:01:51 +01:00
ebc006ad53
Move SBA related WAs logic from CSR to EncodeWA
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Signed-off-by: Krzysztof Gibala <krzysztof.gibala@intel.com>
2022-03-24 12:24:56 +01:00
35d9d9e18c
Do not force resetting SCM properties
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Related-To: NEO-6728
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-16 14:16:45 +01:00
cd95572443
Reuse common logic of programming SCM fields for gen 9 and gen 11
...
Logic related to programming non coherent and thread arbitration policy for
gens 9 and 11 has been moved to EncodeComputeMode object, where similar
logic for gens gen12lp and newer is located.
Functions PreambleHelper::programThreadArbitration and
PreambleHelper::getThreadArbitrationCommandsSize have been removed.
Redundant setForceNonCoherent call has been removed from XE HPG
Related-To: NEO-6728
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-16 10:04:32 +01:00
32b0f7b014
Remove redundant value CsrSizeRequestFlags::numGrfRequiredChanged
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Related-To: NEO-5995
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-15 15:08:15 +01:00
3eab7009ac
Move SCM related WAs logic from CSR to EncodeComputeMode
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This will help with unifying the logic between APIs and GENs.
Related-To: NEO-6728
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-11 14:00:53 +01:00
e24322f266
Debug flag to control MI_ARB_CHECK prefetcher
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-03-10 12:50:05 +01:00
41c51df086
Revert "Recycle old command buffers of immediate command lists"
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This reverts commit 8f93f4f3ec
2022-03-10 09:12:47 +01:00
8f93f4f3ec
Recycle old command buffers of immediate command lists
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Related-To: NEO-6242
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-03-08 14:59:26 +01:00
8f5dd3cff5
Refactor immediate command list flushing
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Related-To: NEO-6242
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-03-07 20:37:28 +01:00
0f54a57910
Update programming STATE_COMPUTE_MODE
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Remove function clearComputeModePropertiesIfNeeded.
If a field has to be programmed unconditionally, ignore isDirty flag.
Related-To: NEO-6728
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2022-03-07 16:23:59 +01:00
82e3b10c5a
Fix typo
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Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-25 18:10:41 +01:00
a2386ad216
Correct programming of implicit args on pre-XeHp platforms
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On pre-XeHp platforms implicit args aren't at the beginning of indirect data,
GPU address of implicit args buffer is programmed within cross thread data
Related-To: NEO-5081, IGC-4710
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-24 20:52:04 +01:00
ea6f089e17
Unify implicit args programming across APIs
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Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-23 11:52:47 +01:00
4b0d986876
Move AllocationType enum out of GraphicsAllocation class
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2022-02-04 17:49:09 +01:00
b697d75695
Correct dimension order in local ids generated for implicit args
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when local ids are generated by HW, use same dim order for runtime generation
move common logic to separated file
Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-02-04 12:46:59 +01:00
dd63f1d2f9
Add new function append3dStateBtd
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Signed-off-by: Katarzyna Cencelewska <katarzyna.cencelewska@intel.com>
2022-02-03 14:42:10 +01:00
8f85d4b8f8
Add debug variable to override message simd.
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Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
2022-02-03 11:07:42 +01:00
9d8ce7aace
Command container appends BB_END on cmd buffer allocation end
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When linear stream created for command container has not enough space
for command and BB_END it will program BB_END and allocate new command
buffer allocation. Pointer returned from getSpace in this case will
return storage from new command buffer allocation.
Related-To: NEO-5707
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-31 16:15:37 +01:00
f8c104feaa
Use fw declaration of IndirectHeap in CommandContainer
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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2022-01-26 13:30:26 +01:00
5e238dc7f1
Unify surface state programming logic related to implicit scaling
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OCL image surface state programming for Xe Hp core is now reusing logic
of EncodeSurfaceState helper
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-25 09:02:28 +01:00
fbc0666d1b
Move setGrfInfo from HardwareCommandsHelper to EncodeDispatchKernel
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unify grf info programming across APIs
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-20 15:42:06 +01:00
5cd76aef6a
Refactor surface state programming, add enum value for default halign value
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Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-19 14:31:28 +01:00
8ebef3769c
Update RENDER_SURFACE_STATE for Xe Hpg
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Program Multi Gpu params in surface state only on Xe Hp Sdv
Respect zero-size image scenario when programming surface state
Move XeHp-only tests to dedicated subdir
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-18 21:06:14 +01:00
c40153ec86
Clarify logic of walk order values for Xe Hp and later
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Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-18 13:36:15 +01:00
4238679078
Refactor implicit scaling device support
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Related-To: NEO-6589
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-18 13:08:43 +01:00
c36c083812
Refactor implicit scaling parameters for surface state
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Related-To: NEO-6589
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-17 09:30:58 +01:00
ff79c84115
Correct INTERFACE_DESCRIPTOR_DATA definitions for XeHp and later
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Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2022-01-14 19:06:55 +01:00
b78bb26cbf
Refactor partitioning of state base address
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Related-To: NEO-6589
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-14 19:06:24 +01:00
9c4f05387b
Refactor partitioning of dispatched kernels
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Related-To: NEO-6589
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-13 22:54:07 +01:00
9785ab7828
Refactor encode dispatch kernel class interface
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Related-To: NEO-6589
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2022-01-13 12:08:38 +01:00
5be4d89b73
Rename function
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Rename MemorySynchronizationCommands::isDcFlushAllowed
to MemorySynchronizationCommands::getDcFlushEnable
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-30 17:03:22 +01:00
205e2e1957
Wait for fence before store cmd buffer in reusable pool
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-12-23 15:36:54 +01:00
f4c151cce5
Refactor PipeControlArgs struct
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Remove struct PipeControlArgsBase
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 17:13:16 +01:00
9a450d1b74
Pass hwInfo to appendMiFlushDw
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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-22 15:22:47 +01:00
0fd685541d
Add isDcFlushAllowed function to HwInfoConfig
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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 18:29:43 +01:00
6d439f88bb
Explicitly set dcFlushEnable value
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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-21 12:21:11 +01:00
66bf806018
Remove magic number from set/getBatchBufferStartAddressGraphicsaddress methods
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rename methods to set/getBatchBufferStartAddress
Related-To: NEO-6466
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-12-16 19:03:01 +01:00
0a139caf77
Use timestamp post sync always for multi tile partitioned walkers
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-16 16:03:16 +01:00
616580637b
Reuse command buffers in L0 command list
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-12-13 14:52:45 +01:00
1107fdfe55
Rename function and remove unused parameter
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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-12-08 22:47:40 +01:00
d5f3ac37bf
Add KernelExecutionType argument to encodeAdditionalWalkerFields method
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Signed-off-by: Rafal Maziejuk <rafal.maziejuk@intel.com>
2021-12-08 12:00:42 +01:00
f20236c7f2
Initial PVC support
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
Related-To: NEO-5542
2021-12-07 10:22:41 +01:00
47dbe359bf
Add command encoder for store data command
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-02 20:56:07 +01:00
3e1023fa1a
Unify memory layout for all multi tile post sync operations
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-12-02 18:00:40 +01:00
8b233f7f45
Support for bindless mode in L0 - improvements
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Related-To: NEO-6448
- add new IGC compilation flag when bindless mode used
- fix SBA programming of BindlessSurfaceStateSize -
always set maximum surface state count
- fix residency of global DSH heap on gen9 - gen12lp
in bindless mode
- add L0 aub test with bindless kernel - disabled
- partial fixes in OCL aub tests
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2021-12-02 16:30:58 +01:00
55959d4d1d
Helper method to check if allocation is compressed
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-12-02 16:13:53 +01:00
cb8a17f393
Initialize partition registers only once
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-29 14:43:53 +01:00
1da896bee0
Add debug key to override implicit scaling API support
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-25 15:50:25 +01:00
91dfa5c2ac
Initial DG2 support
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-11-19 10:01:29 +01:00
7ea0a11c0a
Unify programming of partition registers
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-18 16:52:51 +01:00
76b8f6296f
Move noop programming to dedicated encoder
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-18 10:28:56 +01:00
3b556a5e44
Add post sync capability to implicit scaling barrier
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-17 12:08:52 +01:00
23a7ab7593
Refactor implicit scaling barriers to add more cache flush options
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-04 17:56:12 +01:00
b2124f43b8
Add implicit scaling barrier implementation
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-03 12:23:42 +01:00
4fbb199790
Add platform parameter to configure pipe control dispatch
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-11-02 12:14:10 +01:00
ad8e640545
Reorganize implicit scaling files
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Related-To: NEO-6262
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-10-29 16:15:00 +02:00
f20cdac7d3
Zebin: add support for has_dpas
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Signed-off-by: Krystian Chmielewski <krystian.chmielewski@intel.com>
2021-10-28 09:59:21 +02:00
9d56939980
Refactor creation of buffer surface state 1/n
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-10-21 13:11:31 +02:00
4768be244b
Cache post syncs.
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Signed-off-by: Michal Mrozek <michal.mrozek@intel.com>
2021-10-13 15:57:13 +02:00
5d2d81b2d1
Use uint64_t instead of void * in indirect dispatch programming
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-06 18:37:36 +02:00
92bf4b978a
Implement implicit args for indirect dispatch
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Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-06 16:10:41 +02:00
ae340ff6f5
Add L0 aub tests for indirect dispatch
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Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-05 21:05:40 +02:00
0b64ecba3f
Pass active partitions from dispatched kernel to context
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Related-To: NEO-6244
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-10-05 14:57:47 +02:00
b891ec2588
Correct cross thread data GPU address in indirect dispatch programming
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Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-10-04 14:59:41 +02:00
897420236a
Add method to set systolic mode
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Resolves: NEO-6040
Signed-off-by: Szymon Morek szymon.morek@intel.com
2021-09-30 10:39:56 +02:00
4ba4c32766
Remove SBA->IOH programming on XE_HP_SDV
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-09-29 12:35:43 +02:00
3b35ba504f
Adapt command stream receiver to multiple active partitions
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Related-To: NEO-6244
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-09-23 14:32:20 +02:00
d2a776bcc6
Remove L3 flush from postSync
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Related-To: NEO-6111
Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2021-09-22 17:49:58 +02:00
2bf08aaa67
Set compression format for AUX_MCS_LCE mode
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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-09-20 17:08:22 +02:00
c73f10c2be
Extend multi tile debug flags to state compute mode command
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-09-17 09:11:37 +02:00
eda3531729
Rename functions and variables in Implicit Scaling
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Related-To: NEO-6244
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-09-16 17:58:35 +02:00
b65d8909e4
Refactor and modularize walker partition code
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Related-To: NEO-6244
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-09-16 10:46:26 +02:00
5a59a6ad2e
Add support for implicit args in L0
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Related-To: NEO-5081
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-09-15 11:12:23 +02:00
e348001399
Adjust PIPELINE_SELECT programming on tgllp
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Signed-off-by: Sebastian Luzynski <sebastian.jozef.luzynski@intel.com>
2021-09-10 13:37:20 +02:00
a924b6a304
Code cleanup - avoid copy 5/n
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Signed-off-by: Kamil Kopryk <kamil.kopryk@intel.com>
2021-09-08 08:59:55 +02:00
55723d0b18
Remove redundant functions
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Remove EncodeStates::adjustStateComputeMode function.
Unify CommandStreamReceiverHw::programComputeMode functions.
Related-To: NEO-5995
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-09-07 16:13:50 +02:00
6b299a3ab0
Make partitioned post sync operations for partitioned workloads
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-09-03 20:20:29 +02:00
0345d9f707
Improve queries with number of SubDevices
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-09-01 14:01:57 +02:00
e7085fdafc
Remove helper to get compression format for stateless compression in SBA
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Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2021-08-27 11:28:53 +02:00
856dee2b08
Improve Sampler programming
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-08-25 19:47:30 +02:00
54cf561e09
Add helper to get compression format for stateless compression on XE_HP_SDV
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Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2021-08-25 16:56:40 +02:00
29c64c3dd0
Disable implicit scaling for cooperative kernels
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When implicit scaling is disabled use useSingleSubdeviceValue = true.
Resolves: NEO-5757
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-08-18 14:56:37 +02:00
aa5e1780a2
Rename plus in filenames to and_later
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Related-To: NEO-5920
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2021-08-17 11:26:27 +02:00
945a7cf905
Revert "Add method to set systolic mode"
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This reverts commit 7ad007e
2021-08-16 16:41:05 +02:00
a85ae676e7
Rename plus in cmake macros to and_later
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Related-To: NEO-5920
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2021-08-13 11:40:19 +02:00
7ad007ec92
Add method to set systolic mode
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Resolves: NEO-6040
Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2021-08-11 09:09:59 +02:00
dbf9198186
Flush tlb on BCS direct submission
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Signed-off-by: Lukasz Jobczyk <lukasz.jobczyk@intel.com>
2021-07-30 16:26:47 +02:00
99caeaebf6
Fix allocation properties when allocating next command buffer
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Signed-off-by: Kacper Nowak <kacper.nowak@intel.com>
2021-07-30 15:19:52 +02:00
1a7c9e63fa
Add method to set force non coherent
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Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2021-07-23 11:18:04 +02:00
37c0501f1c
Add atomic move for native cleanup operations
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Related-To: NEO-5848
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-07-15 15:49:22 +02:00
c389db6f1c
Add space calculation for SBA instruction
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Signed-off-by: Sebastian Luzynski <sebastian.jozef.luzynski@intel.com>
2021-07-13 12:19:30 +02:00
fc4a1d608d
Refactor immediate command list with kernel operations to use flushTask().
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This is applicable for submissions with sync & async command queue modes.
Related-To: LOCI-1988
Signed-off-by: Vinod Tipparaju <vinod.tipparaju@intel.com>
2021-07-07 15:31:38 +02:00
d7a2a62ded
Add additional StateBaseAddress cmd wa
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Resolves: NEO-5982
Signed-off-by: Sebastian Luzynski <sebastian.jozef.luzynski@intel.com>
2021-07-06 11:53:47 +02:00
62f89b174a
Add work_dim patching to l0 kernel
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Related-To: NEO-5931
Signed-off-by: Dominik Dabek <dominik.dabek@intel.com>
2021-07-05 20:09:20 +02:00
2acc0fb3f6
Add memory backed buffer allocation for L0 ray tracing.
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This allocates the buffer on a per-device basis and enables ray
tracing on devices that support it when given a kernel with ray
tracing calls.
Signed-off-by: Jim Snow <jim.m.snow@intel.com>
2021-07-02 11:56:18 +02:00
7ee9d279c8
Set correct allocation after reseting command container
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-07-01 16:46:35 +02:00
95966711fe
Reorganize sync commands in static partitioning
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-07-01 11:50:06 +02:00
1a042af9c6
GmmClientContext cleanup
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-06-29 12:01:07 +02:00
96d14967ac
Partial support for XE_HP_SDV
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-06-24 18:35:54 +02:00
72d124e275
add function to append params for image from buffer
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-06-24 13:33:43 +02:00
99c0f02e12
Update StateComputeModeProperties
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Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-06-18 12:25:16 +02:00
0e5ca243e2
Add notify enable parameter to post sync commands
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Related-To: NEO-5845
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-06-17 19:22:51 +02:00
a481c28e55
Program GPU atomics on stateless kernels for L0
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Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
2021-06-17 18:57:35 +02:00
3ed0f074af
Add method to set compression flag
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Signed-off-by: Szymon Morek <szymon.morek@intel.com>
2021-06-10 12:27:24 +02:00
4fa5041f27
Add inline directive to smallest functions
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-06-10 09:27:07 +02:00
689ceacfe6
Fix set allocation adress in SS when offset is patched
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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-06-08 13:05:38 +02:00
573d01f085
Update StreamProperties
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Update ThreadArbitrationPolicy enum.
Remove adjustThreadArbitionPolicy from CommandStreamReceiverHw.
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-06-08 10:05:05 +02:00
8f91fcdd73
Add new atomic operation
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Related-To: NEO-5244
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-06-04 09:00:11 +02:00
7eb81e9d85
Unify StreamProperties structs
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Introduce functions allowing to copy values from one struct to another,
while correctly setting values of isDirty field.
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-05-27 15:37:14 +02:00
1281e858df
Disable compression flags when image is not compressed
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Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-05-27 12:05:52 +02:00
0f32231fc8
Use correct INTERNAL heap base address for ISA in system memory
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Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
2021-05-25 10:22:28 +02:00
d693d24f27
Add StateComputeModeProperties to StreamProperties
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Related-To: NEO-4940, NEO-4574
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2021-05-21 16:39:39 +02:00
159404f38e
Revert "Program border color once per dsh"
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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-05-18 12:26:58 +02:00
171a614f18
Fix reset border color offset when replacing heap buffer
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Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-05-05 13:38:02 +02:00
b943ad078f
Program border color once per dsh
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Related-To: NEO-4928
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
2021-04-30 13:31:58 +02:00
53104e0830
Add a parameter to the encode function
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Signed-off-by: Daria Hinz <daria.hinz@intel.com>
2021-04-22 12:07:16 +02:00
e5eba8be53
Add setters and getters for coherency type in render surface state
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Signed-off-by: Milczarek, Slawomir <slawomir.milczarek@intel.com>
2021-04-13 16:12:46 +02:00
bd32518d31
Add extra parameters to EncodeComputeMode::adjustComputeMode() method
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Signed-off-by: Igor Venevtsev <igor.venevtsev@intel.com>
2021-03-31 16:51:55 +02:00
8215395401
Simplify Context method
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return if context has multiple sub devices related to a given root device
Related-To: NEO-3691
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2021-03-30 10:22:15 +02:00
e36941b171
Change argument type in EncodeMemoryPrefetch class
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Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
2021-03-25 18:27:07 +01:00
f9197d4e0d
Improve memoryPrefetch method
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Signed-off-by: Bartosz Dunajski <bartosz.dunajski@intel.com>
2021-03-24 15:12:05 +01:00
Zbigniew Zdanowicz