Commit Graph

1350 Commits

Author SHA1 Message Date
526a3a664b Adding new tool for decoding and encoding OCL binary.
Decoder decodes the binary to kernel heaps and patch token data, which
is in a human readible form. Encoder encodes it back to binary form.

Change-Id: Id07b1294ba24360e90c824171741cf14bd43cfad
2018-10-05 12:18:18 +02:00
bb62343aba Add new parameter to thread data dispatching
Change-Id: I86710b0cc764156f4c2db9d24ccd1c96b32d7660
2018-10-05 12:06:25 +02:00
73b2e947a5 Multiple TimestampPackets handling
Change-Id: Ia5936c3d0a34b892aa4444026a5aebc681f126c2
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-10-05 01:54:35 +02:00
bc4700a193 Add OsContext argument to MemoryManager::makeNonResidentEvictionAllocations
OsContext has to propagate through following calls first:
- WddmCommandStreamReceiver<GfxFamily>::processEviction
- CommandStreamReceiver::makeSurfacePackNonResident

Change-Id: I7559c7406b2860c51905c9961cec251fac231b08
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-10-05 01:28:31 +02:00
2d7077e138 Fix correct command buffer estimation for non-kernel enqueue calls
Change-Id: I8655d1824c229f13104e085f55fa15c310a17210
2018-10-05 00:47:54 +02:00
2110ba6ca4 Passing correct taskCount to waitForTaskCountAndCleanAllocationList
Change-Id: Ib0d2474bcd5827f8030331f7ef45ffc2805b955b
2018-10-04 23:53:43 +02:00
5976cef692 fix naming convention in mock_gmm
Change-Id: I0173d2f4413b8dc56788c9a2d065221d10070878
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-10-04 22:59:31 +02:00
6a3bbc002e Set correct flags for tiling when platform doesn't support y tiling
Change-Id: I39de5c91aafb9099d799c3323016df692cab349c
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-10-04 22:55:11 +02:00
77bbd2b89b Don't access command stream receivers when vector is empty
Change-Id: I1011b94be1ec7f28b71659c27b09b93e577769e2
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-10-04 22:42:38 +02:00
61000c0dd4 CSR AUB + HW mode - flush to poll MMIO for completion
Ensures that each submit of LRCA be serialized through the simulator
like it is for AUBs captured in the standalone mode.

Change-Id: I1e3ad500012dce960d0e64b56af1cb60142772da
2018-10-04 10:32:08 +02:00
a73801097f Change LRCA initialization
- program Debug register

Change-Id: I9993263b94fac0c56126f550fe174792dba6744b
2018-10-04 03:43:40 +02:00
9c3d89dc36 Fixes for aub tests
- remove unnecessary createAllocationAndHandleResidency calls
for hostptr memory used for buffers
- expect data under correct GPU VA from GraphicsAllocation in
AUBReadBuffer test

Change-Id: Ida8f3bbf4f2f5d27535f56952079528472992f0b
2018-10-04 01:01:50 +02:00
599f6e28ef reuse gmmlib dynamic library when target is present and already built
instead of copying gmmlib shared library into our build build folders we
can use LD_LIBRARY_PATH to use .so file located in original location.

Change-Id: Icf8ae4000032c0032866e940a243a7f5881a4c16
Signed-off-by: Artur Harasimiuk <artur.harasimiuk@intel.com>
2018-10-04 00:15:41 +02:00
2cd411227c Improve PageTableManager creation
Change-Id: If359c76ae880fb2e1f56fc561aca761530787b5e
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-10-03 22:37:05 +02:00
b602cd2bb8 Pass execution environment to memory manager
Change-Id: If43cf9d1353b4cbc02ea269fb9105c01cc4e0876
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-10-03 22:12:26 +02:00
84865512cd Scheduler cannot utilize scratch space.
Change-Id: Ib3e6e3aef711477f800ae437c59eb7340a481510
2018-10-03 21:59:11 +02:00
3fdb17bc7f Move hw specific GpgpuWalkerHelper functions to separate file
Change-Id: If2e793d0c3de1a5245bbdee065111a504807b134
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
18.40.11622
2018-10-03 20:19:47 +02:00
ce29770d61 Extend PhysicalAddressAllocator with page size and alignement
- this allows for reserving 64k pages or bigger with specified alignement
if required

Change-Id: I256d6c0d9e7fee0e2bac5f4ab5e4fd49ea9d8d50
2018-10-03 20:02:58 +02:00
ec48ccecdb AUB CSRs to use a shared address mapper (CPU VA to GTT VA)
This commit moves address mapper from CSR to execution environment
in order to generate unique GTT VA for LRCA, HWSP and ring buffer
between different CSRs.
Additionally, moved the rest of AUB file stream tests to separate module.

Change-Id: I02ae44202c0255277a7ac17532485419e0c403ab
2018-10-03 12:50:25 +02:00
5f11e68861 Add EngineType suffix to aub file name in AubFixture
Change-Id: I9b8f27461e6d36d596e85fde973aa1b2f34dbede
2018-10-03 01:56:36 +02:00
9a1adc3095 Remove scenarios with memory manager with null csr
Change-Id: Ie151bf3d16c5d994f154c8f9ac3db43702a4798c
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-10-02 21:43:21 +02:00
2632b21fd1 Organize dispatching of thread data for better reuse of code
Change-Id: I8c156f8b5a50f6fa4dfb5218cdadb2840ff556eb
2018-10-02 18:47:13 +02:00
95cfb156cf ULT renaming: clCreatePerfCountersINTEL tests
Change-Id: I3c32be2317fbdad6522b3f160077732fd0ec55c7
Signed-off-by: Cetnerowski, Adam <adam.cetnerowski@intel.com>
2018-10-02 18:23:00 +02:00
caa477115f Remove support for static gmmlib
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>

https://github.com/intel/compute-runtime/pull/91

Change-Id: I90184d7aabf3dd0d8a74ff40115213241b4ca724
2018-10-02 18:21:51 +02:00
c75dc23b6e Change HWCMDTEST_F() tests to HWTEST_F() where possible
Change-Id: Ibfe147a12b53f832723f83809770e1b203159f8f
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2018-10-02 17:29:46 +02:00
6dfcb913f0 dependencies update
Change-Id: I5f9e9098a1b410211ee83f903faaa9b631ea8896
2018-10-01 15:52:22 +02:00
b16bd14f37 Change virtual class HardwareInterface to static
Change-Id: I4f1f59ecb51b95041dc6dcc6c606b94595813f53
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
2018-10-01 15:11:43 +02:00
f3b1d73e88 Add missing include
Change-Id: I3384f2d599941cfd96bbe93559ebfb323f6eb285
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
2018-10-01 10:12:10 +02:00
2227386eb7 CSR with AUB dump to call makeNonResident on AUB CSR
AUB CSR can implement additional actions to be taken on makeNonResident
such as dumping buffer and image resources.

Change-Id: Iab76081116011e0882de3c902db74a5dc4dd0b36
2018-09-29 00:23:40 +02:00
41e8d70363 Change makeSurfacePackNonResident argument to a reference
Change-Id: Ic95ad2406184e91a78c152fad3fe6f0f4ebb24ae
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-09-28 18:08:18 +02:00
4ea9f496d5 Fixes for AUBs
- pass aub usage in MockDevice to memory manager
- disallow mapping on cpu for cpu inaccessible memory

Change-Id: I5437a06efd4dd32940b603a15ff98a40091e2b04
2018-09-28 15:55:55 +02:00
90b21644ae ULT renanming: clCreatePipe tests
Change-Id: I70c67e41abf89f7f5a521d30c42ba143914bfb17
Signed-off-by: Cetnerowski, Adam <adam.cetnerowski@intel.com>
2018-09-28 11:32:35 +02:00
ea9e7bea31 Change MemoryManager::lastPeriodicTrimFenceValue to a vector
Also start registering OsContext to MemoryManager in
WddmMemoryManagerResidencyTest along with some cleanup in fixture's SetUp

Change-Id: I3f6763ae0cd9bf638cdc5dbbfbc60dfb0fd0ef05
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-09-28 06:33:12 +02:00
cbd017d495 Handle TimestamPacket with implicit dependencies ownership
Change-Id: I22a4de4e9eb904c359583e235e0de54a7c743e07
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
2018-09-28 01:48:02 +02:00
7ddf1d554b Move getAddressSpace from AUB & TBX CSRs to CSRSimulatedHw
Change-Id: Iaa6164445f55efba3681fc41e2ec614f999e1362
2018-09-27 10:43:00 -07:00
7a3515e882 Remove filename duplication
Change-Id: I570f8904ba2ca7b9f8509af33a8a29dcec424e3b
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
18.39.11595
2018-09-27 18:45:28 +02:00
2ad5108380 Clarified dependencies in Context::getSupportedImageFormats
Change-Id: Iaa09a2b572b3ae6d0533378f0ecf227bd90b1a10
2018-09-27 18:41:18 +02:00
65565acdaf Refactor Buffer::create
- simplify conditions by separation
- reorder some calls
- pass allocateMemory to AllocationFlags

Change-Id: Iab6fd35f9b9c10bfbc19058e69058346ef87dad8
2018-09-27 18:16:54 +02:00
330b9eddbd Upload data to cpu inaccessible memory with enqueueWriteBuffer
Change-Id: Ibb33c4248fd0cb4338c82a9deb3994147c0acba5
2018-09-27 18:09:01 +02:00
e06aa17dfc Grf configuration
Change-Id: I3741f53a38c6707b0c8ad82ae553ea65ae6917e4
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
2018-09-27 17:57:19 +02:00
a81b1a461f ci: use LP ocl-dev account for ubuntu 18.04 builds on Travis
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>

https://github.com/intel/compute-runtime/pull/92

Change-Id: I1ecf19664fc29f61662ffc012d2154f2ee74e715
2018-09-27 11:24:07 +02:00
04e083120e Append gmmlib to neo package
Change-Id: I39e94700a3113e12e7be72ba10eaef18ff7f6217
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
2018-09-27 08:06:09 +02:00
465e1a3165 Fixes for AUBs
Change-Id: Iac55927eb96db8dd68b86d21e66392039ba1f058
2018-09-27 06:38:19 +02:00
64c891f0fd Use specific address for Allocator32Bit in AUB CSR
Change-Id: If3fd466fcfea21c1967b10def57acf67ccfdc5e6
2018-09-26 16:01:07 -07:00
efdbde245a AUB CSRs to use a shared physical address allocator
This commit introduces AUB-specific control class to execution environment.

Change-Id: I525c9c93a4f10f769dbedb7d097674c35693f0b1
2018-09-26 20:31:56 +02:00
6aab39fd9b Move MMAllocateInPreferredPoolTests to inl file
Change-Id: I08dc6dfedbd4c970174377454fdac112cbf29f48
2018-09-26 19:30:35 +02:00
51e888dfc7 Add new arguments to GpgpuWalkerHelper<GfxFamily>::setGpgpuWalkerThreadData
Change-Id: I19e42a75f5224f6e3588c2c7be4a3451714bb5ef
2018-09-26 14:56:01 +02:00
9e8a434464 Add new parameter to dispatch payload data
Change-Id: I0034c5a40de65a050e19691b13793b7053354757
2018-09-26 14:43:46 +02:00
5e3df9559a ci: use LP ocl-dev account for CI builds on Ubuntu and Arch
Signed-off-by: Jacek Danecki <jacek.danecki@intel.com>

https://github.com/intel/compute-runtime/pull/90

Change-Id: I987f691dfe1258b7353ca1eda502994145babd5b
2018-09-26 13:21:03 +02:00
95e4dc4152 Delete unneeded residency/eviction allocations mutators
Change-Id: Ic73ea4c4e3ebf422f935a440a1b4789fe1c15494
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
2018-09-26 13:02:19 +02:00