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274 Commits

Author SHA1 Message Date
Mrozek, Michal 387fdc5682 Make sure that timestamp is properly connected to mapBuffer event. 
Related-To: NEO-2317

Change-Id: I607211e9e8bb05e0c4103a10087c10f6959f2008
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-04-04 11:36:06 +02:00
Filip Hazubski b2e16b7897 Update allocationForCacheFlush method 
Related-To: NEO-2535

Change-Id: Ia24556814188263e2ebb54b6419feddd5d8ed707
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-04-03 18:07:13 +02:00
Mateusz Jablonski f76c0e84fb Don't copy compressed buffer on CPU 
Change-Id: I9c36ee8f23284286bb846fd9a0fd196733d0f8f9
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-04-03 13:15:41 +02:00
Mrozek, Michal 4cb060fc46 Remove not needed code. 
Change-Id: Idcbc53f22cc3a3f1c3acb4b2a620372d6102b12b
Signed-off-by: Mrozek, Michal <michal.mrozek@intel.com>
 2019-04-03 12:17:53 +02:00
Mateusz Jablonski f3d17008ee TransferProperties: lock resource only when transfer on CPU is requested 
Change-Id: Ic93b4fd438e75f5d54cbae9bec332c4b18c6b1ee
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-04-01 14:02:49 +02:00
Jobczyk, Lukasz a025dc6985 Reverse logic of creating Memory Manager - part 6 
-Remove a redundant condition from the MemoryManager constructor

Change-Id: I4b6c56f30a19e77a7a20f68c6d85516aaa52d102
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-04-01 10:27:29 +02:00
Mateusz Hoppe 4296588aa9 Use GPU address to compare with SurfaceBaseAddress in ULTs 
- remove redundant casts

Change-Id: I175801869f24be47dc6703b61bf26c0f8a1c77c6
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2019-03-26 20:49:54 +01:00
Maciej Plewka 9e52684f5b Change namespace from OCLRT to NEO 
Change-Id: If965c79d70392db26597aea4c2f3b7ae2820fe96
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-03-26 15:48:19 +01:00
Filip Hazubski cdd46679c8 Add getIntelQueueInfo helper function 
Change-Id: I5daed24c36db8f5da143db8665b4353582dbc94b
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-03-26 11:31:35 +01:00
Mateusz Hoppe 047f2bec87 Program correct addresses in EnqueueReadWriteBufferRect scenarios 
- SurfaceBaseAddress should be programmed with aligned address
this was not the case for certain origin and region values
- offset from aligned address added to operationParams

Change-Id: I0742b826dd0b70f0a6dedf436b850734fa015688
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2019-03-26 10:37:46 +01:00
Mateusz Hoppe c5ddf11e78 Use GPU address in EnqueueCopyBufferToImageTest 
Change-Id: I2724fb9f2cac9222cacfff913e648df1d1531ccd
Signed-off-by: Mateusz Hoppe <mateusz.hoppe@intel.com>
 2019-03-26 08:38:04 +01:00
Maciej Dziuban 33c07c875f Do not insert PipeControl WA or DC Flush when not needed 
Change-Id: I71030273708f243324a566232528bce00a0361df
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-03-22 12:37:27 +01:00
Stefanowski, Adam 16aee8cc46 [2/n] Move Hardware Info to Execution Environment 
- remove hwInfo from the csr functions where it was passed as a parameter,
now csr functions have access to hwInfo by Execution Environment

Change-Id: I756ae63d9728c9c963571147bab97f9e1c15797b
Signed-off-by: Adam Stefanowski <adam.stefanowski@intel.com>
 2019-03-22 10:08:26 +01:00
Mateusz Jablonski 395e79fee8 Add support for many GMMs in Graphics Allocation 
Change-Id: I955b8dd50b502f91700c5529d0a0a291632aa157
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-03-13 15:44:45 +01:00
Koska, Andrzej fcdfcb3fc4 Pass enqueued values to enqueueHandler 
Change-Id: I991818657c7cafaf8911ce711a87a6c7b4531517
Signed-off-by: Koska, Andrzej <andrzej.koska@intel.com>
 2019-03-13 11:23:37 +01:00
Piotr Fusik ec72787b98 Remove MemoryManager::allocateGraphicsMemoryForHostPtr. 
Change-Id: I629f2299a183fc135135dbaff89216b966554a95
Signed-off-by: Piotr Fusik <piotr.fusik@intel.com>
 2019-03-12 15:51:32 +01:00
Maciej Plewka e53a8e8709 Add postSyncAddress to flush after walker 
Change-Id: I7fdfaf8e0acc365998cc74306ab715ea3d9c7d72
Signed-off-by: Maciej Plewka <maciej.plewka@intel.com>
 2019-03-04 14:47:53 +01:00
Zbigniew Zdanowicz 10a25e405a Remove debug flag ForceMultiEngineQueue 
Change-Id: Iabf38999a03be3422c25c12978808731df77a899
Signed-off-by: Zbigniew Zdanowicz <zbigniew.zdanowicz@intel.com>
 2019-02-28 16:06:36 +01:00
Mateusz Jablonski 6fb28dd828 Refactor GraphicsAllocation class 
move most of members to protected section
merge related members into structs

Change-Id: Ief2e092aa5e61ca6f13308f9d9b1937ea6c913b4
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-02-28 14:09:11 +01:00
Filip Hazubski 8b57d28116 clang-format: enable sorting includes 
Include files are now grouped and sorted in following order:
1. Header file of the class the current file implements
2. Project files
3. Third party files
4. Standard library

Change-Id: If31af05652184169f7fee1d7ad08f1b2ed602cf0
Signed-off-by: Filip Hazubski <filip.hazubski@intel.com>
 2019-02-27 11:50:07 +01:00
Hoppe, Mateusz 432b8f20a7 Allow cpu copy with debug keys only when ready waitlist events 
Change-Id: If9293787c76b8248a84e25d03cbf9a9b5aaf7cca
 2019-02-22 17:39:57 +01:00
Maciej Dziuban 90e970cee6 Create GraphicsAllocation during dispatch when queue is blocked 
Change-Id: I8a6f9e14ff57e7ed2920260af291317805f4df13
Signed-off-by: Maciej Dziuban <maciej.dziuban@intel.com>
 2019-02-21 15:28:17 +01:00
Katarzyna Cencelewska c9a8f9b1be GlSharingFunction tests update 
Add mock of opengl32.dll to check that sharing functions are loaded

Change-Id: I361707ee9a506e84db51d4fa9c98823db2550fae
 2019-02-20 16:05:32 +01:00
Mrozek, Michal 4139e88982 Allocate command buffers with proper allocation type. 
Change-Id: I912dd41cf68fa16ab481bb003c4f5ae63f1f04c4
 2019-02-20 12:52:45 +01:00
Jobczyk, Lukasz 2bcecf3e62 Align command buffers to 64KB 
Change-Id: Id1fbd7c6f1aee48c4b69ec305d5332cb0aa86507
Signed-off-by: Jobczyk, Lukasz <lukasz.jobczyk@intel.com>
 2019-02-18 09:58:45 +01:00
Mrozek, Michal 0e7fd2ffed Add multiEngine field to command queue with debug variable to override it. 
Change-Id: I3c1e424a7ad545e166e178d1726595e6d9502ca7
 2019-02-12 12:22:24 +01:00
Kamil Diedrich a7b46ccdbd Add RAII for cl_objects 
- add removeVirtualEvent to cmdQueue fixture
- add const keyword in event functions

Change-Id: I11354eb8fceb15ae2c58bddd327863a15aab6393
 2019-02-12 11:19:35 +01:00
Venevtsev, Igor 5e8fb19e5d Remove OCL Events concept from EnqueueOperation and dispatchWalker 
Change-Id: Iec55b0be673a2a40b9621212add224a33d4abc5d
 2019-02-12 08:46:18 +01:00
Kamil Diedrich 89410a6733 Add DCFlush before resolving 
Change-Id: Id5f82edc4631aa16baa55b26b8bde69f4a30572c
 2019-02-11 16:33:34 +01:00
Dunajski, Bartosz dc181defba Use GpuAddress for TimestampPacket programming 
Change-Id: I1303605c33e2e0267a1716e12a0bfcb341fcfbd7
Signed-off-by: Dunajski, Bartosz <bartosz.dunajski@intel.com>
 2019-02-11 15:31:17 +01:00
Chodor, Jaroslaw 43856e88b5 Refactor around cache flush and command queue 
Change-Id: I277e27cbc60fbbb015c0024f171697408879ec0b
 2019-02-10 17:59:33 +01:00
Kamil Diedrich e1eab521e7 use release for cl-objects instead of delete 
- fix for data race in events
- modification of the addition child event

Change-Id: I6ea3a413f13f13a91d37d20d8b9fad37d0ffafb9
 2019-02-05 14:09:32 +01:00
Hoppe, Mateusz 3c47c418a9 Refactor HardwareParse::getSurfaceState() to return CPU memory 
- if SSH indirectHeap is passed, use CPU address instead of GPU
address programed in SBA command

Change-Id: Id2c8973db0dfe2d9562ee835a27c4d3c28ea3351
 2019-02-04 17:49:00 +01:00
Hoppe, Mateusz 509ed273c4 Refactor Ults finding hardware commands 
- use CPU address for found dynamicStateHeap address in
StateBaseAddress command

Change-Id: I2d857c5a069f5a8f46169d2047cdb27efd3502b8
 2019-02-04 17:26:37 +01:00
Mateusz Jablonski ce4a75e121 Require same allocation type when obtaining reusable allocation 
Change-Id: I829301b83a6214bcfb4fc9f2692f21ae9a002456
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-02-01 16:10:28 +01:00
Koska, Andrzej 395d053f02 Limiting the value of LWS to the value of GWS 
Change-Id: I24e89125e586ed77d396ba9e40dd039f1ab213fe
 2019-02-01 12:49:54 +01:00
Mateusz Jablonski f157943610 Allocate internal allocations through preferred pool 
Change-Id: Ib17431ceefc1eb72f86625e0998f679baaa7cb0d
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-30 11:18:15 +01:00
Chodor, Jaroslaw 311de0c644 Adding support for excluding tests per platform 
Change-Id: I5c41cadd0f44d05640593673f1c00da84d428711
 2019-01-30 01:37:10 +01:00
Milczarek, Slawomir b11e0825c9 AUB capture with support for allocation dumps 
Change-Id: I90a2b75043c33af92e4557be37cde4b9699582c6
 2019-01-28 21:20:08 +01:00
Mateusz Jablonski 128bf4552f Remove debug flag ForceResourceLockOnTransferCalls 
Unlock locked resoures in freeGraphicsMemory method

Change-Id: I2baae7b7f9d8260f19a4b083849c5bf0d1a764f3
Signed-off-by: Mateusz Jablonski <mateusz.jablonski@intel.com>
 2019-01-25 14:03:29 +01:00
Zdanowicz, Zbigniew 158f200476 Add HW commands const definitions 
Change-Id: If2e9d7f7f707b7b8c7bd8dbd3853ab3b6dad0c9a
 2019-01-18 12:13:25 +01:00
Pawel Wilma 14e8fdd8f8 Fix for incorrect timestamp offset calculation in event profiling info 
Change-Id: I634c29daf4734b24e4075542dc6550c531977f0a
Signed-off-by: Pawel Wilma <pawel.wilma@intel.com>
 2019-01-11 16:39:05 +01:00
Mrozek, Michal ef73bb8c11 Move Walker specific code to dedicated method. 
- move cache flushes after the Walker.

Change-Id: I58c5e76bad22ac42da2c466ef008ef5bf96df077
 2019-01-10 16:36:56 +01:00
Hoppe, Mateusz cbc4d349a8 Do not align down pointer passed to hostPtr allocation 
- do not align up hostPtr allocation size
- align BaseAddress programmed in SurfaceState to DWORD

Change-Id: Ic6d02e53fd13dda881f8eb845a131bffe4deb45c
 2019-01-08 21:21:34 +01:00
Zdanowicz, Zbigniew 767f27a483 Add calculation of default SSH size in ULTs 
Change-Id: I682f7cc671ab18de7a9976e0034842df0f6134bf
 2019-01-04 09:28:21 +01:00
Venevtsev, Igor 73a63c7689 Fix Read/WriteBuffer for unaligned offsets 
Change-Id: I08d33e80243f41174f4629c8a611e286629d2e10
 2018-12-31 14:50:07 +01:00
Kamil Diedrich fad2f8dbd1 Change auxTranslationDirectory 
Change-Id: I5d433d340e945b799dbec25a22fd610312f00c0a
 2018-12-28 16:46:42 +01:00
Kamil Diedrich 4b1871bf0e Add pipe control before and after buffer translation 
Change-Id: I4ee32c410e1ac2bcdb3ceae203cd461de79146a5
 2018-12-20 09:30:53 +01:00
Mrozek, Michal b99cf6c3ff Image / Buffer refactor. 
- do not use redescribe flag for image/buffer from other image/buffer.
- use redescribe flag only when image is redescribed via redescribe interface
- remove image specific functions from mem object
- remove redundant fields
- add new implementation of isImageFromBuffer/isImageFromImage basing
on associated mem object.
- pass associated mem object to redescrbed images.
- remove redundant setters

Change-Id: I267637a48fbc2afdad9a9f5e5e9ccd6bd0c09972
 2018-12-19 21:21:44 +01:00
Zdanowicz, Zbigniew 3dca095ccf Add cache flush command after WALKER command 
Change-Id: I3983dc6c0797047e17cc8189655a22a22e85892b
 2018-12-19 13:15:33 +01:00